JP2825217B2 - Flash memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory for executing an erase program in order to prevent excessive erasure during erasure.

[0002]

2. Description of the Related Art In a flash memory, a floating gate is provided in a memory cell transistor, a high voltage is applied between a control gate and a drain, and hot electrons generated near a drain junction are injected into the floating gate. , A semiconductor memory device that stores (writes) information. This flash memory uses an ultraviolet-erasable EPROM [Erasable and Progra
mmable Read Only Memory] while achieving the same low chip cost,
Since it can be electrically erased similarly to M [Electrically EPROM], it has recently been widely used as a rewritable nonvolatile storage device.

In the flash memory, as shown in FIG. 4, control gates and drains of a large number of memory cell transistors 1 having floating gates are respectively connected to word lines W1 to Wm and bit lines B1 to Bn arranged in a matrix. At the same time, the source is connected to a common source line S. Each word line W1 to Wm is connected to a word line selection circuit 2
(Row decoder). The word line selection circuit 2 is connected to word lines W1 to W1 according to an external address.
This is a circuit for selecting Wm. Also, each bit line B1 to Bn
Are connected to a data line D via a bit line selection circuit 3 (column decoder). This bit line selection circuit 3
Is a circuit for selecting the bit lines B1 to Bn according to an external address and connecting to the data line D. The data line D is connected to the sense amplifier 4. The sense amplifier 4 amplifies the signal read on the data line D,
This is a circuit for determining the value of “0” or “1”.

When the flash memory having the above configuration erases written data, a high erasing voltage (12 V) is applied to the source line S and the word lines W1 to Wm are erased.
Is set to a potential equal to or lower than the ground level. Then
A large potential difference is applied between the source and the control gate of the memory cell transistor 1, and electrons in the floating gate are drawn to the source as an F / N current due to a tunnel phenomenon through the insulating film, thereby erasing stored data. Will be

However, the threshold voltage of the written memory cell transistor 1 is generally higher than 5 V,
The threshold voltage of the memory cell transistor 1 in the erased state is about 1 V to 3 V, and the amount of electrons stored in the floating gate greatly depends on whether or not the data is written. Therefore, if these memory cell transistors 1 are collectively erased as they are in a chip unit or a block unit, the memory cell transistors 1 which were originally erased will be over-erased. Since the memory cell transistor 1 in the over-erased state has a threshold voltage of 0 V or less, a leak current flows between the drain and the source even if the control gate is set to 0 V, and the same bit line B1 To Bn, which hinders the normal read operation of the other memory cell transistors 1 connected to.

Therefore, conventionally, when erasing a flash memory, an erasing program for writing into all the memory cell transistors 1 to be erased has been executed in advance. When writing is performed by the erase program, the threshold voltage of all memory cell transistors 1 is 5 V
As described above, excessive erasure can be prevented. The write operation by the erase program is usually performed for each memory cell transistor 1. However, recently, F
A flash write function of writing all the memory cell transistors 1 at a time using the / N current is realized, thereby shortening the time required for the erase program.

[0007]

However, in the above erasing program, after writing to the memory cell transistor 1, it is necessary to confirm whether or not this writing has been normally performed. Conventionally, this check is performed by executing a read operation for each memory cell transistor 1. Therefore, even if the time required for writing is shortened by the flash write function, this check still takes a long time. This has been a major obstacle to reducing the erasing time of the flash memory.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a flash memory with a short erasing time by collectively checking erasing programs.

[0009]

According to a first aspect of the present invention, a control gate and a drain of a memory cell transistor having a floating gate are provided.
In a flash memory connected to a word line and a bit line arranged in a matrix and having a source connected to a common source line, a bit line potential comparison circuit for comparing the potential of the bit line with a predetermined voltage is provided. An erase program confirming means for applying a voltage higher than a threshold voltage at the time of writing to a word line and applying an appropriate voltage to a source line is provided.

Further, according to the invention of claim 2, in addition to the configuration of claim 1, when any one of the bit line potential comparison circuits determines that the bit line potential is higher than a predetermined voltage, this is detected. It is characterized in that a judgment circuit is provided.

[0011]

When the erase program confirming means applies a voltage equal to or higher than the threshold voltage at the time of writing to the word line and applies an appropriate voltage to the source line, the lowest bit connected to the bit line is applied to the bit line. A potential corresponding to a difference between the threshold voltage of the memory cell transistor having the threshold voltage and the potential of the word line appears. Then, the bit line potential comparison circuit compares the potential of the bit line at this time with a predetermined voltage, and when it is determined that the potential of the bit line is higher than the predetermined voltage, the memory which has not been normally written to the bit line. Indicates that a cell transistor is present.

Therefore, the erase program confirmation means is operated after the execution of the erase program, and the potential of each bit line at this time is compared with a predetermined voltage by the bit line potential comparison circuit, so that the memory cell transistors can be individually read. Even if there is no memory cell transistor, it is possible to collectively check whether there is a memory cell transistor that has not been written normally.

Further, the bit line potential comparison circuit detects the presence of a memory cell transistor that has not been normally written for each bit line. If the determination circuit can detect that there is a bit line potential comparison circuit determined to be higher than the predetermined voltage, the memory cell transistors on a plurality of bit lines can be further confirmed.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments.
1 to 3 show one embodiment of the present invention. FIG. 1 shows an embodiment of the present invention and is a block diagram showing a configuration of a flash memory. Components having the same functions as those of the conventional example shown in FIG.

In this embodiment, a description will be given of a flash memory in which a differential amplifier is provided for each bit line so that an erase program can be checked at a time.

Each of the bit lines B1 to Bn and the source line S are connected via each transfer gate of the first transfer gate array 5 controlled by a signal φP.
Therefore, when the signal φP becomes active, each transfer gate of the first transfer gate array 5 is turned on.
, And the potentials are made equal by connecting between the bit lines B1 to Bn and the source line S.

Each of the bit lines B1 to Bn is connected to one input of each differential amplifier of the differential amplifier array 7 via each transfer gate of the second transfer gate array 6 controlled by the signal φc. I have. The other input of each differential amplifier of the differential amplifier array 7 is connected to the reference voltage generating circuit 9 via each transfer gate of the third transfer gate array 8 controlled by the same signal φc.
Output is connected. This reference voltage generation circuit 9
This circuit outputs a predetermined reference voltage Vref. Each differential amplifier of the differential amplifier array 7 is a DRAM [Dynamic Rando
m Access Memory] is an amplifier circuit generally used as a sense amplifier, and its operation is controlled by a signal φs. Therefore, when the signal φc and the signal φs become active,
The differential amplifier compares the input potential of each of the bit lines B1 to Bn with the reference voltage Vref, and outputs a signal that goes high when the potential of each of the bit lines B1 to Bn is higher.

The output of each differential amplifier of the differential amplifier array 7 is sent to a decision circuit 10 controlled by a signal φE. This determination circuit 10 receives the signal φ
This circuit outputs an H level (active) error signal ERR when at least one of the outputs of the differential amplifier becomes H level when E is active.

An erase program operation in the flash memory having the above configuration will be described.

Erasing and writing are performed by writing for each memory cell transistor 1 or by writing all memory cell transistors 1 at once using a flash write function.

In order to confirm the erase program, first, the bit line selection circuit 3 is set to a non-selected state, and the signal φ
s and φE are inactive and 8V is applied to all word lines W1 to Wm.
And 0 V is applied to the source line S, and the signal φ
Activate P and φc. Then, the bit lines B1 to Bn
Are connected to the source line S via the first transfer gate array 5.
, The electric charge of each memory cell transistor 1 is discharged, and the potential of each bit line B1 to Bn becomes 0V. The bit lines B1 to Bn are connected to the respective differential amplifiers of the differential amplifier array 7 via the second transfer gate array 6.
Is input, and the reference voltage V of the reference voltage generation circuit 9 is input via the third transfer gate array 8.
ref is input.

In this state, the signal φP is made inactive and the bit lines B1 to Bn are disconnected from the source line S, and then the potential of the source line S is raised to 5V. Then, the potentials of the bit lines B1 to Bn increase via the respective memory cell transistors 1. At this time, the potentials of the bit lines B1 to Bn are changed by the memory cell transistors connected to the respective bit lines B1 to Bn. 1 depends on the memory cell transistor 1 having the lowest threshold voltage. That is, for example, the memory cell transistor 1 connected to a certain bit line B
Is 5 V, 6 V, and 7 V, 5
Since the threshold voltage of V depends on the memory cell transistor 1, the bit line B subtracts the threshold voltage Vth (5V) of the memory cell transistor 1 from the potential VW (8V) of the word lines W1 to Wm. 3V potential.

When the signal φc is deactivated to cut off the second transfer gate array 6 and the third transfer gate array 8, and the signal φs is activated to operate each differential amplifier of the differential amplifier array 7. When the potential of the bit lines B1 to Bn is higher than the reference voltage Vref, the output goes high. That is, for example, if the reference voltage Vref of the reference voltage generation circuit 9 is set to 3 V,
When the potential of the bit lines B1 to Bn exceeds 3 V, an H level is output, and the threshold voltage Vth of any one of the memory cell transistors 1 connected to the bit lines B1 to Bn becomes 5
V is less than V. Also, the judgment circuit 1
0 outputs an active error signal ERR when the output of any of the differential amplifiers goes high due to the activation of the signal φE.

Therefore, when the error signal ERR output from the determination circuit 10 becomes active, the memory cell transistor 1 whose threshold voltage Vth is not sufficiently high exists, which indicates that the erase program is not complete. Then, in this case, the erase program is executed again.

As a result, according to the flash memory of this embodiment, the erasure program can be checked for all the memory cell transistors 1 to be erased at once, so that the erasing time can be greatly reduced. become able to.

FIG. 2 shows another embodiment of the present invention and is a block diagram showing a configuration of a flash memory. It should be noted that components having the same functions as those of the first embodiment shown in FIG.

In the first embodiment shown in FIG. 1, the differential amplifier of the differential amplifier array 7 is provided for each bit line B. In the present embodiment, one differential amplifier is provided for two bit lines B. The number of differential amplifiers is provided. The signal φc is divided into a signal φc1 and a signal φc2, and two bit lines B are selected depending on which is activated.

In an actual flash memory, bit line B
Since the arrangement pitch of 1 to Bn is short, 1 as in the first embodiment.
It is difficult to arrange one differential amplifier for each bit line B in terms of layout. However, in the present embodiment, it is sufficient to arrange one differential amplifier for every two bit lines B, so that the layout of the flash memory of the present embodiment does not cause any difficulty.

In this embodiment, one for every two bit lines B
Are arranged, for example, four bit lines B
It is also possible to arrange one differential amplifier for each.
However, in this embodiment as well, it is necessary to confirm the erase program by dividing the two bit lines B into two, and if the number of bit lines B further increases, the number of confirmations will increase. However, even if the number of confirmations increases in this manner, the confirmation of the erase program of the memory cell transistors 1 connected to the plurality of bit lines B cannot be performed collectively. Compared to the case where the access is performed individually and the confirmation is performed, the time can be greatly reduced to some extent.

FIG. 3 shows still another embodiment of the present invention, and is a block diagram showing a configuration of a flash memory capable of performing confirmation after erasing. It should be noted that components having the same functions as those of the first embodiment shown in FIG.

In each of the differential amplifiers in the differential amplifier array 7 of the first embodiment shown in FIG. 1, the potentials of the bit lines B1 to Bn are higher than the reference voltage Vref of the reference voltage generating circuit 9. In such a case, an H level is output in the case of the above. However, each differential amplifier of this circuit example is configured to output an H level when the potential of the bit lines B1 to Bn becomes lower than the reference voltage Vref. Therefore, if the same operation as the confirmation of the erase program is performed after the erase operation is completed, if the memory cell transistor 1 in which the threshold voltage Vth is not sufficiently lowered and the erase is not completely performed exists, The differential amplifier outputs the H level, and the determination circuit 10 can detect this error in the erasing operation.

In this circuit example, the position of the output line of the differential amplifier is different from that of the first embodiment, and the other structures are similar to those of the first embodiment. By combining the respective circuits with the example, it is possible to configure a flash memory capable of easily confirming both the erase program and the erase state.

[0033]

As is apparent from the above description, according to the present invention, the erasure program can be checked all at once, so that the erasing time of the flash memory can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a flash memory according to one embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a flash memory according to another embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a flash memory according to still another embodiment of the present invention, which can perform confirmation after erasure;

FIG. 4 is a block diagram showing a configuration of a conventional flash memory.

[Explanation of symbols]

 Reference Signs List 1 memory cell transistor 7 differential amplifier array B1 to Bn bit line W1 to Wm word line S source line Vref reference voltage

Claims (2)

(57) [Claims] 1. A flash memory in which a control gate and a drain of a memory cell transistor having a floating gate are connected to a word line and a bit line arranged in a matrix and a source is connected to a common source line. Bit line potential comparison circuit for comparing the potential of the bit line with a predetermined voltage, and erase program confirmation means for applying a voltage higher than the threshold voltage at the time of writing to the word line and applying an appropriate voltage to the source line Flash memory characterized by the above. 2. A circuit according to claim 1, further comprising a determination circuit for detecting when any one of the bit line potential comparison circuits determines that the potential of the bit line is higher than a predetermined voltage. The flash memory as described.