JP2009230793A - Nonvolatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem in conventional electronic devices that the user has to protect data with careful attention by himself or herself. <P>SOLUTION: In this nonvolatile semiconductor storage device, the data stored in an undecided data storing memory area which is constituted of EEPROM are replaced with a determined data storing memory area which is constituted of memory elements capable of writing the data only once, after the lapse of predetermined period. The determined data can be protected without making the user be conscious of the replacement by forming such a configuration. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device.

A nonvolatile semiconductor memory device stores data by accumulating electric charges in a charge accumulation film. EEPROM (Electronically Erasable and Programmable Read Only Memory: electrically rewritable non-volatile memory) is roughly divided into two structures with different types of charge storage films.
One is an FG (Floating Gate) in which a conductor called a floating gate serving as a charge storage film is surrounded by an oxide film and electrically insulated on a gate insulating film, and charges are stored in the floating gate. Floating gate) type.

  The other is a MNOS (Metal-Nitride-Oxide) that has a charge storage film in which a plurality of insulating films are stacked and stores information by controlling the amount of charge stored in a charge trap in the charge storage film. -Silicon) type and MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type.

The threshold voltage in the state where electrons are stored in the charge storage film, that is, in the state where write data is stored, is Vtw, and the threshold voltage in the state where holes are stored in the charge storage film, that is, where erase data is stored The voltage is Vte, and the threshold voltage in a state where neither electrons nor holes are accumulated in the charge storage film, that is, the thermal equilibrium state threshold voltage is called V0.
Here, when the value of the voltage Vcg applied to the gate electrode of the memory element when reading the data stored in the memory element is set so that the relationship of Vte <Vcg <Vtw is established, the drain current of the memory element is Since it does not flow in a state where data is stored but flows in a state where erase data is stored, it is possible to discriminate between write data and erase data.

However, the values of Vtw and Vte are not always constant. The memory element gradually approaches a thermal equilibrium state that is a stable state of energy with the passage of time. That is, since the charge accumulated in the charge storage film is released over time, the values of Vtw and Vte approach V0, and finally Vtw = Vte = V0.
If the relationship of Vte <Vcg <Vtw does not hold in the process in which the values of Vtw and Vte approach V0, data cannot be read correctly.

In addition, by repeatedly writing and erasing data, the oxide film that insulates the semiconductor substrate from the charge storage film is damaged by the application of the write voltage and the erase voltage and by the repeated passage of charge. Accumulate and cause defects.
Even when a defect occurs, the values of Vtw and Vte approach V0, so the relationship of Vte <Vcg <Vtw does not hold and data cannot be read correctly.

Due to these circumstances, the EEPROM has a limit of time for storing stored data and a limit of the number of times of writing and erasing. This is called memory life. In general, a long memory life means that the stored data can be held for a long time or the number of times of writing and erasing is large.
Several proposals are being seen as a method of coping with these two limitations when approaching the use of EEPROM (see, for example, Patent Document 1).

  Next, it demonstrates using drawing. FIG. 7 is an explanatory diagram of the configuration of the main part of the nonvolatile semiconductor memory device described in the prior art disclosed in Patent Document 1, and is a diagram rewritten without departing from the gist thereof for easy explanation.

  In FIG. 7, 500 is a flash memory card, 50 is a card controller, 51 is a flash memory, 52 is an X decoder, 53 is a defect detection circuit, BAD is a defect detection signal, and 60 is a flash memory cell group. 61 and 62 are sectors of the flash memory cell group. 63 is a data area, and 64 is a management area. 65a and 65b are monitor bits.

The flash memory cell group 60 has a plurality of sectors each including a plurality of nonvolatile memory cells that are selected simultaneously. One sector corresponds to one word. In FIG. 7, representative sectors 61 and 62 are shown.
The flash memory cell group 60 includes a data area 63 used for storing data and a management area 64 for managing the data area 63. The monitor bits 65a and 65b are formed in the management area 64. The monitor bits 65a and 65b are nonvolatile memory cells that have a smaller threshold margin in data retention characteristics than the nonvolatile memory cells in the data area 63.

The conventional erasing and writing operations described in Patent Document 1 will be described.
Data erasing and writing are performed in units of sectors, that is, in units of words, regardless of the data area 63 and the management area 64. The monitor bits 65a and 65b store mutually contradictory data. That is, when erasing data (logical value “0”) is stored in the monitor bit 65a, write data (logical value “1”) is stored in the monitor bit 65b.

Next, a defect detection and a coping operation when a defect is detected will be described.
By repeating the lapse of time after data is stored or repeatedly erasing and writing data, the threshold margin of the nonvolatile memory cell gradually decreases, and eventually the nonvolatile memory cell in the data area 63 The monitor bits 65a and 65b having a smaller threshold margin in the data retention characteristic reach the lifetime earlier.

  The defect detection circuit 53 is not particularly limited, but can be configured by an exclusive OR circuit for comparing the logical values of the monitor bits 65a and 65b. If the monitor bits 65a and 65b are logical values “0” and “1”, respectively, the lifetime has not yet been reached. However, when the monitor bits 65a and 65b become logic values “0” and “0” or “1” and “1”, respectively, the output logic of the exclusive OR circuit of the defect detection circuit 53 is inverted, and the monitor bits It is detected that the life of the sector 61 to which 65a and 65b belong is approaching.

The defect detection circuit 53 that has detected that the life of the sector 61 is approaching, sends a defect detection signal BAD to the card controller 50.
Upon receiving the defect detection signal BAD, the card controller 50 replaces the data stored in the sector 61 with the unused sector 62.

Thereafter, when a signal for instructing the card controller 50 to read the data stored in the sector 61 is received from the outside of the flash memory card 500, the card controller 50 replaces the sector 61 with the sector 62 in the X decoder 52. Send a signal to access to.
Then, the data stored in the sector 62 instead of the data stored in the sector 61 is output to the outside of the flash memory card 500.

The prior art disclosed in Patent Document 1 is provided with monitor bits 65a and 65b having a smaller threshold margin in data retention characteristics than the nonvolatile memory cells in the data area 63 used for storing data. It is possible to detect that the life of the sector 61 is approaching, and the reliability of the flash memory card 500 is improved by replacing the data stored in the sector 61 with the unused sector 62 by the card controller 50. It has the feature of doing.

JP 2000-173275 A (pages 5-7, FIG. 7)

By the way, the nonvolatile semiconductor memory device stores two types of data: definite data that does not need to be rewritten and unconfirmed data that needs to be rewritten or erased.
For example, when a non-volatile semiconductor storage device is incorporated in an electronic device, the operation program of the electronic device is deterministic data because there is a problem that it will not operate if it is modified. On the other hand, the unique information of the user who uses the electronic device is unconfirmed data because it causes inconvenience if it cannot be altered.

  On the electronic device side (or non-volatile semiconductor memory device), it is impossible to determine whether the stored data is confirmed data or unconfirmed data. In order to prevent modification such as overwriting or overwriting, data protection was carried out by self-care.

  When the conventional technique shown in Patent Document 1 is mounted on an electronic device, after the data is stored in the data area of the flash memory cell group 60, the monitor bits 65a and 65b detect that the memory life is approaching. Whether the data is confirmed data or unconfirmed data, the card controller 50 replaces the data stored in the sector 61 with another sector 62. As a result, the problem of data loss due to the memory life has been solved, but no measures have been taken for data protection according to the type of data.

  In other words, even if the data is originally determined that does not need to be rewritten, the prior art disclosed in Patent Document 1 cannot recognize the data as determined data, and thus performs sector replacement in the same manner as unconfirmed data. Only. From the user's point of view, since it is not conscious of sector replacement in the flash memory cell group 60, it appears that data is simply stored. Therefore, there is a risk of modification such as accidentally overwriting stored data.

  The present invention has been made to solve such a problem, and an object of the present invention is to perform data protection without being conscious of a user who uses a nonvolatile semiconductor memory device.

  In order to solve the above problems, the present invention adopts the following configuration.

A memory area including a deterministic data storage memory area and an indeterminate data storage memory area, a write circuit, a read circuit, and a timer; the timer includes a timer memory element and a history memory; When storing data in the memory area, the data is simultaneously stored in the indeterminate data storage memory area and the timer memory element, and history information is stored in the history memory, and the timer stores the data stored in the timer memory element. When the change is detected, the history information is referred to, the data stored in the undetermined data storage memory area is specified, the data replacement signal is output, and when the reading circuit receives the data replacement signal, the undetermined data storage memory area Read the data stored in and send the data to the writing circuit,
The writing circuit writes data in the definite data storage memory area.

  The memory element constituting the definite data storage memory area has a longer memory life than the memory element constituting the undetermined data storage memory area.

  The definite data storage memory area is a memory element in which data can be written only once.

  The timer memory element is characterized in that the memory life is shorter than that of the memory element constituting the undetermined data storage memory area.

  The timer memory element and the memory element constituting the undetermined data storage memory area have the same structure.

  The timer memory element and the memory element constituting the undetermined data storage memory area have a stacked film formed by stacking a plurality of insulating films.

When writing data to the timer memory element, by lowering the write voltage or shortening the write time than when writing data to the indeterminate data storage memory area,
The threshold margin of the timer memory element is made smaller than the threshold margin of the memory elements constituting the undetermined data storage memory area.

  When writing data to the timer memory element, writing damage is accumulated by performing data writing at least twice, and the memory life of the timer memory element is shortened.

The nonvolatile semiconductor memory device of the present invention is a fixed semiconductor memory device that can store data stored in an undetermined data storage memory area composed of an EEPROM with a memory element that can write data only once after a predetermined time has elapsed. Replace with the data storage memory area.
In this way, since the confirmed data that originally does not need to be rewritten is replaced with the confirmed data storage memory area, the confirmed data can be protected without the user being aware of it.

The nonvolatile semiconductor memory device of the present invention stores data in an indeterminate data storage memory area. Thereafter, it is determined whether the data is confirmed data or unconfirmed data, and only the confirmed data is replaced with a confirmed data storage memory area.
Whether the written data is confirmed data or undefined data is determined by a timer. This determination is made with the passage of time from the time of data writing, and it is determined that data that has not been rewritten (overwritten) even after a predetermined time has passed is determined data that does not need to be rewritten. .

  The predetermined time elapses is to detect the memory life of the timer memory element of the timer, and when the data is stored, the data is also stored in the timer memory element. The time until the end of the service life is used. In general, a memory has a long lifetime, for example, several months to over 10 years. Data that has not been rewritten (overwritten) over that time is determined as data that does not need to be rewritten.

It should be noted that the lifetime of the timer memory element can be freely selected from the above-mentioned period of several months to over 10 years. That is, the lifetime as a memory element is selected in advance. Whether the written data is confirmed data or unconfirmed data can be determined by the determination by the timer, that is, the lifetime of the timer memory element, so you can freely set the time until this lifetime is reached. For example, you can decide how long it takes to protect your data.

  The definite data storage memory area is configured by a memory element that can write data only once. The element is described as using an OTPROM (One Time PROM). A known configuration can be used for the OTPROM. For example, a dielectric breakdown type OTPROM which has a MIS (Metal Insulator Semiconductor) type transistor element structure and performs writing only once by dielectric breakdown of the gate insulating film can be used.

  As described above, the nonvolatile semiconductor memory device of the present invention can determine whether stored data is determined data that does not need to be rewritten or unconfirmed data that needs to be rewritten. By replacing only the confirmed data with the confirmed data storage memory area, the confirmed data can be protected without the user being aware of it. In addition, after replacement of the confirmed data, the area in which the confirmed data in the unconfirmed data storage memory area is stored can be used as an area for storing new unconfirmed data, which improves the area efficiency of the memory area. .

  In the nonvolatile semiconductor memory device of the present invention, the timer memory element and the memory element constituting the undetermined data storage memory area will be described as elements having the same structure.

  Next, the nonvolatile semiconductor memory device of the present invention will be described in detail with reference to the drawings. In the drawings, the same numbers are assigned to the same components.

[Overall Description of Nonvolatile Semiconductor Memory Device: FIG. 1]
FIG. 1 is a block diagram for explaining a nonvolatile semiconductor memory device according to the present invention.
In FIG. 1, 1 is a confirmed data storage memory area, 2 is an unconfirmed data storage memory area, 3 is a write circuit, 4 is a timer, 5 is a read circuit, 6 is a memory for timer, 7 and 8 are data discrimination circuits, 10 , 20 are used areas, 11 and 21 are blank areas, 40 is a history memory, and 100 is a nonvolatile semiconductor memory device having these.

In the fixed data storage memory area 1, an area in which data is stored is referred to as a use area 10, and an area in which no data is stored is referred to as a blank area 11.
Similarly, in the undetermined data storage memory area 2, an area storing data is referred to as a use area 20, and an area not storing data is referred to as a blank area 21.

  It is assumed that the memory element that constitutes the confirmed data storage memory area 1 has a longer memory life than the memory element that constitutes the indeterminate data storage memory area 2. For example, the unconfirmed data storage memory area 2 is composed of an EEPROM, and the confirmed data storage memory area 1 is composed of an OTPROM.

The read circuit 5 has a data discrimination circuit 7. The timer 4 includes a timer memory 6, a data determination circuit 8, and a history memory 40.
The memory elements constituting the timer memory 6 are assumed to have a shorter memory life than the memory elements constituting the indeterminate data storage memory area 2. The lifetime of the memory elements constituting the timer memory 6 is set in advance as described above. For example, when the nonvolatile semiconductor memory device according to the present invention is mounted on an electronic device having a relatively short product life, it is not necessary to extend the life of the memory element. The lifetime of the history memory 40 may be the same as that of the memory elements that constitute the undetermined data storage memory area 2.

[Description of data write operation: FIG. 1]
Next, the data write operation of the nonvolatile semiconductor memory device of the present invention will be described with reference to FIG.
As already described, the data includes confirmed data such as an operation program that does not need to be rewritten thereafter, or unconfirmed data such as user data. For example, even an operation program becomes unconfirmed data if there is a possibility of rewriting due to subsequent specification changes or bugs.
When data is written to the nonvolatile semiconductor memory device 100, it is not known whether the data is confirmed data or unconfirmed data. Therefore, all the data is written into the use area 20 of the undefined data storage memory area 2 by the writing circuit 3.
Precisely, the undetermined data storage memory area 2 before the data is written is all the blank area 21, and by writing data in the blank area 21, the portion becomes the use area 20.

When data is written to the use area 20, data is also written to the timer memory 6 at the same time.
Although not shown, the timer memory 6 is divided into a plurality of blocks, and one block is used for writing data into the use area 20 once.
When new data is written to the use area 20, data is written to an unused block of the timer memory 6, and when data written to the use area 20 is overwritten, the timer memory 6 corresponds. The block also overwrites the data.
Information about which address in the use area 20 corresponds to the data written in a specific block of the timer memory 6 is stored in the history memory 40 of the timer 4 as history information.

The history information stored in the history memory 40 is information for selecting data to be replaced from data stored in the undetermined data storage memory area 2.
For example, if the same data as the data stored in the undetermined data storage memory area 2 is written in the first block of the timer memory 6, this "data written in the first block is the undetermined data storage memory area. The association information is “the data stored in 2”.

  By the way, when writing data to the use area 20, it has been described that “the data is simultaneously written” to the timer memory 6. A slight time difference may occur due to generation, transmission thereof, and the like. Strictly speaking, it would be more correct to write “write almost at the same time”, but to write at the same time to simplify the explanation.

[Description of data read operation: FIGS. 1 and 2]
Next, the data read operation of the nonvolatile semiconductor memory device of the present invention will be described with reference to FIG.
When reading data stored in the nonvolatile semiconductor memory device 100, a read signal S is sent from the read circuit 5 to the confirmed data storage memory area 1 and the undefined data storage memory area 2.

  When the read signal S reaches the use area 10 of the definite data storage memory area 1, the storage data a corresponding to the stored data is sent from the use area 10 to the read circuit 5 and is discriminated by the data discrimination circuit 7 of the read circuit 5. The result is output from the read circuit 5 to the outside of the nonvolatile semiconductor memory device 100.

  When the read signal S reaches the use area 20 of the undefined data storage memory area 2, the storage data b corresponding to the stored data is sent from the use area 20 to the read circuit 5, and the data discrimination circuit 7 included in the read circuit 5 The determined result is output from the read circuit 5 to the outside of the nonvolatile semiconductor memory device 100.

Here, the data discrimination of the read circuit 5 will be described in more detail.
FIG. 2 is a block diagram for explaining the configuration of the data discriminating circuit 7 included in the reading circuit 5 of the present invention. Although not shown, the data discrimination circuit 8 has the same configuration.
In FIG. 2, 70 is a read load element, 71 is a read comparator, PG is a read voltage input terminal, IN is a data input terminal, and OUT is a data output terminal.

The stored data of the bits designated in the determined data storage memory area 1 and the undefined data storage memory area 2 in FIG. 1 are input from the data input terminal IN in FIG.
The load value of the read load element 70 is determined according to the value of the read voltage Vpg input to the read voltage input terminal PG.

Stored data input from the data input terminal IN is determined using the determined load value, and the result is output from the data output terminal OUT to the outside of the data determination circuit 7 via the read comparator 71.
Here, the boundary for discriminating stored data is the sense level.

[Description of data replacement operation: FIG. 1]
Next, the data replacement operation of the nonvolatile semiconductor memory device of the present invention will be described with reference to FIG.

The memory element that constitutes the timer memory 6 has a shorter memory life than the memory element that constitutes the indeterminate data storage memory area 2.
When the timer 4 senses that a specific block of the timer memory 6 has reached the end of its life using the data discriminating circuit 8, it collates with the history information stored in the history memory 40 of the timer 4, and the unconfirmed data storage memory area It is determined to which address in the second use area 20 the data written is to be replaced, and a data replacement signal SU is sent to the read circuit 5 to start the data replacement operation of the present invention.

The read circuit 5 that has received the data replacement signal SU sends the read signal S to an address that is the target of data replacement in the use area 20.
The use area 20 that has received the read signal S sends the storage data b stored at the target address to the read circuit 5.

  The read circuit 5 that has received the storage data b sends the information of the storage data b to the write circuit 3, and the write circuit 3 writes the information of the storage data b to the blank area 11 of the defined data storage memory area 1, The data replacement operation ends. This state is indicated by a dotted arrow from the write circuit 3 to the defined data storage memory area 1 in FIG.

When the timer memory 6 reaches the end of its life, the unconfirmed data storage memory area 2 has not yet reached its end of life, and the stored data is accurate with no mixed defects.
Data can be protected by replacing accurate data with the confirmed data storage memory area 1 having a longer memory life than the unconfirmed data storage memory area 2.

[Explanation of timer memory: FIG. 2, FIG. 3, FIG. 4, FIG. 5, FIG. 6]
Here, a method for making the memory life of the timer memory 6 shorter than the memory life of the unconfirmed data storage memory area 2 will be described. There are first to fourth means.

[Explanation of first means: FIG. 3]
FIG. 3 is a cross-sectional view for explaining the structure of the memory elements constituting the undetermined data storage memory area 2 and the timer memory 6 of the present invention. As described above, in the embodiment of the present invention, these two memory elements have the same structure.
In FIG. 3, 30 is a gate electrode, 31 is a top insulating film, 32 is a charge storage film, 33 is a bottom insulating film, 34 is a semiconductor substrate, 35 is a source, 36 is a drain, and 300 is a memory element having them.

The memory life of the memory element 300 varies depending on the film thickness of the bottom insulating film 33.
Increasing the thickness of the bottom insulating film 33 increases the memory life of the memory element 300, and decreasing the thickness of the bottom insulating film 33 decreases the memory life of the memory element 300.
Therefore, the memory life of the memory element constituting the timer memory 6 is shortened by making the bottom insulating film thinner than the memory element constituting the undetermined data storage memory area 2.

[Description of Second Means: FIGS. 4 and 5]
FIG. 4 is an explanatory diagram showing the relationship between the change in the threshold voltage value of the memory element 300 in FIG. 3 with respect to the write time and the sense level, and shows the case where the write voltage is different. The horizontal axis represents the data write voltage application time on the logarithmic axis, and the vertical axis represents the threshold voltage value.
Vppw1, Vppw2, and Vppw3 are values of the write voltage, and the magnitudes of the values are Vppw1 <Vppw2 <Vppw3.
The difference between the threshold voltage value and the sense level value is called a threshold margin. A state in which the threshold voltage value is larger than the sense level value is referred to as a data write state.

The threshold margin varies depending on the write voltage or the write time.
In the data writing state, the threshold margin is increased when the writing time is increased or the writing voltage is increased, and the threshold margin is decreased when the writing time is shortened or the writing voltage is decreased.

  Although not shown, the threshold margin gradually decreases as time elapses after data is written or data is repeatedly overwritten. When the threshold margin becomes 0, the written data disappears, that is, the memory life is reached.

  Therefore, when the data write state is stored in the memory element constituting the timer memory 6, the write time is shorter than when the data write state is stored in the memory element constituting the undetermined data storage memory area 2, or The memory life is shortened by reducing the write voltage.

FIG. 5 is an explanatory diagram showing the relationship between the change of the threshold voltage value of the memory element 300 in FIG. 3 with respect to the erase time and the sense level, and shows the case where the erase voltage is different. The horizontal axis represents the data erase voltage application time on a logarithmic axis, and the vertical axis represents the threshold voltage value.
Vppe1, Vppe2, and Vppe3 are erase voltage values, and the magnitudes of the values are Vppe1 <Vppe2 <Vppe3.
A state in which the threshold voltage value is smaller than the sense level value is referred to as a data erase state.

In the data erase state, similarly to the data write state, the threshold margin varies depending on the erase voltage or the erase time.
Therefore, when the data erase state is stored in the memory element constituting the timer memory 6, the erase time is shorter than when the data erase state is stored in the memory element constituting the unconfirmed data storage memory area 2, or The memory life is shortened by reducing the erase voltage.

[Explanation of third means: FIGS. 2 and 6]
FIG. 6 is an explanatory diagram showing the relationship between the value of the sense level of the data discrimination circuit 7 and the data discrimination circuit 8 (not shown) in FIG. 2 and the value of the read voltage Vpg. The horizontal axis represents the value of the read voltage Vpg, and the vertical axis represents the value of the sense level.
When the read voltage Vpg increases, the sense level decreases, and when the read voltage Vpg decreases, the sense level increases.

In the data write state, the threshold margin decreases as the sense level increases. In the data erase state, the threshold margin decreases as the sense level decreases.
Therefore, the read voltage Vpg of the data discriminating circuit 8 is prepared in two types, that is, smaller than and larger than the read voltage Vpg of the data discriminating circuit 7, and the data is discriminated by the two types of read voltages, thereby the timer memory. 6 can be made shorter than the memory life of the undetermined data storage memory area 2.

[Description of Fourth Meaning: FIG. 3]
In the memory element 300 shown in FIG. 3, when data writing and erasing are repeated, damage to the bottom insulating film 33 due to application of a writing voltage and an erasing voltage and damage due to repeated passage of charges accumulate. Will occur. When a defect occurs, the threshold margin is small and sometimes becomes 0.
Therefore, when data is stored in the timer memory 6, by writing the data to be stored after intentionally rewriting a plurality of times, the probability of occurrence of defects can be increased and the memory life can be shortened.

  As described above, the first to fourth means are representative means for making the memory life of the timer memory 6 shorter than the memory life of the unconfirmed data storage memory area 2. Of course, these means may be combined.

In the nonvolatile semiconductor memory device of the present invention, since the start time of the data replacement operation is defined by the memory life of the timer memory 6 included in the timer 4, before the data in the undetermined data storage memory area 2 disappears. Data replacement is possible.
This is because the memory life is not determined only by the elapsed time since the data was stored, but it is strongly influenced by the number of data rewrites and the environment in which the memory element is left, particularly the ambient temperature. Since not only the memory elements of the indeterminate data storage memory area 2 but also the memory elements of the timer memory 6 are received, in a situation where the memory life is shortened, the data is stored at a stage where the elapsed time after storing the data is shorter. This is because the replacement operation is started.

[Explanation of memory elements in the definite data storage memory area]
Here, the memory elements constituting the determined data storage memory area 1 will be described.
For example, a known dielectric breakdown type PROM, a fuse type PROM, or a diode breakdown type PROM can be used as the memory element constituting the definite data storage memory region 1.

The dielectric breakdown type PROM uses a MIS type transistor as a memory element.
Whether a current flows between the gate and the source of the MIS transistor or between the gate and the drain corresponds to logical values “0” and “1”.
Data is written by applying a breakdown voltage larger than the withstand voltage of the gate insulating film between the gate and the source or between the gate and the drain, thereby causing the gate insulating film to break down into a short circuit state.

The fuse type PROM uses a fuse made of polysilicon doped with impurities at a high concentration as a memory element.
Whether or not current flows through the fuse corresponds to logical values “0” and “1”.
Data is written by passing an excessive current through the fuse and blowing the fuse.

The diode destruction type PROM uses a pn junction diode as a memory element.
Whether or not the reverse current of the diode flows corresponds to logical values “0” and “1”.
Data is written by applying a breakdown voltage larger than the reverse breakdown voltage to both ends of the diode to destroy the diode and short-circuit it.

  In addition to the dielectric breakdown type PROM, the fuse type PROM, and the diode breakdown type PROM, the memory element 300 described with reference to FIG. 3 can also be used as the OTPROM.

When the memory element 300 is used as an OTPROM constituting the determined data storage memory area 1, the thickness of the bottom insulating film 33 is set to the thickness of the bottom insulating film 33 of the memory element 300 constituting the undefined data storage memory area 2. Is sufficiently thick (for example, 1.5 times thicker).
By doing so, the memory life is remarkably long (for example, 1000 times longer), and in actual use, it can function as an OTPROM in which data is not lost.

  The nonvolatile semiconductor memory device of the present invention is suitable for an electronic device that needs to store confirmed data such as an operation program and unconfirmed data such as user data.

1 is a block diagram for explaining a nonvolatile semiconductor memory device according to the present invention. FIG. 4 is a block diagram for explaining a data discrimination circuit of the nonvolatile semiconductor memory device according to the present invention. FIG. 1 is a cross-sectional view for explaining a structure of a memory element of a nonvolatile semiconductor memory device according to the present invention. It is a figure explaining the relationship between the time which applies a write voltage to a memory element, and a threshold voltage. It is a figure explaining the relationship between the time which applies erase voltage to a memory element, and threshold voltage. It is a figure explaining the relationship between the read voltage applied to a read load element, and the sense level of a data discrimination circuit. It is a block diagram explaining the prior art shown in patent document 1. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Deterministic data storage memory area 2 Undetermined data storage memory area 3 Write circuit 4 Timer 5 Read circuit 6 Timer memory 7, 8 Data discrimination circuit 10, 20 Use area 11, 21 Blank area 40 History memory 100 Non-volatile semiconductor memory device a, b Stored data S Read signal SU Data replacement signal

Claims (8)

A memory area including a confirmed data storage memory area and an indeterminate data storage memory area, a write circuit, a read circuit, and a timer;
The timer includes a timer memory element and a history memory,
The write circuit, when storing data in the memory area, simultaneously stores the data in the unconfirmed data storage memory area and the timer memory element, and stores history information in the history memory,
When the timer detects a change in the data stored in the timer memory element, the timer refers to the history information, specifies the data stored in the indeterminate data storage memory area, and outputs a data replacement signal.
When the read circuit receives the data replacement signal, the read circuit reads the data stored in the undetermined data storage memory area and transmits the data to the write circuit.
The non-volatile semiconductor memory device, wherein the write circuit writes the data into the defined data storage memory area.   2. The nonvolatile semiconductor memory device according to claim 1, wherein a memory element constituting the definite data storage memory area has a longer memory life than a memory element constituting the undetermined data storage memory area.   3. The nonvolatile semiconductor memory device according to claim 1, wherein the determined data storage memory area is a memory element in which data can be written only once.   4. The nonvolatile semiconductor memory device according to claim 1, wherein the timer memory element has a shorter memory life than a memory element that constitutes the indeterminate data storage memory area. 5.   5. The nonvolatile semiconductor memory device according to claim 1, wherein the memory element for timer and the memory element that constitutes the indeterminate data storage memory area have the same structure. 6.   6. The timer memory element and the memory element constituting the undetermined data storage memory area have a laminated film formed by laminating a plurality of insulating films. The nonvolatile semiconductor memory device according to one. When writing data to the memory element for timer, by lowering the write voltage or shortening the write time than when writing data to the indeterminate data storage memory area,
7. The threshold margin of the timer memory element is made smaller than a threshold margin of a memory element constituting the undefined data storage memory area. Nonvolatile semiconductor memory device. When writing data to the timer memory element, write damage is accumulated by writing data at least twice,
8. The nonvolatile semiconductor memory device according to claim 1, wherein a memory life of the timer memory element is shortened.

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