JP2002093179A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system in which an apparent access time is shortened. SOLUTION: This non-volatile semiconductor memory provided with plural non-volatile memory cells and plural data registers storing temporarily data of the memory cell, transfers data of selected one page out of the memory cells to the corresponding data register, outputs data of one page transferred to the corresponding data register to the outside, and outputs a busy signal indicating that access cannot be performed to the outside while data of one page is transferred to the corresponding data register. The device has a latch circuit connected to the data register and a buffer circuit connected to this latch circuit, and the busy signal is switched to a ready state after data of the head column address of read-out out of the data of one page is transferred to the latch circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory, and more particularly to a non-volatile semiconductor memory which can be read and written in page units.

[0002]

2. Description of the Related Art Recent EEPROM (Electrically Era)
sable & Programmable Read Only Memory), especially NA
The ND type EEPROM is configured so that reading and writing can be performed in a page unit (256 bits to several K bits) in consideration of a small amount of current flowing to a memory cell at the time of writing / erasing. As the nonvolatile semiconductor memory of the NAND type, a memory having a storage capacity of 4 Mbits has already been put to practical use (1989-ISS).
CC An Experimental 4Mb EEROM with a NANDStructured
Cell).

FIG. 22A shows a configuration of two NAND bundles each formed by connecting eight memory cells MC each having a floating gate structure between a bit line and a source. The select gates of the memory cells are set to low level, and the select gates of the remaining seven memory cells in the NAND bundle are set to high level. The bit line and N
The gate of the select transistor T1 between the AND bundles (select line SL (1)) and the gate of the select transistor T2 between the GND bundle and the NAND bundle (select line SL (2)) are set to a high level. In the nonvolatile semiconductor memory having the NAND structure, although the threshold value of the written memory cell is positively distributed as shown in FIG. 22B, the writing is performed based on the gate voltage (H level) of the non-selected transistors in the NAND bundle. The amount of electrons injected into the memory cell is controlled so that the later threshold value becomes low. Therefore, if the threshold voltage of the selected memory cell is positive, no current flows between the bit line BL and GND, and the bit line goes high. Conversely, if the threshold voltage of the selected memory cell is negative, a current flows between the bit line and GND, and the bit line goes low. The memory cell data is read by sensing the potential of the bit line.

Next, a write operation will be described. FIG.
As shown in FIG. 3A, a high voltage (V _pp ) of about 20 V is supplied from the row decoder to the selection gate of the selected memory cell, and the selection gates of the other seven memory cells of the same NAND bundle are supplied to the selection gate. An intermediate voltage (VPI) of about 10 V is supplied. 0V is applied to all select gates of other NAND bundles.
Is supplied. At this time, the NA including the selected memory cell
The gate voltage of the selection transistor between the ND bundle and the bit line is set to 12V, and the gate voltage of the selection transistor between the NAND bundle and the source line is set to 0V. In this state, when the bit line is set to 0 V, the N
Drain, source, and drain of all memory cells in the AND bundle
And the potential of the channel becomes 0 V, so that a potential difference of 20 V occurs between the selection gate and the channel of the selected memory cell, and electrons are injected from the substrate into the floating gate. At this time, a potential difference of 10 V is generated between the selection gates and the channels of the other seven memory cells in the same NAND bundle.
Since the oxide film thickness between the floating gate and the channel is set so that injection of electrons hardly occurs at a potential difference of 0 V, "0" data is not written in the other seven memory cells. When the bit line is set to a write-protected drain voltage (VDPI) of about 10 V, the potential difference between the select gate and the channel of the selected memory cell becomes 10 V,
No writing is performed. At this time, writing is not performed because there is no potential difference between the selection gates and the channels of the other seven memory cells in the same NAND bundle. Data is written by supplying 0V to the bit line when writing "0" data to the selected memory cell and supplying VDPI to the bit line when writing "1" data to the selected memory cell. .

Finally, the erasing operation will be described. FIG.
As shown in (1), by setting the substrate at 20 V (V _pp ) and the selection gate at 0 V, the electrons in the floating gate are drawn out to the substrate to perform erasing. At this time, the select line is set at 2 to reduce the gate stress of the select transistor.
It is set to 0 V (V _pp ). Further, the bit line and the source line are set to OPEN so that the PN junction in the memory array does not enter the forward bias state, and has a potential of approximately _Vpp .

As described above, in a NAND-structure semiconductor memory in which writing is performed by a tunnel current, the current flowing through a bit line at the time of writing is small, so that writing can be simultaneously performed to several thousand memory cells.

FIG. 25 shows a 4M N which is currently in practical use.
FIG. 25 is a diagram for explaining the operation mode of the AND structure semiconductor memory. As shown in FIG. 25A, 512 bits × 8 (I / O) = 4096 bit lines are arranged in the column direction, and 128 NAND bundles are arranged in the row direction. × 8 bits = 1024
Book word lines are arranged. When writing to this memory, each data register connected to each bit line stores I
After data is input 512 times from the / O buffer circuit (FIG. 25 (b)), writing to 4096 bits is performed collectively (FIG. 25 (c)). At the time of reading, a random read mode (FIG. 25D) for reading specific column address data after transferring data of a memory cell to a data register and an in-page read mode for reading only data register contents (FIG. 25E) ). When the row address (page address) is switched, a random read state is set, and it takes 10 μsec to read data from the memory cell. However, when the column address (intra-page address) is switched, page read becomes possible, and 70 nsec. High-speed reading is possible. FIG. 26 is a block diagram of a semiconductor memory configured in this manner. Each bit line has a sense amplifier circuit that determines the potential of the bit line and reads data of the memory cell, and a data that is read and written. A data register to be latched is connected. The data register is configured so that data can be selectively output and input by a column decoder output selected corresponding to a column address. A row decoder circuit driven by a row address buffer includes a selected word line,
The different voltages described above are supplied to the other seven word lines of the NAND bundle including the selected memory cell and the word lines of the other NAND bundle in the read, write, and erase modes. The read, write, and erase modes are controlled by command codes input from the I / O buffer circuit. Command data is shown in FIG.
As shown in (1), the chip is fetched into the command register by the clock of the external control signal NWE, and the chip operation is determined by the command decoder output corresponding to the fetched command code. FIG. 28 is a diagram showing timings of random read (page read) and intra-page read in the operation mode of FIG. 27. The access time (t _acc ) when the row address switches is as slow as 10 μsec, but the column address is low. Since the access time (t _pac ) in the case where is switched is as fast as 70 nsec, the average access time in the case of continuous reading of one page is (10 μsec + 70).
(nsec × 511) /512=89.3 nsec, which enables high-speed reading. FIG. 29 shows the input waveform timing when batch writing is performed after serial data input. First, when a command code of [40] is input from the I / O buffer, the chip is controlled by the control circuit to 512 bits.
In the byte serial data input mode, a row address and 512-byte data are input by the clock of the external control signal NWE. When the 512th byte of data is input, data of 4096 bits is automatically written. Thereafter, in order to check whether the data has been written correctly, the user inputs a [CO] command, and performs a recovery operation for discharging the high voltage supplied to the word line and the bit line at the time of writing, and a total operation while incrementing the column address. A verify operation for reading data at a column address is performed. If the read data is different from the data to be written, the user needs to input the command of [40] and write again. In the conventional memory configured as described above, when reading and writing data of an arbitrary length from an arbitrary address,
The external chip that controls the memory identifies the column address and the row address of the memory, and performs data reading after 10 μsec when the page address is switched, and reads data after 70 nsec when the intra-page address is switched. Must be accessed to perform the following. FIG. 30A shows three column addresses (A0 to A).
2) shows a program sequence of the memory control chip when reading continuous data from address 2 to address 1F of the semiconductor memory composed of 7 row addresses (A3 to A8). FIG. 2B shows the concept.
At the time of the first reading, since the memory cell data needs to be transferred to the data register, the access time is 10 μm.
sec. Next, since only the column address is switched from address 2 to address 7, the read operation is performed in 70 nsec while incrementing the column address. Next, at the address 8, since the row address is switched, it is necessary to transfer the memory cell data to the data register again, and the access time becomes 10 μsec. Further, from address 8 to address F, continuous reading of 70 nsec is performed again.

As described above, in the conventional semiconductor memory, it is necessary to use a program whose read speed is changed in consideration of the number of bits in one page of the semiconductor memory to be used. Therefore, when the number of bits in one page of the semiconductor memory to be used changes, it is necessary to re-create the memory control chip program.

FIG. 31A shows a program sequence of a memory control chip when writing is performed in a semiconductor memory having the same column address and row address configuration as FIG. As shown in the input waveform timing of FIG.
After inputting data for a page, a write operation is started.
For this reason, as shown in FIG. 31A, even when it is desired to write data from address 2 to address 7, it is necessary to input unnecessary dummy data to addresses 0 and 1. For example, one page is composed of 512 bits, and when only one bit is written, it is necessary to input unnecessary data of 511 bits. Further, in a conventional semiconductor memory, it is necessary to perform reading in a program verify mode in order to determine whether or not writing has been normally performed after programming, and to compare with program data to determine whether or not to perform writing again. As described above, when data is written to the conventional semiconductor memory, the program of the memory control chip becomes complicated, and the time for writing data to the semiconductor memory is increased.

As described above, the conventional reading / reading in page units is performed.
Since the writable semiconductor memory is configured as described above, at the time of continuous data reading, the memory control chip determines whether the reading is within the same page address as the previous address or not, so that the number of bits per page is When using different semiconductor memories, it is necessary to change the program of the memory control chip. When a large number of semiconductor memories having different numbers of bits per page are used, the memory control chip needs to individually manage the address length of one page of each semiconductor memory. Further, at the time of writing, it is necessary to input data for one page even when writing with a data length of one page or less, and the time required for writing has been long.

[0011]

SUMMARY OF THE INVENTION An object of the present invention is to provide a system in which the apparent access time is shortened in such a memory system.

[0012]

A non-volatile semiconductor memory according to the present invention includes a plurality of non-volatile memory cells and a plurality of data registers for temporarily storing data of the memory cells. The data for one page is transferred to the corresponding data register, the data for one page transferred to the data register is output to the outside, and at least the data for one page is transferred to the corresponding data register. A non-volatile semiconductor memory for outputting a busy signal indicating that access is impossible to the outside, comprising: a latch circuit connected to the data register; and an output buffer circuit connected to the latch circuit. The busy signal is switched to the ready state after the data of the read start column address of the data Configured as obtain things.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a nonvolatile semiconductor device to which the present invention is applied. For simplicity, column addresses (addresses within a page) are A0 to A2, and row addresses (page addresses) are 1536 of A3 to A8. The figure shows a bit semiconductor memory (512 bits × 3 I / O). The memory cell has an 8 NAND configuration as in the conventional circuit of FIG.
The relationship among the bit line potential, the word line potential, and the gate potential of the selection transistor at the time of reading / writing of the memory cell is the same as in the conventional example. At the time of reading and writing, an external address is input via an I / O buffer circuit, and A0 to A
The column address of 2 is sent to the column address buffer circuit,
The row addresses A3 to A8 are latched in the row address buffer circuit. The command circuit and the internal operation control circuit include external control signals CLE, ALE, NWP, NCE,
NWE and NRE are input from the respective input pins to determine the operation mode of the chip. A signal indicating whether the chip can be accessed or not is sent from the control circuit.
Output to the outside via the / Busy pin. FIG. 2 shows an operation mode of the chip determined by the control signal. The external control signal CLE determines a command input mode, and the external control signal ALE determines an address input mode. Further, the external control signal NCE is a chip select signal, and the external control signal NWE functions as a clock signal for taking in respective input data in the command input mode, the address input mode, and the data input mode. The external control signal NRE is a clock signal having an address increment when reading a continuous address from an input address at the time of reading data and an output buffer enable function. In the semiconductor memory configured as described above, if a glitch occurs in an input data signal and an erroneous command is input, the semiconductor memory may be in a write or erase state and the stored data may be destroyed. For this reason, the semiconductor memory of the present embodiment has a program / erase protection function for defining that the chip does not perform the write operation and the erase operation when the external control signal NWP is in the “L” state. As described above, the Ready / Busy output terminal
If the chip is inaccessible, "L" level Busy
"H" when a signal is output and the chip is accessible
A level Read signal is output.

Next, a read operation of the nonvolatile semiconductor memory of this embodiment will be described. FIG. 3 is a diagram showing an input waveform of a control signal and a data output timing when continuous reading is performed from a column address N and a page address M.

First, in the address input mode shown in FIG.
The column address and the page address are fetched into the address buffer, and at the same time, an “L” level access disable signal indicating a busy state is output to the outside. At this time, as shown in FIG. 3B, the memory cell information connected to the selected word line is output to the bit line and latched by the data register circuit. When this latch operation is completed, an "H" level access enable signal indicating a read state is output to the outside to notify the chip controller that the stored data can be read. Next, data is output to the outside with an access time of 70 nsec while incrementing the in-page address (column address) input by the clock of the external control signal NRE (FIG. 3).
(C)). Next, when the reading of the last address in the page is completed, the page address is incremented, and at the same time, an “L” level access disable signal indicating the busy state is output to the outside, and the read address is connected to the word line selected by the new page address. The latched memory cell information is latched in the data register circuit (FIG. 3D). At the end of the latch operation, an “H” level access enable signal indicating the Ready state is output to the outside, and the page address is incremented from address 0 in the page (column address 0) in response to the clock of the external control signal RE. While outputting data (FIG. 3- (e)). This continuous operation is repeated by the data length of the continuous data to be read,
After the final data reading is completed, the external control signal NCE is set to “H” level, thereby completing a series of reading operations.

FIG. 4 is a circuit diagram showing an address buffer circuit configured to perform the above-described address input and address increment operations. This address buffer circuit includes a binary counter using CMOS transfer gates TG1 to TG4, means for setting the inside of the binary counter to a logic level corresponding to the input address signal, means for resetting the inside of the binary counter to a predetermined logic. It consists of. Dn is connected to an I / O input / output terminal to receive external address information. The data latch control signal LPn is an internal control signal that goes low for a predetermined period in response to the rise of the external control signal NWE in the address input operation mode. The address information of the input / output terminal includes a NOR gate NOR1, an inverter INV1, a NAND gate NAND1, a clocked inverter CINV1,
The data is transferred to the internal nodes N2 and N4 of the binary counter via the clocked inverter CINV2. After a predetermined period, when LPn becomes "H" level, the clocked inverters CINV1 and CINV2 are inactive and the clocked inverters CINV3 and CINV4 are in operation, so that the above-mentioned address information is latched in the binary counter. A signal having the same phase as the latched address information is output to the internal address signal output terminal AiS of the address buffer circuit, and a signal having a phase opposite to that of the latched address information is output to the internal address signal output terminal AiSB. The input terminals Ai-1 S and Ai-1 SB of this address buffer circuit are connected to the internal address signal output terminals of the address buffer circuit immediately before this address buffer circuit, and the internal terminals of the previous address buffer circuit. When the address signal changes by two cycles, the internal address signal of the address buffer circuit changes by one cycle. The internal address signal of each address buffer circuit is input to a corresponding decoder circuit, and a word line and a bit line corresponding to the internal address signal are selected as in the conventional circuit. The reset signal RST sets the internal address signal AiS to the “L” level and the internal address signal AiS
A signal used to reset B to logic "H". When the reset signal RST changes from "L" to "H" to "L", the internal address signal is set to the above-described predetermined logic level. .

FIG. 5 is a circuit diagram for explaining the operation of an address buffer circuit of a 1536-bit semiconductor memory composed of column addresses A0 to A2 and row addresses A3 to A8. The circuits of symbols ABUF0 to ABUF8 in this circuit diagram are the same as the address buffer circuits of FIG. 4, and indicate the address buffer circuits corresponding to the addresses A0 to A8, respectively.

A0 to A2 address buffer circuit ABU
Address latch control signal LP1 is commonly input to F0 to F2, and address buffer circuits ABUF3 of A3 to A5 are input.
5, an address latch control signal LP2 is commonly input to the address buffer circuits ABUF6 to ABUF8 of A6 to A8. The data input / output terminals Dn of the address buffer circuits ABUF0, 3, 6 are commonly connected to the input / output terminals of the I / O0, and the data input / output terminals Dn of the address buffer circuits ABUF1, 4, 7 are commonly connected to the I / O1. Connected to input and output terminals. Further, address buffer circuits ABUF2, 5,
Eight data input / output terminals Dn are commonly connected to input / output terminals of I / O2. A reset signal input terminal of the address buffer circuit of A0 to A2 has a signal RST which becomes "H" level for resetting the inside of the chip at power-on, and clears the contents of the address register in a data register read mode described later. Therefore, the signal of the OR logic of the signal DATAPUL which becomes "H" level is input.

The operation of the circuit of FIG. 5 will be described below for the case of the read mode operation of FIG. When the external control signal NWE changes from “H” → “L” → “H” level to input address data from the data input terminal, “H” →
An address latch control signal LP1 of a pulse that changes from “L” to “H” level is generated. At this time, the other address latch control signals LP2 and LP3 are held at logic "H". As a result, as described above, the data input / output terminal I / O
The address information supplied to 0, 1, and 2 is latched by the address buffer circuits A0 to A2, and the internal address signal is set to a logical level corresponding to the input address information. Next, in order to input address data from A3 to A5, A3 is input from I / O0 to I / O2.
When the external control signal NWE changes from “H” → “L” → “H” level when the address data from
An address latch control signal LP2 of a pulse that changes from “H” → “L” → “H” level is generated. At this time, the other address latch control signals LP1 and LP3 are held at logic "H".

As a result, the data input / output terminals I / O0,
Address information from A3 to A5 supplied to the address buffer circuits A1 and A2 is stored in the address buffer circuits ABUF3 to ABUF3, respectively.
The internal address signal is latched by the UF 5 and set to a logic level corresponding to the input address information. Finally, the address data from A6 to A8 is input from I / O0 to I / O2, and the external control signal NWE is changed from "H" to "H".
When changing from “L” to “H” level, “H” → “L”
→ The address latch control signal LP3 of the pulse which changes to "H" level is generated, and the address data from A6 to A8 is latched by the address buffer circuits ABUF6 to ABUF8. As described above, the address information of A0 to A8 supplied to the I / O input / output terminal is input to each address buffer in three steps of the NWE pulse.

FIG. 6 shows the aforementioned address latch control signal LP.
FIG. 2 is a circuit diagram illustrating a circuit that generates 1 to LP3. The shift registers represented by symbols are shown in FIG.
9 illustrates a shift register circuit illustrated in FIG. When the address data is input, this circuit LA goes high for a predetermined period in response to the rise of the external control signal NWE.
Receiving the TPULA signal, it forms negative data latching pulse signals LP1, LP2 and LP3. When the power is turned on and when the external control signal ALE changes from “H” to “L” level, the output of the first shift register is “H” level because the reset signal ARST is at “H” level for a predetermined period.
The outputs of the second to fourth shift registers are initialized to "L" level. Next, when address data is input, when a positive logic LATPULA signal is output in response to the NWE clock of the first step, the output signal of the first shift register is at "H" level, so that the NAND gate N
Negative logic address latch control signal LP via AND2
1 is output. The shift register advances one stage in response to the fall of the pulse signal LATPULA, the output of the second shift register is at "H" level, and the outputs of the first, third, and fourth shift registers are at "L". Level. Next, when the LATPULA signal is output again in response to the NWE clock of the second step, since the output signal of the second shift register circuit is at "H" level, the address latch control signal of negative logic is output via the NAND gate NAND3. LP2 is output. The shift register further advances by one stage in response to the falling edge of the pulse signal LATPULA, and the output signal of the third shift register goes high.
The output signals of the first, second, and fourth shift registers are “L”
Level. Similarly, the address latch control signal LP3 is output via the NAND gate NAND4 in response to the third step NWE clock. N of the third step
When the address input is completed by the WE clock, the output signal of the fourth shift register becomes "H" level, and the CL of each shift register, which is the output signal of the NOR gate NOR2, is output.
The OCK input signal is held at the “L” level. At this time, the CLOKB input signal of each shift register is held at "H" level by the NAND gate NAND5. Therefore, even if the NWE clock signal of the fourth and fifth steps is input and the pulse signal LATPULA is generated, the output signals of the first, second and third shift registers hold the "L" level, and the address latch control is performed. The signal is not output.

When the address input is completed by the three-step NWE clock signal in this manner, the Busy signal is output in response to the level change of the third latch data control signal LP3, and the address buffer corresponding to the row address is output. The word line corresponding to the internal address signal of the circuit is selected. After a predetermined (10 μsec) delay time, the control gate is connected to the selected word line.
Memory cell data for a page is read out via a bit line and latched in a data register.

Next, a read operation when the external control signal NRE is changed from "H" to "L" to "H" to read the contents of the data register will be described with reference to FIGS. The pulse signal PUL is a signal output when the external control signal RE is changed from "H" to "L" level in the serial read operation mode. The signal PUL and its inverted signal PULB are input terminals of the address buffer circuit A0, respectively. Ai-1S and Ai-1SB. However, when reading the first column address after inputting the address and when reading the first column address after switching the page address and rewriting the data register contents, Re
The pulse signal PUL is configured not to be output in response to the change of the ad / Busy signal from “L” to “H” level. When the external control signal NRE is changed from “H” to “L” level after the address input (FIG. 9 shows the case where the column address = 4 is input) in the semiconductor memory configured as described above, the data register of address 4 The contents are output to the I / O input / output terminal, and the I / O input / output terminal changes from the high impedance state to a predetermined level. At this time, since the pulse signal PUL is not generated as described above, the binary output signal (= internal address signal) of the address buffer circuit does not change. Next, when the external control signal NRE changes from “L” to “H” level, the I / O input / output terminal enters a high impedance state. When the external control signal NRE changes from “H” to “L” level again, a pulse signal PUL is generated this time, so that the internal address signal A0S of the address buffer circuit ABUF0 changes from “L” to “H” level. Thereafter, the contents of the data register (column address = 5) selected by the internal address signal are output to the I / O input / output terminal. After that, the external control signal NRE is changed from “L” to “H”.
When the level changes to a high level, the I / O input / output terminal enters a high impedance state. Next, the external control signal NRE becomes “H” →
When the internal address A0S changes to "L" level, the internal address A0S changes from "H" to "L" level by the pulse signal PUL, and in response to the change of A0S, the internal address signal which is an output signal of the address buffer circuit ABUF1. A
1S also changes from “L” to “H” level. As described above, the internal address determined by the internal address signals A0S, A1S, A2S is incremented by the signal PUL. In the fourth step, the external control signal NRE is changed from “H” →
When the internal column address signal changes to "L" level, all the internal column address signals change to "H" level, so that the signal COLEND changes from "L" to "H" level. This signal COLEN
When D is at “H” level, external control signal RE is at “L” level.
When the signal changes to "H" level (the fourth step), the pulse signal PUL is output, the internal address is incremented, and the Ready / Busy signal changes from "H" to "L" level. As described above, the internal column address after the continuous reading from the address specified by the input address to the last address of the column indicates the address 0 by the clock of the external control signal NRE, and the row address ( Page address) is incremented. Also BU
In response to the output of the SY signal, the memory cell data whose gate is connected to the newly selected word line is transferred to the data register after a predetermined read time (10 μsec),
READY signal indicating that the chip is accessible
Output to Ready / Busy output terminal. Chip is Read
When the read operation is performed by inputting the clock external control signal NRE after changing to the y state (fifth step), the Ready
Since this is the first read operation after the / Busy signal changes from “L” to “H” address, the signal PUL is not output, and
The contents of the data register at column address 0 are I / O
Output to O input / output terminal.

Thereafter, when reading is performed by the clock of the external control signal NRE up to the last address of the column, the Busy signal is output again to the Ready / Busy output terminal as described above, and the memory cell data of the next page address is output. Is transferred to the data register. When reading the last address of the internal address, the signal COLEND becomes “L” →
The signal AEND also changes from “L” to “H” level while changing to “H” level. After the last address is read, the next external control signal NRE is set so that the read operation is not performed. Therefore, when the signal AEND changes to "H" level after the last address read, the READY signal is held at the Ready / Busy output terminal, and the external control signal NRE changes from "L" to "H" level. However, the pulse signal PUL is not output. Since the BUSY signal is not output, the transfer of the memory cell data to the data register is not performed. in this way,
When reading is performed up to the last address of one chip, the signal AEND is incremented so that the memory cell data at address 0 is not read out.
Is controlling.

FIG. 10 shows a program sequence of the memory control chip when continuous data reading is performed in the semiconductor memory thus configured. In the semiconductor memory chip of this embodiment, if the chip is accessible, reading is always possible with the same access time (70 nsec), and a program for determining whether the column address (in-page address) is the last address is required. And not. Therefore, there is no need to change the memory control chip program even when a chip having an arbitrary address length within a page is used. Even when a large number of memories are used, a large number of memories can be managed with a simple memory control chip program. There is. FIG. 11 shows a continuous example in the case of using a large number of semiconductor memories configured as described above. By using the external control signal NCE as the most significant address, this system can be used in one semiconductor memory. It is possible to manage as a single semiconductor memory having a memory capacity equal to or larger than the capacity.

FIG. 12 is a diagram showing an input waveform of an external control signal and data input timing when writing to the above-described semiconductor memory. First, when the serial data input command 80H is input in the command data input mode, the chip enters an address input mode for inputting a program start address. In the address input mode, the column address and the page address are fetched into the respective address buffer circuits by the three-step clock of the external control signal NWE as in the above-described read mode, and each internal address signal is converted into a predetermined logic corresponding to the input address data. Set to level. In the above-described read mode, after inputting the address information in the third step, a Busy signal is output to the Ready / Busy output terminal and the memory cell data is transferred to the data register. In the serial data input mode, the Ready / Busy output terminal is used. The read operation of transferring the memory cell data to the data register is not performed. When serial data input command 80H is input, all data in the data register is initialized to "H" level.

This operation will be described with reference to the data register circuit of FIG. 13 and the timing chart of FIG. FIG. 13 shows a data register circuit provided for each bit line, and includes clocked inverters CINV5 and CINV.
Reference numeral 6 functions as a data latch, and clocked inverter CINV5 functions as a sense amplifier when reading data. The N-channel transistor whose gate is supplied with the signal PRE is used for precharging the data latch unit. At this time, the bit line and the data latch unit are electrically separated by the N-channel transistor whose gate is supplied with the signal BLCD. . Further, the data register circuit is connected to a common bus line IOi / IOiB provided for each I / O via a column gate transistor whose gate receives a column decoder output signal CSLj. First, the serial data input command 80
When H is input from the I / O input / output terminal, signals SENB, SENB,
RLCHB goes to “H” level, and signals SEN and RLC
Since H changes to “L” level, the clocked inverters CINV5 and CINV6 become inactive. At the same time, the precharge signal PRE changes to “H” level, so that the nodes BLj in all data registers are precharged to “H” level. After the precharge operation, the signal SEN changes from “L” to “H” level, and the signal RLCB
Changes from “H” to “L” level, and node NBLj is set to “L” level. Thus, the node BL
After the setting of j and NBLj is completed, the signal SENB changes from “H” to “L” and the signal RLCH changes from “L” to “H” level, and the setting data is latched in the data register circuit. . By this initialization operation, the nodes BLj of all the data registers are set to the “H” level, and the data of all the data registers are set to “1”. After that, when the address input operation is completed, the signal SD
Since the IC changes from “L” to “H” level, write data and its inverted data are transferred from the I / O input / output terminal to the common bus line IOi / IOiB. Next, while the external control signal NWE is at the "L" level, the column decoder output signal CSL6 corresponding to the input column address (address 5) is at the "H" level. Buffer inverters BUF1 and BUF2 for driving a common bus line
Is set to be sufficiently larger than the clocked inverters CINV5 and CINV6, the latch content of the data register selected by the column decoder output signal CSL6 is rewritten with the write data on the common bus line. As a result, data is input from the address 5 to the address 7 by the clock of the external control signal NWE. As a result, the contents of the data registers from the address 0 to the address 4 of the column are latched with the data "1" at the time of initialization. The data input from the I / O input / output terminal is latched at column addresses 5 to 7. When a program command 10H is input in the command input mode after the data input mode, the chip writes data to a memory cell.

[0028] During the data writing, the power VBITH latch circuit is changed to VDPI potential of 10V from V _cc potential. At the same time, the potential of the signal BLCD changes from 0V to 12V.
And the bit line and the latch circuit are electrically connected. As a result, the bit line whose data in the data register is "1" is set to the VDPI potential and the bit in which the data in the data register is "0" is set. Line is set to 0V.
For this reason, the data of the data register is connected to the bit line of "0", electrons are injected into the floating gate of the memory cell selected by the word line, and "0" data is written to the memory cell. Ready during the above write operation
The Busy signal is output from the / Busy output terminal, and after a predetermined writing time has elapsed, the READY signal is automatically output. Whether this write operation has been completed normally depends on whether 70H
, The result of the automatic verification stored in the internal register can be read from the I / O input / output terminal. Such a flag read function is a function that has been put to practical use in a conventional semiconductor memory, and a description thereof will be omitted.

FIG. 15 shows a memory control chip program sequence when data is written from addresses 2 to 7 of the semiconductor memory configured as described above. By using the semiconductor memory according to the embodiment of the present invention, data can be input from an intermediate address in one page, and data before the start column address can be automatically initialized to predetermined data. There is no need to execute the dummy data input instruction shown in the conventional example of FIG. 31, and the program time can be reduced.

Next, the address register read function of the semiconductor memory of this embodiment will be described. In this function, the internal address is normally latched after the address is input at the time of data reading and data writing, or is latched in the address register while the internal address is being incremented by the external control signal NWE clock. Used to read internal address information.

FIG. 16 is a diagram showing the input timing of the external control signal when the contents of the address register are read out in the circuit of this embodiment. FIG. 17 is a circuit diagram of an output buffer circuit of the nonvolatile semiconductor device according to the present embodiment.
8 is the signals AREG1 to 3 and NAREG1 to 3 of FIG.
FIG. 3 is a circuit diagram of an address register read control circuit for generating the signal of FIG. The first shift register and the second to fourth shift registers in FIG. 18 represent the shift register circuits of FIGS. 7 and 8, respectively. First, when E0H is input in the command input mode, the chip enters the register read mode, the signal ADDR in FIG. 18 changes from “L” to “H” level, and the positive logic pulse signal ARRST for a predetermined period causes Output nodes AS1, AS2, AS3, A of each shift register in FIG.
S4 is reset to "H", "L", "L", and "L" levels, respectively. If the chip is in the read mode before the register read mode, the control signal READ / NREAD of the clocked inverter CINV7 in FIG.
Are at the “H” / “L” level, respectively, so that the data of the common bus line IOoB detected by the current mirror circuit CM is transferred to the node OUT. Next, in the register read mode, the signal READ changes from “H” to “L” level, so that the clocked inverter CINV7 is in an inactive state.
Since the latch circuit LAT formed by the inverter set to be smaller than 0 is connected, the level of the node OUT is maintained at the level before the register read mode. Next, in order to read the contents of the address register, when the external control signal NRE is changed to "L" level, the level of the node ADR in FIG. 18 changes from "L" to "H" level, and the signal AREG1 is changed to "L" of the node AS1. "H" level changes in response to the "H" level. Therefore, clocked inverter CINV8 shown in FIG.
Data corresponding to the logic level of the internal address signal AOS is latched in the UT. The signal BUS in FIG. 17 is Ready
/ Busy internal BU of opposite phase to the signal output to the input / output terminal
Since the signal is an SY signal and the chip is accessible in the register read mode, the signal BUS is at the “L” level. Therefore, the external control signal NRE becomes "L".
When the level changes to the level, the node OE changes from “L” to “H” level, and a signal having the same phase as the internal address signal A0S latched at the node OUT is output to the input / output terminal I / O0. At this time, the input / output terminals I / O0, 1, 2 are configured to output signals having the same phase as the internal address signals A0S, A1S, A2S, respectively. Addresses A0 to A2 can be read simultaneously.
Next, when the external control signal NRE is changed from “L” to “H” level, the node ADR becomes “L” level, and the clocked inverter CINV8 is deactivated. Further, in response to the change of the external control signal NRE, a negative logic pulse signal AREGPUL is formed as shown in FIG.
8 shift register output node AS1 goes from “H” →
Go to “L” level and output node AS2 goes “L” →
It changes to “H” level. Therefore, the signal AREG2 changes to "H" level when the external control signal NRE changes from "H" to "L" level in the second step, and the data corresponding to the logic level of the internal address signal A3S via the clocked inverter CINV9. Is latched at the node OUT. At this time, the level of the node OE also changes from “L” to →
Since it changes to “H”, a signal having the same phase as the internal address signal A3S is output to the input / output terminal I / O0. At the same time, the I / O1 and I / O2 are configured to output signals having the same phase as the internal addresses A4S and A5S, respectively. In the second step, when the external control signal NRE changes from “L” to “H” level, the pulse signal AREG
Due to PUL, the output node AS2 of the shift register circuit of FIG. 18 goes from “H” to “L” level, and the output node AS
3 changes from "L" to "H" level. When the external control signal NRE changes from “H” to “L” level in the third step, the internal address signal A6S is responded to the signal AREG3.
Is output to the input / output terminal I / O0. At this time, the input / output terminals I / O1 and I / O2 are configured to output signals having the same phase as the internal address signals A7S and A8S, respectively. External control signal R at the third step
When E changes from “L” to “H” level, the output node AS4 of the shift register changes to “H” level.
The output level of the shift register does not change in response to the signal AREGPUL. Therefore, even if the external control signal NRE clock of the fourth step is input, the signals AREG1 to AREG1 are output.
3 is not at the "H" level, and a signal having the same phase as the internal address AOS latched at the node OUT is output to the input / output terminal I / O0. When the register read command EOH is input again, the pulse signal ARR
The contents of the shift register are reset by ST, and the internal addresses A0 to A8 can be read again.

Next, the data register read function will be described. This function is used to confirm the contents of the data register after data input in the write mode. FIG.
As shown in (1), when the register read command EOH is input in the command input mode, a positive logic pulse signal DATAPULL for clearing the internal column address latched in the address buffer circuit of FIG. 5 to address 0 is generated. Therefore, as described in the above-described read operation, when the external control signal NRE is input by a clock, the contents of the data register input in the data input mode can be continuously read from the internal address 0 to the last column address. . However, in the read mode described above, when the last column address is read, Re
The Busy signal is output from the ady / Busy output terminal,
In the register-read mode, the ready / busy output terminal responds to the level change of the signal ADDR.
The configuration is such that the Ady signal is held and the Busy signal is not output. Further, when the last column address is read in the above-described read mode, the row
Although the address is incremented, in the register-read mode, the signal ADDR is controlled so that the row address is not incremented. Therefore, even if the write operation is performed after confirming the contents of the data register in the data register read mode, the contents of the data register can be normally written to the memory cell at a predetermined row address input before the data register read mode. Can be performed.

Next, the operation of resetting the internal address register and the data register when the power is turned on in the semiconductor memory of this embodiment will be described. In this embodiment, the internal address register and the data register are reset by setting the external control signal NWP to "L" level at power-on and setting the external control signal NWP to "H" level after power-on. Is done. The external control signal NWP is executed in order to prevent noise from occurring in other external control signals and prevent the chip from erroneously rewriting the contents of the data register and writing / erasing data to / from the memory cells. This is an external control signal provided to control whether or not it is possible. As shown in the operation mode table of FIG. 2, when external control signal NWP is at "L" level, the chip is configured such that data input, program / erase, and data transfer from a memory cell to a data register are not performed. You. To inhibit the data input operation, when the external control signal NWP is at "L" level, the signal PUL of FIG.
Is held at the "H" level so that the increment operation of the internal address is not performed, the generation of a precharge signal PRE for resetting the data register circuit of FIG. 13 and the generation of signals SEN / SENB, RLCH /
The data transfer and the latch operation of the data register from the common bus line by RLCH5 and CSLj may be prohibited.

FIGS. 21 (a), 21 (b) and 21 (c) are circuit diagrams of a program / erase command input circuit.
DWES is an external control signal N in command input mode.
The signal changes from “H” to “L” level in response to WE. CMDWESB is a signal of the opposite phase to CMDWES. Therefore, when a predetermined command code is input to the I / O input / output terminal in the command mode, the control signal of the corresponding command input circuit goes high. Since the internal operation of the program / erase is controlled by the output signal RROG / ERASE of each command circuit shown in FIG. 21, the signal RROG / ERASE becomes “H” level with the internal signal WPSB in the same phase as the external control signal NWP. , The program / erase operation is not performed when the external control signal NWP is at "L" level. Further, the data transfer operation from the memory cell to the data register is performed by detecting that the internal signal having the opposite phase to the signal output to the Ready / Busy output terminal changes from "L" to "H" level. , The aforementioned internal signal WP
By holding this signal at "L" level at SB, the data transfer operation is prohibited when external control signal NWP is at L level. As described above, the external control signal NWP is used for rewriting the contents of the data register, writing data to the memory cell /
It is used to inhibit the erase operation and to initialize the contents of the internal address register and data register when the power is turned on. FIG.
(C) shows a reset pulse generation circuit. When the external control signal NWP changes from “L” to “H” level, a reset pulse RST of positive logic is generated. This reset signal RST is input to the address buffer circuit of FIG. 4, and the output signals AiS of all the address buffer circuits are set to "L" by the positive logic reset signal RST.
The internal address is reset to address 0. The reset signal ARST input to the data latch control signal generation circuit shown in FIG. 6 is also output in a positive logic corresponding to the reset signal RST, so that the level of the output node of the shift register of the data latch control signal generation circuit is also low. The predetermined level is set as described above. The reset signal ARRST input to the address register read control circuit shown in FIG. 18 is also output in response to the reset signal RST, so that each output node of each shift register circuit is reset to the above-described predetermined level. The latch data of each data register is the reset signal RS
It is reset to "1" data by T. This signal RS
The reset operation by T is the same as the data register initial setting operation after inputting the data input command 80H in the data input mode, and the column gate transistor CSL
j is in a non-conductive state, a precharge operation by the signal PRE, and the signals SEN / SENB and RLCH / RLCH
B performs a latch operation. In the nonvolatile semiconductor device thus configured, when power is turned on, the external control signal NC
External control signal NWP even if E, CLE, ALE are undefined
Is fixed to "L" level, malfunction of writing / erasing can be inhibited. After the power supply voltage reaches a predetermined level, the external control signal NWP is changed from "L" to "H" level. It is possible to reliably reset the latch circuit inside the chip.

Next, still another embodiment of the present invention will be described. FIG. 32 shows an address buffer circuit, and the address buffer ABUF indicated by a symbol is the same as that of the first embodiment. In this embodiment, a further latch circuit ACLi is connected to the output side of the column address buffers A0 to A2. The contents of the symbol notation are as shown in FIG. The latch control signal REP,
REPBs are signals having phases opposite to each other. When REP becomes "H", the output signals A of the address buffers ABUF0 to ABUF2 are output.
0 to 2 are held, and data is held while REP is “L”. By storing the current address in the latch circuit in this way and incrementing the address data of the address buffer circuit itself in advance, the time required for incrementing the address buffer circuit can be shortened.

FIG. 35 shows a circuit for transferring the data latched in the data register to the data output buffer. SDiB is a signal after the data latched in the data register is input to the current mirror type sense amplifier through the bus lines IOi and IOiB in FIG. 13 and amplified. SDiB is input to the latch A when the signal CENA becomes “H”, and when CENA becomes “L”.
Then, the latch A holds the data. Further CENB
When B becomes "H", data is transferred to latch B, and CE is latched.
When NBB becomes “L”, the latch B holds data. By using such a circuit, the data of the next address can be taken into the latch A from the data register while outputting the data of the latch B to the outside of the chip.

A case where the circuit of the present invention is applied to a serial read will be described. FIG. 34 is a timing chart showing the operation of main signals for one cycle of random access and serial access. The signal PRE,
BLCD, SEN, SENB, RLCH, and RLCHB are the signals shown in FIG.
It changes as shown in FIG. After inputting the address for three steps or after serial access, random read is started, and after entering the Ready state, the word line selected in the previous operation is deselected and the word line to be accessed is selected. Thereafter, the signal PRE becomes "H", and the bit line and the data register are precharged. At this time, the BLCD is at "H", and the bit line and the data register are connected. After that, the PRE becomes “L”, and then the signal SEN changes from “L” → “H” →
When “L” and RLCHB change from “H” → “L” → “H”, the “H” level is latched at the node BLj in the data register. Thereafter, the signal RDENBR becomes “H”, and a predetermined voltage is set to the control gate of the selected 8 nd cell. After a predetermined time, the signal S
When EN changes from “L” to “H” and SENB changes from “H” to “L”, CINV5 in FIG. 15 is activated to sense read data. Thereafter, when RLCH changes from “L” to “H” and RLCHB changes from “H” to “L”, sense data for one page is latched. Thereafter, after a predetermined time, the data at the column head address is transferred from the data register to the output latches A and B in FIG. That is, the output gate CSLij of the data register corresponding to the head address opens in response to the signal CEN, and the data is transferred to the current mirror type sense amplifier. At the same time, CENAB is changed from “H” → “L” → “H”
By doing so, this data is transferred to the latch A. At this time, CENA changes from “L” → “H” → “L”. CENBB is a signal that operates with a waveform that is substantially in phase with NRE, and CENAB is initially “H” → “L” →
When the signal changes to “H”, the input gate of the latch B is open, and data is transferred to the latch B. At the same time,
The column address counters ABUF0 to ABUF2 are incremented once by PUL1, and the output indicates the next address. However, since REP remains at the “L” level, the internal address remains at the head address. Perform the above operation within the random access time,
The Ready / Busy signal is set to “H” to notify the outside of the chip that the random read has been completed. Subsequently, when serial access is performed, when the external control signal NRE becomes “L”, the head address data is output from the latch B to the outside through the data output buffer. At the same time, the chip performs an operation of transferring the data of the next address to the latch A. That is, in response to the clock input of the control signal NRE for outputting the data of the head address, the signal R
The EP is output, and the data of the next address of ABUF0 to ABUF2 is taken into the address output latches ACL0 to ACL2 (then, the column address buffer is incremented by the signal PUL1 and the data of ABUF0 to ABUF2 indicates the next address). . The data of the next address is transferred to the latch A from the data register corresponding to the next address by the signals CEN and CENAB. After that, the control signal NR
When E becomes “H” and the data output of the head address is completed, CENBB also becomes “H”, and the data of the next address of the latch A is moved to the latch B. As described above, by outputting the data at address n in response to the clock input of the control signal NRE and simultaneously transferring the data at address n + 1 from the data register, the serial access time seen from the outside of the chip is It is time to output through the data output buffer, and the cycle time of data output can be shortened. In this embodiment, the data in the address buffers ABUF0 to ABUF2 indicates the address two ahead of the data being output at that time, and the data in the address output latches ACL0 to ACL2 indicates the address one ahead. Therefore, a signal for incrementing the row addresses A3S to A8S is required after outputting the data of the last address of the column. As shown in FIG. 32, in this embodiment, a signal PUL2 is input as an input signal of the address buffer ABUF3. FIG. 35 shows the signal PU.
The circuit which outputs L2 is shown. When serial access is performed by the NRE clock to output data at the address immediately before the last address of the column, the address output latches ACL0 to ACL2 indicate the last address of the column. Correspondingly, a signal COLEND indicating the last address of the column
Is output. When the clock of the control signal NRE is input to output the data at the last address of the column, the circuit of FIG. 36 outputs a pulse signal to the node NA in response to the fall of NRE. At this time, "H" is input to the other gate of NAND1, so that flip-flop F1 is set, and node NB attains "H" level. When the control signal NRE becomes "H" after outputting the data of the last address, PUL2 is output through NAND2.
Until the flip-flop F1 is reset through the delay circuit delay3.
Maintain the "H" level. The delay time of the delay circuit delay2 is such that COLEND is “H” immediately before the last address of the column.
The level is set so that a pulse output to the node NA by the clock of the control signal NRE at that time is not picked up. As described above, when the output of the data of the last address is detected, PUL2 is output, the address buffers A3 to A8 are incremented, and random access to the next page is performed.

Next, an example in which writing can be properly performed even when a defective bit line exists will be described.

FIG. 37 is a flow chart for explaining an internal preset operation after a data input command is input in the above-described chip of this embodiment. When writing is performed in this sequence, if there is a defective bit line in which the bit line wired with Al is short-circuited to the source line, there is a problem as described below.

That is, the column address of such a defective bit line is usually stored in a redundancy circuit by cutting a fuse or the like. When an address of the defective bit line is selected, a column redundancy bit line is selected instead of the defective bit line. However, the precharge operation and the initial data preset operation of the data register shown in FIG.
This is performed for all bit lines regardless of the column address. Therefore, as shown in FIG. 13, the data register of the defective bit before being remedied by the redundancy circuit is also preset to the write inhibit “1” data because the transistor to which the signal PRE is input to the gate becomes conductive. You. In this case, the following problem occurs. In the data latch circuit of FIG. 13, the power VBITH latch circuit of the data register from the external power supply V _cc, the power is supplied by a booster circuit built-in chip VDPI (10V), switches, and signal BLCD 0
V changes to 12 V of the internal power supply. At this time, the node BL of the data register to which the above-mentioned defective bit line is connected is connected.
Since j is at a high level due to the above-described preset operation, the P-channel transistor of the clocked inverter CINV6 is conducting, and the power supply VBIT
A leak current flows from H to the ground potential. Power supply VDP
Since I is the output of the booster circuit, the current supply capability is usually 1
As small as mA or less. Therefore, when a leak current flows through a defective bit line, the potential of the power supply VDPI falls below 12V. Along with this, the bit line potentials of the other write inhibits also fall below 12 V, causing a problem of erroneous writing.

FIG. 38 is a flow chart showing a write operation of another embodiment of the present invention in which this problem is solved. FIG. 39 shows the sense amplifier of this embodiment.
FIG. 3 is a circuit diagram of a data register. In the present embodiment, when a data input command is input, each bit line is charged via the N-channel transistor TrN1 connected to each bit line. After a predetermined read time after charging the bit line, the signal BLCD is set to the high level, and the data of the bit line is transferred to the data register. During this predetermined time, all select lines are set to a non-selected state. As a result, the level of the bit line having a leak is reduced to a low level, and the level of a normal bit line having no leak is maintained at a high level. The level of this bit line is latched in the data register. Such a bit line leak test is performed, and “0” data as write data is latched in the data register to which the defective bit line is connected, regardless of the data in the memory cell, and the level of the node BLj in the data register is Is preset to a low level. The data register connected to the normal bit line latches "1" data as write data, and presets the level of the node BLj in the data register to a high level. As shown in FIG. 38, when the bit line leak test mode ends, write data is input to the data register from a predetermined address specified in the address input mode, and thereafter, writing is performed.

As described above, in this embodiment, at the time of writing, the content of the data register connected to the defective bit line is "0" data. Therefore, the P-channel transistor TrPl of the clocked inverter CINV6 in the data register is in a non-conductive state. Therefore, even when the writing operation is started and the BLCD becomes 12 V, no leak current flows from the power supply VBITH to the ground, and the voltage of VBITH does not decrease.

The data register preset operation by the bit line leak test may be configured to be performed, for example, when a reset command such as FF is input. That is, in this case, the FF reset command is executed before the start of writing, that is, before the data input command is input. As a result, the contents of the data register connected to the defective bit line are preset to "0" data, and the contents of the data register connected to the normal bit line are set to "1".
Preset to data. Thereafter, the system may be configured to execute a data input command, input data from a predetermined address, and then perform a write operation.

As described above, according to the embodiment of the present invention, after the contents of the data register for one page are continuously read from the input address, it indicates that the chip cannot be accessed. The BUSY signal is output to the outside of the chip, the row address is automatically incremented, and the data of the memory cell can be transferred to the data register. Long memory data can be read continuously.

When data from a predetermined address specified by the input address to an arbitrary address is input, the contents of the data register of the address in one page are automatically recognized as a predetermined value. When performing writing of a smaller size, writing can be performed without inputting data for one page, so that the time required for writing can be reduced. further,
Since the chip internal reset operation at power-on is performed by the program / erase protect signal, the chip contents can be reliably reset without using a power-on reset circuit.

[0046]

According to the present invention, a latch circuit is provided between a data register and an output circuit to perform a pipeline operation, and a busy signal is switched to a ready state after transferring data to the latch circuit. The apparent access time can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor memory of the present invention,
FIG. 4 is a block diagram in which Ready / Busy output is performed from a control circuit.

FIG. 2 is a diagram illustrating an operation mode of the semiconductor memory of the present invention, in which “Read / Busy” is “L” in “program erase” and “read (cell → register)” modes.

FIG. 3 is a timing chart of a read operation of the semiconductor memory according to the present invention, and FIG.
FIG. 4 is a timing chart in which the state is set to “Busy” in FIGS.

4 is a circuit diagram of an address buffer circuit according to the present invention, showing a detailed circuit of a block ABUF in FIG. 5, wherein an initial value can be directly set from a data input terminal I / On.

FIG. 5 is a circuit diagram of an address input unit according to the present invention,
FIG. 3 is a circuit diagram illustrating a binary counter.

6 is a circuit diagram of an address latch control signal generation circuit according to the present invention, wherein a latch pulse LP1 for latching an initial value in each group (upper, middle, and lower) of a binary counter as the address input means in FIG. 5; ~ Circuit diagram for generating LP3.

FIG. 7 is a circuit diagram of a shift register circuit, showing details of a first shift register in FIG. 6;

FIG. 8 is a circuit diagram of a shift register circuit, showing details of a second shift register in FIG. 6;

FIG. 9 is an internal signal timing chart for explaining the operation of the address input means of FIG. 5;

FIG. 10 is a sequence diagram of a control program for reading the semiconductor memory of the present invention.

FIG. 11 is a connection example in a case where a large number of semiconductor memories of the present invention are connected and used, in which control signals such as Ready / Busy are commonly connected.

FIG. 12 is a timing chart of a write operation of the semiconductor memory of the present invention, in which a column address, a row address, and write data are taken in after a data input command 80H;

FIG. 13 shows a data register circuit for initializing register data to “1” before data input.

FIG. 14 is a timing chart of a write operation of the semiconductor memory of the present invention.

15 is a write control program sequence diagram of the semiconductor memory of the present invention, and FIG.
FIG. 4 is a sequence diagram in which the input of dummy data required in step 1 is unnecessary.

FIG. 16 is an operation timing chart for explaining a register read operation of the semiconductor memory of the present invention, in which a command mode is set according to a combination of control signals, a register read command E0H is fetched, and address data and register data are output. FIG.

FIG. 17 is a circuit diagram of an output circuit of the semiconductor memory of the present invention.
(Output buffer.)

FIG. 18 is a circuit diagram of the address register read control circuit of the present invention, which generates a control signal for transferring an address from an binary counter to an output buffer.

FIG. 19 is an internal signal timing chart for explaining an address register read operation of the output circuit of FIG. 17;

FIG. 20 is a timing chart of a reset operation when the power of the semiconductor memory of the present invention is turned on (see [0038]).

FIG. 21 is a diagram illustrating a command circuit and a reset signal generation circuit (see [0039]) for explaining a reset operation at the time of power-on of the semiconductor memory of the present invention.

FIG. 22 is a diagram illustrating a memory cell operation in NAND connection.

FIG. 23 is a diagram for explaining the operation of the memory cell, and shows the correspondence between charge injection and data.

FIG. 24 is a diagram illustrating a memory cell operation (erase operation).

FIG. 25 is a view for explaining a conventional read operation.

FIG. 26 is a block diagram of a conventional nonvolatile semiconductor device without Ready / Busy output.

FIG. 27 is a table illustrating operation modes of a conventional nonvolatile semiconductor device.

FIG. 28 is a timing chart of a read operation of a conventional nonvolatile semiconductor device (see [0007]).

FIG. 29 is a timing chart of a write operation of a conventional nonvolatile semiconductor device.

FIG. 30 is a control program sequence diagram for reading out a conventional nonvolatile semiconductor device.

FIG. 31 is a control program sequence diagram for writing a conventional nonvolatile semiconductor device, and is a sequence diagram in a case where input of dummy data is required.

FIG. 32 shows another example of an address buffer circuit capable of performing a pipeline operation.

FIG. 33 is a detailed diagram of a latch circuit. (Details of the ALCi block in FIG. 32)

FIG. 34 is a timing chart of main signals in one cycle of random access and serial access in the address buffer circuit of FIG. 32;

FIG. 35 is a circuit for transferring data in a data register to a data output buffer. (Realizes pipeline operation.)

FIG. 36 illustrates a circuit that outputs a pulse signal PUL2 ([00
42]).

FIG. 37 is a write operation flowchart including a data register initialization operation of the present invention.

FIG. 38 is a write operation flowchart including an operation of initializing a data register by a bit line leak test of the present invention.

FIG. 39 is a circuit diagram as an example of a sense amplifier / data register for implementing the bit line leak test of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Drain side select line 103 Source side select line 105 Column address buffer 107 Row address buffer 109 Command decoder 111 I / O terminal

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Masamichi Asano 580-1 Horikawa-cho, Sachi-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Semiconductor System Technology Center Co., Ltd. (72) Inventor Yoshiyoshi Tokushige, Kawasaki-shi, Kanagawa 580-1, Horikawa-cho, Ward Toshiba Semiconductor System Technology Center Co., Ltd. (72) Inventor: Toshio Yamamura 580-1, Horikawa-cho, Saiwai-ku, Kawasaki City, Kanagawa Prefecture F-term (Toshiba Semiconductor System Technology Center) 5B025 AA03 AB01 AC01 AD00 AD01 AD04 AD05 AE05

Claims (6)

[Claims] A plurality of nonvolatile memory cells; and a plurality of data registers for temporarily storing data of the memory cells, wherein data of one page selected from the memory cells is stored in a corresponding one of the data registers. And transferring one page of data transferred to the data register to the outside, and outputting a busy signal indicating that access is disabled to the outside while transferring at least the one page of data to the corresponding data register. A non-volatile semiconductor memory, comprising: a latch circuit connected to the data register; and an output buffer circuit connected to the latch circuit. A non-volatile semiconductor memory, wherein the busy signal is switched to a ready state after being transferred to a circuit. 2. The nonvolatile memory according to claim 1, further comprising address control means for incrementing an externally input address, and reading corresponding data from said plurality of data registers in response to the incremented address. Semiconductor memory. 3. The nonvolatile semiconductor memory device according to claim 1, wherein said latch circuit has first and second latch circuits connected in series for transferring data in a cooperative manner. 4. The non-volatile semiconductor memory device according to claim 1, further comprising a busy signal output terminal for outputting the busy signal to the outside. 5. The nonvolatile semiconductor memory according to claim 1, wherein said memory cells are NAND-connected. 6. A transfer circuit comprising a p-channel transistor and an n-channel transistor controlled by complementary signals, each of said first and second latch circuits.
The nonvolatile semiconductor memory device according to claim 1, further comprising a gate.