JPH0793499A - Memory card - Google Patents

Abstract

PURPOSE:To realize a busy signal function in a memory card where a flash memory with a data poling function is used. CONSTITUTION:The memory card 1 providing plural flash memories FMRY-1 to FMRY-19 with a status polling function which outputs information reporting the comletion of an automatic system operation such as auto-erasion, etc., from a first terminal PI/07 so as to enable status poling. In the memory ard 1, a card controller 3 is adopted, which outputs a busy signal BSYN synchronizing with the indication of the automatic system operation from an outside and indicating a busy state, waits for the state where information for reporting the completion of the applying operation is outputted from the first terminal PI/07 of the whole flash memories FMRY to which the operation is indicated and changes the busy signal BSYN into a ready state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory card having a plurality of electrically erasable and writable nonvolatile memories, such as a memory card using a flash memory (also referred to as an I / O card), and Relates to a technology effectively applied to an information processing system using the memory card.

[0002]

2. Description of the Related Art A flash memory can be electrically erased and written similarly to an EEPROM, and
Similar to the EPROM, the memory cell can be composed of one transistor, and has a function of electrically erasing all of the memory cells or a block of memory cells collectively. Therefore, the flash memory can rewrite the stored information in a state where it is mounted on the system (onboard), and can shorten the rewriting time by its batch erasing function, and further, it can reduce the chip occupation area. It also contributes to reduction.

The flash memory is, for example, a 4-megabit flash memory (HN2) manufactured by Hitachi, Ltd.
8F4001). As described in the user's manual issued by Hitachi, Ltd. this year, the end of the operation can be confirmed externally by status polling during automatic writing and automatic erasing. For example, in automatic erasing, a specific data input / output terminal is maintained at a low level until a predetermined erased state is obtained by verification, and the terminal is brought to a high level upon completion of erasing. A microprocessor or the like that has instructed the flash memory to automatically erase can recognize the end of the operation by referring to the signal.

[0004]

The present inventor has studied a memory card in which a plurality of nonvolatile memory devices such as the flash memory having the status polling function as described above are mounted on a card substrate. According to this, in order to notify the outside as a ready state or a busy state of the memory card whether or not the operation such as the automatic erasing instructed to the memory card has been completed, the following points must be considered. The inventor has found out. That is, a signal representing the ready state or the busy state of the entire memory card must be formed from the signal output by each non-volatile memory device for the status polling function. When the signal output terminal for the status polling function in the non-volatile memory device is also used as another terminal such as a data input / output terminal, the interface specifications of the memory card and the non-volatile memory device are specified. A circuit or logic for matching is required.

An object of the present invention is to provide a memory card capable of notifying the busy state and ready state of the entire memory card to the outside by integrating the status polling function of each of the plurality of nonvolatile memory devices. Another object of the present invention is to provide a memory card in which access control to a plurality of built-in nonvolatile storage devices is easy. Another object of the present invention is to provide a memory card capable of preventing malfunction of a plurality of built-in nonvolatile memory devices.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

(1) Completion of an auto erase or auto program operation which can be electrically erased and written, and which automatically performs a predetermined operation based on an instruction from the outside, such as erasing or writing, and its verify automatically. A plurality of non-volatile memory devices each having a function of outputting information for notifying the user from the first terminal to enable status polling (hereinafter also simply referred to as status polling function or data polling function); A memory card having a card controller for selectively access-controlling the plurality of non-volatile storage devices according to given information, the busy state being synchronized with an instruction of the predetermined operation from the outside to the non-volatile storage device. Outputs a busy signal to the outside, and displays all the non-volatile memory A card controller equipped with a busy signal generator that changes the busy signal to a ready state after waiting for a state in which information for notifying the completion of the predetermined operation is output from the first terminal of the device is adopted. is there. (2) When the first terminal for information output for the status polling function is also used as one of the data input / output terminals in the non-volatile memory device, the busy signal is in a busy state. That is, in order to make another non-volatile storage device read-accessible during a predetermined operation such as auto-lays, a non-volatile storage device outputs information for the status polling function in each non-volatile storage device. It is advisable to connect the first terminal of the above to a separate polling signal line for each non-volatile memory device. At this time, the other data input / output terminals of the non-volatile memory device may be connected to the data bus common to the respective non-volatile memory devices. (3) When the operation of each of the above nonvolatile storage devices is instructed by command data given thereto, in order to simplify the access control of the nonvolatile storage device by the card controller, It is advisable to adopt a format in which the state transition control generates a control mode according to the type of command data that defines the operation mode of the device. (4) A non-volatile memory device that writes command data to another non-volatile memory device while the non-volatile memory device operates according to its status polling function and operates in parallel with mutually different command data Even if the operations corresponding to the respective status polling functions are performed in parallel, in order to easily integrate the respective status polling functions, the above-mentioned card controller is specially equipped for each nonvolatile storage device. A control unit that performs state transition control may be adopted. (5) If a reset is instructed during the busy state,
To prevent malfunction of the flash memory during operation,
It is desirable to force the busy signal to the ready state. (6) In order to prevent a malfunction of the flash memory due to an undesired drop of the erase or write high voltage during the busy state, a detection circuit for detecting the undesired drop of the high voltage and notifying the card controller The card controller may force the busy signal into the ready state by being notified by the detection circuit that the high voltage is undesirably lowered when the busy signal is in the busy state. (7) Designation of the memory block to be erased when a nonvolatile memory device of a type in which the erase operation is enabled in memory block units and the designation of a plurality of memory blocks to be erased is permitted by a plurality of address inputs The end of the supply of the address, in other words, the start of erasing the plurality of memory blocks by the nonvolatile memory device is transmitted by the change of the signal such as the chip enable signal supplied to the nonvolatile memory device. In the memory card, such a chip enable signal is controlled by the card controller. At this time, in order for the card controller to surely recognize the end of supply of the specified address of the memory block to be erased, in other words, to surely recognize the erase operation start timing of a plurality of blocks with respect to the nonvolatile memory device. To this end, a register for externally receiving polling start data indicating that the input of the designated address of the memory block to be erased has been completed is adopted, and the card controller may make the determination accordingly. At this time, a busy signal is output in a busy state in response to the polling start data being written in the register. (8) When a non-volatile memory device of a type in which an erase operation is enabled in units of memory blocks and a plurality of memory blocks to be erased are allowed to be specified by inputting addresses a plurality of times is installed, erase targets are to be erased multiple times. In order to prevent a malfunction caused by giving undesired command data as a data input during input of a specified address of a memory block, the card controller is configured to store a nonvolatile memory while supplying the specified address of the memory block to be erased. It is desirable to supply data not assigned as commands to the data input / output terminals of the device.

[0009]

According to the above means, the card controller integrally controls the status polling function of each built-in non-volatile memory device, so that the status polling function of the built-in non-volatile memory device can be controlled by the memory card itself in a busy state or a ready state. It acts to replace the state and notify the outside. Such an action eliminates the need for the host device that accesses the memory card to individually perform status polling on each non-volatile storage device, and the host device receives the busy signal as an interrupt signal or the like, thereby performing such processing. The host device is released from, and the throughput of the system is improved. Further, by adopting a data polling signal line unique to each nonvolatile memory device, even if a specific nonvolatile memory device is operating according to its status polling function, other data may be paralleled to other nonvolatile memory devices. It improves the usability of the memory card, such as enabling the read operation to the nonvolatile storage device, and further improves the throughput of the system using the memory card. Setting the state transition control as the control mode for the non-volatile storage device by the card controller facilitates access control for the non-volatile storage device. Furthermore, the busy signal is set to the ready state in response to a card reset instruction in the busy state, and the busy signal is set to the ready state when the high voltage for erasing or writing undesirably drops during the busy state. Also, supplying code data that is not assigned to a command of the nonvolatile memory device as a data input of the nonvolatile memory device while inputting the designated address of the memory block to be erased means that the nonvolatile memory built in the memory card is Prevent malfunction of the device.

[0010]

1 is a block diagram of a flash memory card according to an embodiment of the present invention. A flash memory card (hereinafter also simply referred to as a memory card) 1 shown in the figure is a JEIDA memory card (type I), that is, a memory card having an interface adapted to the JEIDA memory card interface. The flash memory card 1 includes a local memory 2 and a card controller 3, both of which are connected by a local bus 4 and are configured as a whole on a card substrate. The local memory 2 is not particularly limited, but is 4 manufactured by Hitachi, Ltd.
Flash memory with a megabit storage capacity (HN2
20 8F4001) are provided. Flash memory
It is illustrated as FMRY-0 to FMRY-19 and is also referred to as device 0 to device 19. The card controller 3 is externally connected to the flash memories FMRY-0 to FMRY- via an interface conforming to JEIDA.
Control 19.

First, the mutually identical flash memories FMRY-0 (to FMRY-19) will be described.

FIG. 19 shows a flash memory FMRY-0.
The external terminal configuration of is shown. The flash memory FMRY-0 shown in the figure is an 8-bit data input / output terminal PI.
/ O0 to PI / O7, 19-bit address input terminal P
A0 to PA18, an input terminal PCEN of a low enable chip selection signal (also referred to as a chip enable signal), an input terminal POEN of a low enable output enable signal, an input terminal of a power supply voltage Vdd such as 5V, 0
It has an input terminal for a ground potential Vss such as V and an input terminal for a high voltage Vpp such as 12V. The flash memory FMRY-0 shown in FIG. 19 is shown in a packaged state, but it is also possible to adopt an unpackaged one according to the configuration of the card substrate.

FIG. 20 shows the flash memory FMRY.
A block diagram of -0 is shown.

In the figure, reference numeral 100 denotes a flash memory cell constituted by an insulated gate field effect transistor having a two-layer gate structure (hereinafter also simply referred to as a memory cell).
Is a memory array in which are arranged in a matrix. The control gates of the flash memory cells are connected to corresponding word lines (not shown), the drains of the flash memory cells are connected to corresponding data lines (not shown), and the sources of the flash memory cells are common sources (not shown) for each memory block. Connected to the wire.

The operation of writing information to the memory cell is realized, for example, by applying a high voltage to the control gate and the drain and injecting electrons from the drain side to the floating gate by avalanche injection. Due to this write operation, the threshold voltage of the flash memory cell seen from the control gate becomes higher than that of the erased memory cell in which the write operation is not performed.

On the other hand, the erase operation is realized, for example, by applying a high voltage to the source and extracting electrons from the floating gate to the source side by the tunnel phenomenon. The erase operation lowers the threshold voltage of the memory transistor viewed from its control gate. The threshold voltage of the memory cell transistor is set to a positive voltage level in both the write and erase states. That is, the threshold voltage in the written state is raised and the threshold voltage in the erased state is lowered with respect to the word line selection level applied from the word line to the control gate. By having such a relationship between both threshold voltages and the word line selection level, it is possible to configure a memory cell with one transistor without employing a selection transistor.

In the read operation, the voltage applied to the drain and the control gate is relatively low so that weak writing to the flash memory cell, that is, unwanted carrier injection to the floating gate is not performed. Limited to low values. For example, a low voltage of about 1 V is applied to the drain and a low voltage of about 5 V is applied to the control gate. By detecting the magnitude of the channel current flowing through the memory cell transistor by these applied voltages, the logical values "0" and "1" of the information stored in the memory cell can be determined.

In FIG. 20, the address input buffer (A
The IB) 101 converts an address signal supplied from the address input terminals PA0 to PA18 into an internal complementary address signal. The converted address signal is latched by the address latch circuit 102. An X address decoder and word driver (XADEC) 103 decodes the X address signal latched in the address latch circuit 102, and drives the word line based on a selection signal obtained by decoding. In the data read operation, the word driver drives the word line with a voltage such as 5V, and in the data write operation, drives the word line with a high voltage such as 12V. All the outputs of the word driver are 0 in the data erasing operation.
It is brought to a low voltage level such as V. A Y address decoder (YADEC) 104 decodes the Y address signal latched by the address latch circuit 102. 10
Reference numeral 5 is a Y selector that selects a data line according to the output selection signal of the Y address decoder 104. Reference numeral 106 denotes a sense amplifier that amplifies a read signal from the data line selected by the Y selector 105 in the data read operation. A data output latch 107 holds the output of the sense amplifier 106. 108 is a data output latch 107
Is a data output buffer for outputting the data held by the. Reference numeral 109 is a data input buffer for fetching write data or command data supplied from the outside. The write data or command data fetched from the data input buffer 109 is held in the data input latch 110. Of the write data held in the data input latch 110, the write circuit 111 supplies the write high voltage to the data line selected by the Y selector 105 with respect to the bit data corresponding to the logical value “0”. The high voltage for writing is supplied to the drain of the memory cell to which the high voltage is applied to the control gate according to the X address signal, and thereby the memory cell is written.

The command data latched by the data input latch 110 is supplied to the memory control circuit 112. The memory control circuit 112 also receives a chip enable signal and an output enable signal supplied from the terminals PCEN and POEN, and controls various internal operations such as read, erase, and write operations of the flash memory. Further, the memory control circuit 112 is also supplied with write data for write verification or the like.

The operation of the flash memory FMRY-0 is determined by command data (also simply referred to as a command). The memory control circuit 112 decodes a command latch (not shown) that latches command data supplied from the data input latch 110 and a command latched in the command latch, and generates a control signal according to various operation modes (not shown). It has a command decoder. The operation voltage required for each operation such as reading, erasing, and writing is supplied to each section according to the operation mode under the control of the memory control circuit 112.

FIG. 21 shows the types of commands set by the command data and their setting modes.

Although not particularly limited, the command data is basically fetched in two cycles of the first cycle and the second cycle. The item of mode shown in each cycle indicates whether the cycle belongs to write or read, the item of address shows the type of address supplied in the cycle, and the item of data is supplied in the cycle. Indicates command data, etc. The type of command is not particularly limited, but is as follows. (1) Read Memory The read memory is an operation mode in which data is read from the memory cell. That is, when the command data "00H" is written in the flash memory in the first cycle, the data Dout to be read in the second cycle is output. (2) Read ID The read ID is an operation mode for reading a product identification code (ID). This is because when the command data "90H" is written in the first cycle, the product identification code ID is output from the address specified by the product identification address IA in the second cycle.

(3) Chip Erase Chip erase is an operation mode for collectively erasing the entire chip. Command data “20” in the first cycle
The operation mode is designated by writing "H" and writing command data "20H" in the second cycle. (4) Block erase Block erase is an operation mode in which erasing is performed in block units. In this operation mode, the command data “60H” is written in the first cycle, the command data “60H” is written in the second cycle, and the address BA of the block to be erased is supplied, thereby (5) Erase verify Erase verify is an operation mode for verifying erase, that is, when command data "A0H" and a memory address to be verified are written in the first cycle, the second cycle At this address, the data (EVD) at that address is read. Be done.

(6) Auto Chip Erase Auto chip erase is an operation mode in which erasing and verifying of the entire chip are automatically performed. this is,
This is performed by writing the command data "30H" in the first cycle and writing the command data "30H" in the second cycle. When this operation mode is designated, the erase operation is automatically performed by the memory control circuit, and therefore erase and verify by external control are not required. When this automatic erasing is started, the status polling (also referred to as data polling) function makes it possible to externally confirm the end of the automatic erasing and verification. That is, during the erase and verify operations, for example, a low level signal is output to the data input / output terminal PI / O7,
When the erase and verify operations are completed, the output of the relevant terminal is inverted to the high level. At this time, the other data input / output terminals I / O0 to I / O6 are set to a high output impedance state. (7) Auto Block Erase Auto block erase is an operation mode in which a specified block is automatically erased and verification for the erase is performed. This is because the command data “20H” is written in the first cycle, the command data “D0H” is written in the second cycle, and the address BA of the block to be erased is supplied to erase and verify the block. Is done. When this operation mode is designated, the erase and verify operations of the block are automatically performed by the memory control circuit, so that the erase and verify operations by external control are not required. Further, similarly to the above, the status polling function via the data input / output terminal PI / O7 makes it possible to externally confirm the end of the automatic erase and verify of the block. (8) Program A program is an operation mode in which a writing operation is performed.
When the command data "40H" is written in the first cycle, the write data PD is written in the memory cell specified by the program address PA in the second cycle. (9) Program verification Program verification is an operation mode in which verification for writing is performed, and command data "C0H" and memory address PV to be verified in the first cycle.
When A is written, the data PD at the address PVA is read in the second cycle.

(10) Auto Program The auto program is an operation mode in which writing is automatically performed and verification for the writing is performed. This is the command data “10H” in the first cycle.
Is written, and the write address P is written in the second cycle.
This is done by designating A and write data PD. When this operation mode is designated, the write operation is automatically performed by the memory control circuit, and therefore the write and verify by external control are not required. When this automatic writing is started, the end of automatic writing and verify operation can be confirmed externally by the status polling function. That is, during the write and verify operations, for example, a signal of the inverted level of the corresponding bit of the write data is output to the data input / output terminal PI / O7, and when the write and verify operations are completed, the output of that terminal is the write data. It is inverted to the level of the corresponding bit. At this time, the other data input / output terminals I / O0 to I / O6 are set to the high output impedance state as described above.

(11) Reset The reset is an operation mode for resetting the inside of the flash memory, and when resetting after the first cycle of the program or auto-program, the command data is written twice in the first and second cycles. This is performed by writing "FFH", and when resetting other states, the command data "FFH" may be written only once.

As is clear from the description of the above command,
The operation of the flash memory is determined by the content of the command data written in the first cycle and, if necessary, the second cycle. Writing of command data is started by chip selection of the flash memory by a chip enable signal. In other words, the flash memory first receives the command data by instructing the chip selection even if the writing of the command data is not instructed from the outside by the write enable signal such as the write enable signal. This is the first cycle. Whether the second cycle is necessary or not is determined by the command data written in the first cycle being decoded by the memory control circuit 112. Due to such operation specifications, the flash memory adopted in this embodiment does not require a write enable signal as a write instruction signal from the outside. In the above operation mode, in each of the operation modes of auto chip erase, auto block erase and auto program (hereinafter simply referred to as auto system operation mode) that enables data polling via the data input / output terminal PI / O7, the data input / output terminal PI / The output for data polling via O is made externally observable in the state where the chip enable signal and the output enable signal supplied via the terminals PCEN and POEN of the flash memory are asserted to the low level, respectively. .

Next, the JEIDA memory interface in the memory card 1 according to this embodiment will be described with reference to FIG.

That is, the 24-bit address signal A0
To A23, and a 2-bit chip enable signal C of low enable, respectively.
E1N, CE2N, low enable write enable signal WEN, low enable output enable signal OEN, high enable reset signal RESET
P and register enable signal RE of low enable
A plurality of control terminals 31 for inputting GN, a data input / output terminal 32 for inputting / outputting 16-bit data D0 to D15, and a control terminal 33 for outputting a low enable busy signal BSYN are provided.

FIG. 22 shows an example of an external access mode to the memory card 1. The access mode is the signals CE1N and CE2N and the address bit A0.
The access is determined in units of bytes (8 bits) and the access in units of words (16 bits).

Next, the structure of the local bus 4 will be described with reference to FIG.

The above 20 flash memories FMRY-
0 to FMRY-19 are alternately assigned to even bytes (lower 8 bits) and odd bytes (upper 8 bits). Data input / output terminal P of each flash memory (device 0, device 2, ...) Assigned to even bytes
I / O0 to PI / O6 are commonly connected to the even byte common data bus MD0-6 (7 bits) for each corresponding bit. Similarly, the data input / output terminals PI / O0 to PI / O6 of each flash memory (device 1, device 3, ...) Allocated to odd-numbered bytes are odd-byte common data bus MD8-14 (7 bits) for each corresponding bit. Commonly connected to. Each flash memory FMRY-0 to FMRY
The data input / output terminal PI / O7 of -19 is a data polling data bus P for each device (flash memory).
It is individually connected to the corresponding bits of D0-19 (20 bits). This data polling data bus PD0-19
Is also used for data polling in the automatic system operation mode. Each flash memory FMRY-0 to FMR
Address input terminals PA0-PA18 of Y-19 are coupled to a 19-bit common address bus MA1-19.
The chip selection for the flash memories FMRY-0 to FMRY-19 is a 20-bit chip selection signal MCE0N.
~ It is performed separately by MCE19N. Further, the output enable signal MOEN for the flash memories FMRY-0 to FMRY-19 is
It is commonly supplied to the terminals POEN of MRY-0 to FMRY-19.

An example block diagram of the card controller 3 is shown in FIG. The card controller 3 includes a memory control signal generator 40 for generating control signals MCE0N to MCE19N, MOEN for the flash memory memories FMRY-0 to FMRY-19, and a data bus D0 on the host side.
-15 is a local bus side data bus MD0-6, MD
7-14, PD0-19, a data bus switching unit 41, a busy signal generation unit that generates a busy signal BSYN signal based on the values of the polling data bus PD0-19, and write data for determining the end of the auto program. The write data storage unit 43 stores (bits D7 and D15 corresponding to the write data to the input / output terminal I / O7 of the flash memory), and the control unit 44 that generates control signals thereof.

The memory control signal generator 40 is shown in FIG.
The chip enable signal MC according to the correspondence shown in
E0N to MCE19N are generated, and an output enable signal MOEN is further generated based on OEN.

The data bus switching unit 41 is based on the correspondence shown in FIG. 22 and is connected to the data buses D0-15 on the host side.
Data buses MD0-6 and MD8-1 on the local bus side
4, Switch connection with PD0-19. That is, the data buses D0-6 and D8-14 are connected to the local side data bus MD0.
-6, how to connect with MD8-14, and
The data buses D7 and D15 are connected to the local data bus PD0.
Switch how to connect to -19. For example, when word access to the flash memories FMRY-0 and FMRY-1 is designated, the data bus D0-6 is the local data bus MD0- when writing a command.
6, the data bus D8-14 is the local data bus M
D7 is connected to D8-14, D7 is connected to the bus PD0 coupled to the data input / output terminal PI / O0 of the flash memory FMRY-0, and D15 is the flash memory F.
It is connected to a bus PD1 coupled to a data input / output terminal PI / O0 of MRY-1. For example, when the operation designated by the command is the automatic operation mode, PD0 and PD1 are disconnected from the data buses D7 and D15 during the polling and are supplied only to the busy signal generating section 42.

The control unit 44 controls the inside of the card controller 3 by the state transition control as shown in FIG. Although the case of the auto system operation mode is typically shown in FIG. 3, the seven states are changed by the command to the flash memory, and the control operation of the card controller 3 is performed by the device described in FIG. It is adapted to the operation of the (flash memory). Similar state transition control is performed for other operation modes not shown in FIG. In FIG. 2, reference numeral 45 is a polling start register. The polling start register 45 is a register in which information indicating that the writing of the block address to be erased has been completed is externally writable in auto block erase in which a plurality of block addresses to be erased can be designated. Is.

FIG. 4 shows an example block diagram of the busy signal generator 42. The busy signal generator 42
An auto-command (command for instructing the above-mentioned auto-system operation mode) is configured by an end determination unit 50 and a busy register unit 51.

When the auto program is designated, the auto command end determination section 50 compares the value of the data input / output terminal PI / O7 (PD bus) of the flash memory with the write data of the write data storage section 43, and the FLASH
The function to determine the end of internal processing of the memory for each flash memory, and when auto chip erase or auto block erase is specified, the value of the data input / output terminal PI / O7 (PD bus) of the flash memory is "0". It has a function of determining the end of the internal processing of the flash memory for each flash memory by detecting the change from "1" to "1". That is, the auto command end determination unit 5
0 is a comparison circuit COM that compares each bit of the data polling data bus PD0-19 with the data bit supplied from the write data storage unit 43 in correspondence with each other.
It has P0-COMP19. Write data storage unit 43
Stores a write data bit in the auto program operation mode. In other auto operation modes, high level data such as logic "1" is stored. The comparison circuits COMP0 to COMP19 correspond to the flash memories FMRY-0 to FMRY-19.
The comparison operation for them is performed by the address signals A0 and A20.
A control signal 52 indicates a flash memory corresponding to a chip to be selected by A23. The matching state of the comparison results in all the comparison circuits instructed to perform the comparison operation is notified to the control unit 44 by the end signal 53. The output of the comparison circuit instructed to perform the comparison operation maintains the low level until the two inputs match. The output of the comparison circuit in which the comparison operation is not selected is put into a high output impedance state, although not particularly limited. The outputs of the comparison circuits COMP0 to COMP19 are supplied to the busy register section 51.

The busy register section 51 is a register for displaying the internal processing state of the flash memories FMRY-0 to FMRY-19 by 1 bit for each flash memory. When an auto command is written to the flash memory to be accessed, the bit corresponding to the flash memory is changed from the logical value "1" to the logical value "0", and the busy state is displayed. This is performed by the control signal from the control unit 44. The value of the busy register unit 51 can be read from the host side and is output to the buses D0 to D7 by reading the register address assigned to the busy register unit 51. The value of each bit of the busy register unit 51 is converted into a busy signal BSYN by a logical OR circuit of negative logic and is output to the host side.

That is, the busy register section 51 is
2 bits corresponding to 20 flash memories bit by bit
It has a structure of 0 bits. Each bit of the busy register unit 51 can be preset by a signal 54 from the control unit 44. The input of each bit of the register unit 51 is coupled to the output of the comparison circuits COMP0 to COMP19, the output of each bit of the register unit 51 is inverted and supplied to the NOR gate circuit 55, and the output of the NOR gate circuit 55 is output. The output is the busy signal BSYN. The control signal 54 is the address signals A0, A20 ...
The logical value "0" is preset to the bit corresponding to the flash memory to be chip-selected by A23, and the logical value "1" is preset to the other bits. Therefore, when the busy register unit 51 is preset, the busy signal BSYN is set to the low level. As a result, the memory card notifies the outside that it is busy. This state is maintained until the flash memory accessed at that time ends the auto-system command operation and the outputs of the predetermined comparison circuits are all set to the logical value "1". When the internal processing of the flash memory ends, the value of the busy signal BSY changes from the busy logical value “0” to the ready logical value “1” based on the end signal from the auto command end determination unit 50. To be done. The contents of the busy register unit 51 can be output to the data buses D0 to D7 by the output control signal 56 from the control unit 44, and the contents can be externally monitored.

The overall operation of the memory card according to this embodiment will be briefly described with reference to FIGS. 1 and 2. For example, when a command is written to the flash memories FMRY-0 and FMRY-1 by word access from the host side, the even byte side commands D0 to D7 are transmitted to the data bus switching unit 41 at MD0-6 (even byte side common data bus). ) And PD0 (flash memory FMRY-0)
Polling data bus) for D8 to D15
The odd-numbered-byte-side command of
7-14 (common data bus on odd byte side) and PD1
(Polling data bus for the flash memory FMRY-1), and the flash memory FM
RY-0 (even bytes) and flash memory FMRY-
The command is written to 1 (odd byte).

When this command is automatic write (auto program), automatic erase erase, or automatic erase block erase, the memory control signal generator 40 sends the chip enable signal to the terminals PCEN of the respective flash memories. MCE0N to MCE19N are output separately and the terminals POE of each flash memory are output.
An output enable signal MOEN is commonly generated toward N, and an operation corresponding to the data polling function is started. That is, the busy signal BSYN output from the busy signal generator 42 is set to low level to notify the host side of the busy state of the memory card. These controls are based on the values of the command (first command) externally written in the first cycle and the command (second command) externally written in the second cycle described in FIG. Done. The control method is a method in which the states shown in the state transition diagram of FIG. 3 are transited according to the command of the flash memory as described above, and the control operation of the card controller 3 is determined so as to follow or correspond to the operation of the flash memory. To be done.

FIG. 5 shows an example of state transition control when an auto chip erase is instructed to the memory card. In particular, the figure shows an example in which a command for instructing the automatic chip erase is written in the flash memories FMRY-0 and FMRY-1 by word access.

First, as the first command, "30"
When "h" is written, the state number in the state transition diagram of Fig. 3 is changed from "000" in the wait state to "001" in the auto chip erase setup state. Next, "30h" is written as the second command. Then, the state number transits from "001" to the auto chip erase polling state "010", whereby the busy signal generator 42 externally asserts the busy signal BSYN to an enable level such as a low level. Furthermore, the flash memory FMRY- to be accessed
For 0 and FMRY-1, the output enable signal MOEN and the chip enable signals MCE0N and MCE1N are asserted to the low level in accordance with the specifications for starting the operation according to the status polling function. As a result, in the flash memory, the output of the data input / output terminal PI / O7 is at low level, and the other data input / output terminals PI / O0 to PI / O6.
Is placed in a high output impedance state. During this period, the flash memories FMRY-0 and FMRY-1 are erased and verified on the entire chip in accordance with the auto chip erase command. Flash memory FMRY-0,
After erasing and verifying the entire FMRY-1 chip, both flash memories FMRY-0, FM are erased.
The output of the data input / output terminal PI / O7 in RY-1 is inverted to the high level. This state is transmitted to the auto command end determination unit 50 via the data polling data buses PD0 and PD1, and the auto command end determination unit 50 notifies the control unit 44 of the end of the auto chip erase by the end signal 53. The control unit 44 returns the internal control state to the command waiting state by the end signal. As a result, the memory control signal generation unit 40 causes the control signals MOEN, MCE to the flash memory.
0N and MCE19N are negated. On the other hand, the busy register unit 51 receives the determination result of the auto command end determination unit 50, and thereby the busy signal BSYN is negated to the high level. Externally, the end of the auto chip erase can be determined based on this. For example, an external host device (not shown) may receive the busy signal B
It is possible to receive this as an interrupt request and perform processing in synchronization with the change of SYN from low level to high level.

FIG. 6 shows a flash memory FMRY-0,
An example operation timing chart when an auto program command is written to FMRY-1 by word access is shown.

A command "10" is issued from the outside in the first cycle.
When "H" is written (1st-W), the program address (PA) is supplied in the second cycle and the program data (PD) is written (2nd-W), an instruction for the second cycle from the outside is given. End, that is, in synchronization with the rise of the write enable signal WEN (time T1), the busy signal BSYN signal is set to the low level and the flash memory of the memory card 1 enters the internal processing state. The busy register unit 51 is in a busy state for notifying the device etc. At this time, since the busy register unit 51 holds information indicating whether or not each flash memory is in the busy state, the host device (not shown) has a busy register unit 51. You can check which flash memory is busy by reading the contents of. Light from the rising edge of the enable signal WEN for example, after lapse of a minimum 120 ns (the value defined by the specification of the flash memory), a flash memory that is the write target chip enable signal MCE0
N, MCE01N and output enable signal MO
EN is asserted and the flash memory FMRY-0,
The operation corresponding to the data polling function of FMRY-1 is started. The chip enable signals MCE0N, MC
The polling data from the flash memory is not fixed until, for example, 150 ns elapses after the fall of E1N.
Therefore, the auto command end determination unit 50
After the time of 0 ns has elapsed, the comparison between the input (polling data) from the polling data buses PD0 and PD1 and the stored write data in the write data storage unit 43 is started. When the stored write data in the write data storage unit 43 and the polling data (data on PD0 and PD1) match, the auto program has been completed, so the auto command end determination unit 50 detects the state. , Flash memory to be accessed (FM
2 bits of the busy register unit 51 corresponding to RY-0, FMRY-1) are changed from the logical value "0" to the logical value "1". As a result, the busy signal BSYN is inverted from low level to high level. As a result, the host system (not shown) can recognize that the processing of the auto program in the memory card 1 is completed. The stored write data referred to here is the data of D7 and D15 latched at the edge indicated by T1.

FIG. 7 shows a flash memory FMRY-0,
An example operation timing chart when an auto chip erase command is written to FMRY-1 by word access is shown. The operation differs from the auto program shown in FIG. 6 only in the method of determining polling data. That is, in the auto chip erase, the polling data output from the data input / output terminal PI / O7 of the flash memory indicates that the flash memory is performing internal processing when it has a logical value "0".
If it has a logical value of "1", it means that the internal processing has been completed. Therefore, in the operation mode, the auto command end determination unit 50 detects this, detects that it has become the logical value "1", and detects the busy register unit 51.
The corresponding bit of is inverted to the logical value "1". Since the other timings are the same as those in FIG. 6, detailed description thereof will be omitted.

FIG. 8 shows a flash memory FMRY-0,
An example operation timing chart when the auto block erase command is written to FMRY-1 by word access is shown.

The difference from the above-mentioned two auto-related commands is that, after the command write in the second cycle, a plurality of block addresses (BA) can be input from the host device (not shown), so the timing of starting data polling. Is not uniquely determined within the card controller 3. Therefore, the control unit 44 has
When the polling start register 45 is provided and the block address input cycle (plurality) is completed, the host device (not shown) writes the data of the logical value “1” to the polling start register 45, and thereby the data polling is started. To be done. Specifically, the chip enable signals MCE0N and MCE1N are asserted in synchronization with the end of the write operation for the polling start register 45 (the rising edge of the write enable signal WEN at time T2), and the data polling function of the flash memory is responded. The operation is started and the busy signal BSYN is asserted to the low level. Whether or not the internal processing of the flash memory is completed is determined by the chip enable signals MCE0N, M as in the above.
It is started 150 ns after CE1N is asserted, the determination method is the same as that of auto chip erase, and processing is being performed by the logical value "0" of the polling data supplied from the data input / output terminal I / O7 of the flash memory. It is determined that there is, and it is determined that the end is the logical value “1”.

FIG. 9 is a timing chart for explaining the prevention of malfunction when a block address is input in the automatic block erase. FIG. 9 shows a state in which the block address is supplied over the second cycle and thereafter. When the block address is supplied to the memory card 1 after the second cycle, the block address is also supplied to the access target flash memory. At this time, data input is don't care in the specification of the flash memory. However, if a code corresponding to a reset command is supplied to the flash memory from an unrelated data bus, the flash memory may be undesirably reset. Therefore, in order to prevent such a malfunction when a block address is input, as shown in the figure, the local data bus (even byte side: PD0, M
D0-6, odd byte side: PD1, MD8-14),
Forcibly code data “AA” by the card controller 3
By inputting "H", it is prevented from being undesirably reset. Here, the code data "AAH" is code data which is not adopted as the command data described in FIG. Code data that means non-operation.

FIG. 10 shows an operation concept showing that another flash memory is made readable during data polling. In the figure, the flash memory FMR is shown.
A case is shown in which the flash memories FMY-2 and FMRY-3 are reread while Y-0 and FMRY-1 are polling data. That is, the flash memory FM
The polling data output from RY-0 and FMRY-1 is sent to the busy signal generation unit 42 via PD0 and PD1 unique to the flash memory. At this time, when the flash memories FMRY-2 and FMRY-3 are read, even-numbered bytes of data are transferred via PD2 and MD0-6.
Odd byte data is transferred to D3 via PD3 and MD 7-14
It is output to 0 to D15. As described above, the read operation from another flash memory can be performed during data polling because the data polling data bus PD0-
19 is each flash memory FMRY-0 to FMRY-1
This is because each of the nine data input / output terminals PI / O7 is provided separately.

FIG. 11 shows a timing chart of the reset operation of the memory card 1 during the operation corresponding to the data polling function of the flash memory. According to the figure, during operation of the flash memories FMRY-0 and FMRY-1 according to the data polling function (during execution of the auto command), the card reset signal RESETP is asserted from the host side (not shown) to the memory card 1. Then, the busy register unit 51 is initialized. As a result, the busy signal BSYN is set to the high level, the ready state (READY) is notified to the outside, and the signals MOEN, MCE0N, and MCE1N for operating the flash memory according to the polling function are negated, The operation according to the data polling state of the flash memory is forcibly terminated. According to this operation timing, when the card reset signal RESETP is asserted, the card controller 3 is initialized, and the polling state of the flash memory is also ended accordingly. However, if the flash memory does not have a reset terminal,
Even after the data polling of the flash memory is completed, the processing based on the auto system command inside the flash memory is continued, and the internal state of the flash memory is not reflected in the busy signal BSYN signal.

FIG. 12 shows an operation timing chart when the busy signal when the card is reset reflects the internal state of the flash memory.
That is, when the card reset is instructed during the data polling, the control unit 44 does not reset the busy register unit 51 and continues the data polling by the busy signal BSYN. That is, the reset signal R
Even if the card reset is instructed by ESETP, the assertion state of the busy signal BSYN to the low level is maintained, and the control signals MOEN and MC to the flash memory are maintained.
Leave E0N and MCE1N asserted. As a result, the operation according to the data polling function is not ended in synchronization with the card reset, and when the internal processing of the flash memory by the auto command at that time is ended, the busy signal BSYN is negated to the high level and the data polling is performed. Is ended.

FIG. 13 shows an embodiment in which an auto system command can be executed in another flash memory during the operation corresponding to the data polling function. That is, the device 0 is set for each of the flash memories FMRY-0 to FMRY-19.
The control unit 65-0 to the device 19 are shown in FIG.
The control unit 64 added to the control unit 44 as shown in FIG. 4 is adopted, and the card controller 3-1 is configured to control the memory control signal generation unit 60 independently for each flash memory. The other configurations are the same as those in FIG. 2, and the circuit blocks having the same functions as those shown in FIG. 2 are designated by the same reference numerals and detailed description thereof will be omitted. The device 0 control unit 65-0 to device 19 control unit 65-19 can perform the state transition control described in FIG. 3 for each flash memory. Therefore, the control unit 64 controls the memory control signal generation unit 6
The output enable signal MOEN is controlled to 0 according to the state of each flash memory together with the control signals MCE0N to MCE19N.

FIG. 14 shows a timing chart when the auto chip erase command is separately executed for a plurality of flash memories in FIG. According to the figure, while the flash memories FMRY-0 and FMRY-1 are performing the automatic chip erase in the word access mode, the flash memory FMRY-
2, when an auto chip erase command is written to FMRY-3, the flash memories FMRY-0, FM
RY-1 and flash memory FMRY-2, FMRY-
An operation in which state transition control is performed on each of 3 and 3 is shown.
That is, the flash memories FMRY-0, FMRY-
When the auto chip erase command for 1 is written, the device 0 control unit 65-0 and the device 1 control unit 65-1 determine this. And the busy signal BSY
N is asserted to the low level and the control signal MO
EN, MCE0N, and MCE1N start the operation corresponding to the data polling function for the flash memories FMRY-0 and FMRY-1. At this time, when the auto chip erase command for the flash memories FMRY-2 and FMRY-3 is externally written, the command is recognized by the device 2 control unit 65-2 and the device 3 control unit 65-3. Based on this, the memory control signal generation unit 60 causes the flash memories FMRY-0 to FM.
Output enable signal MOE common to RY-19
N is negated, in other words, the flash memories FMRY-0, F currently operating according to the data polling function.
The operation in MRY-1 is interrupted, and the auto chip erase command is written in the flash memories FMRY-2 and FMRY-3. After that, output enable signal MOEN and chip enable signal MC
E0N to MCE3N are asserted, the operation corresponding to the data polling function by the flash memories FMRY-0 and FMRY-1 is restarted, and the operation corresponding to the data polling function by the flash memories FMRY-2 and FMRY-3 is started. Flash memory FMR
When the end of the auto chip erase by Y-0 and FMRY-1 is determined through the data input / output terminal PI / O7, the device 0 control unit 65-0 and the device 1 control unit 65-1 enter the command waiting state. It is transitioned. Following this, the end of the auto chip erase by the flash memories FMRY-2 and FMRY-3 is the data input / output terminal P.
When it is determined via the I / O 7, the device 0 control unit 65
-2 and the device 1 control unit 65-3 are transited to the command waiting state. At the same time, the busy signal BSYN is negated to a high level.

FIG. 15 is a timing chart showing the state of the local bus 4 during the operation shown in FIG. 14 in more detail. That is, the flash memory FMRY-0,
FMRY-1 and flash memory FMRY-2, FM
The operations corresponding to the data polling function by RY-3 are performed in parallel, and the polling data output from the respective data input / output terminals PI / O7 are independently polled data buses PD0, PD1 and polling data. It is sent to the auto command end determination unit of the card controller 3-1 via the buses PD2 and PD3. In response to this, the end determination of the data polling state is independently performed, and the control signals MCE0, MCE1N, MCE2N, MCE3N are independently controlled. The falling timing of the busy signal BSYN is the earliest second command write cycle (2nd-
W) is synchronized with the end timing, and its rising timing is synchronized with the timing when the internal processing of the flash memory is terminated latest. In addition, at the time of command writing during operation according to the data polling function, in order to avoid collision of polling data and command on the data polling bus PD, or to enable command writing to the flash memory, first. The operation corresponding to the started data polling function is temporarily suspended.

FIG. 16 shows a block diagram of a flash memory card according to another embodiment. The flash memory card 1-1 shown in the figure includes a card controller 3-2 having the functions of the card controller 3 or 3-1 described in the above embodiment, and a plurality of flash memories FMR.
As in the above embodiment, the local memory 2 including Y-0 to FMRY-19 and the local bus 4 are provided.
In this embodiment, when the high voltage Vpp required for erasing or writing to the flash memory is cut off or abnormally lowered during the operation corresponding to the data polling function, the high voltage Vpp drops in order to prevent malfunction. A detection circuit 70 is provided to notify the card controller 3-2 of the drop in the high voltage Vpp. When the high voltage Vpp is lower than the specified voltage required for the flash memory, the state is detected by the high voltage Vpp drop detection circuit 70 and is notified to the card controller 3-2 by the control signal 71. The card controller 3-2 receives this,
As shown in FIG. 17, the control signals MOEN, MCE for outputting the polling data to the flash memory.
0N and MCE1N are negated to terminate the operation corresponding to the data polling function. At this time, the flash memory also ends the internal processing in an abnormal state due to the abnormal voltage drop of the high voltage Vpp. An abnormal voltage drop of the high voltage Vpp during data polling, that is, an unacceptable drop of the high voltage Vpp during internal processing of the flash memory can be regarded as an abnormal operation of the flash memory card, and a host device (not shown) detects this state. To enable the card controller 3-2, the busy signal BSYN
The busy state is maintained until, for example, a card reset is instructed. The host device (not shown) detects that the flash memory card has been busy for more than a certain period of time and detects that the flash memory card has timed out, so that the flash memory card 1-1 has an abnormality requiring a card reset. Can be detected.

FIG. 18 shows a system configuration example to which the flash memory card 1 (1-1) described above is applied. The flash memory card 1 (1-1) has a central processing unit (CPU) 80, a random access memory (RAM) 81, and a read-only memory (ROM) 82 that are commonly connected to a bus 83. It is connected via an interface circuit (I / F) 84. In this configuration, the flash memory card 1 (1-1) is accessed by the CPU 80 as a host device.

According to the above embodiment, there are the following effects. (1) Flash memory FM built in the memory card
Since the card controller 3 (3-1) integrally controls the individual status polling functions of RY-0 to FMRY-19, the status polling function of the flash memory is replaced with the busy state or the ready state of the memory card itself and notified to the outside. can do. Therefore,
The host device that accesses the memory card 1 (1-1) does not need to individually perform status polling processing on each flash memory, and the busy signal BSYN is received by the host device as an interrupt signal, so that such processing is performed. The host device is released from, and the throughput of the system can be improved. (2) By adopting the data polling signal lines PD0 to PD19 unique to each flash memory, even if the specific flash memory is operating according to its status polling function, other The read operation for the flash memory can be enabled, and the usability of the memory card and the throughput of the system using the memory card are improved. (3) Since the card controllers 3 and 3-1 have a format for generating the control mode according to the type of command data that defines the operation mode of the flash memory by the state transition control, the nonvolatile storage device according to the command data. Access control can be simplified. That is, it is possible to easily realize the synchronization control or the synchronization operation with the built-in flash memory. (4) Card controller 3 that employs a control unit that performs the above state transition control for each flash memory
By using -1, command data is written to another flash memory while the flash memory is operating in accordance with its status polling function, and each flash memory is operated in parallel with different command data. Even when the operations according to the status polling functions are performed in parallel, the status polling functions can be easily integrated. (5) When the memory card is performing an operation according to its data polling function, that is, when a card reset instruction is given while the busy signal indicates the busy state, the busy signal is forced to the ready state. By doing so, it is possible to prevent the malfunction of the flash memory during the operation in the busy state. (6) A detection circuit 70 is provided for detecting an undesired drop in high voltage for writing or erasing and notifying the card controllers 3 and 3-1 of the card, and when the busy signal BSYN is in a busy state, the card When the controller receives the notification of the undesired drop of the high voltage by the detection circuit, the busy signal is forced to the ready state, and the flash due to the undesired drop of the high voltage for erasing or writing in the middle of the busy state. It is possible to prevent malfunction of the memory. (7) Designation of the memory block to be erased when a flash memory capable of batch erasing operation in units of one or more memory blocks is mounted in a format in which a plurality of memory blocks to be erased can be designated by inputting addresses a plurality of times. By adopting a register that receives polling start data indicating that address input has been completed from the outside, this makes it possible for the card controller to make sure that the supply of the specified address of the memory block to be erased has been completed. To be recognizable,
It is possible to maximize the erasing function of the flash memory capable of erasing multiple blocks at once. This can shorten the overall erase time in memory block units as compared with a memory card that can erase only a single memory block. Also in this respect, the throughput of the system can be improved. (8) Further, by supplying the data “AAH” which is not assigned as a command to the data input / output terminal of the flash memory during the supply of the designated address of the erase target memory block, the erase target memory block is erased over a plurality of times. It is possible to prevent malfunction caused by giving undesired command data as data input during input of the designated address.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the scope of the invention. Yes.

For example, the nonvolatile memory device is not limited to the flash memory and may be an EEPROM. The number is not limited to 20 and can be changed as appropriate. Further, the card interface is not limited to the JEIDA standard of the above embodiment. Further, the types of operation modes of the flash memory and the contents of operations in each operation mode are not limited to those in the above embodiment, and various modifications can be made.

[0062]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) The status polling function of each built-in non-volatile memory device is integratedly controlled by the card controller so that the status polling function of the built-in non-volatile memory device is replaced with the busy or ready status of the memory card itself. You can notify the outside. This eliminates the need for the host device accessing the memory card to individually perform status polling on each non-volatile storage device, and the host device receives the busy signal as an interrupt signal to prevent the host device from performing such a process. The device is opened and the throughput of the system can be improved. (2) By adopting a data polling signal line unique to each non-volatile memory device, even if a particular non-volatile memory device is operating according to its status polling function, other It is possible to improve the usability of the memory card and further improve the throughput of the system using the memory card by enabling the read operation to the nonvolatile storage device. (3) By setting the state transition control as the control mode for the non-volatile storage device by the card controller, access control to the non-volatile storage device can be facilitated. For example, control in synchronization with the operation of the nonvolatile storage device becomes easy. (4) The busy signal is set to the ready state in response to a card reset instruction in the busy state, and the busy signal is set to the ready state when the erase or write high voltage undesirably drops during the busy state. In addition, supplying code data that is not assigned to a command of the nonvolatile memory device as a data input of the nonvolatile memory device while inputting the specified address of the memory block to be erased This can contribute to prevention of malfunction of the storage device.

[Brief description of drawings]

FIG. 1 is a block diagram of a flash memory card according to an embodiment of the present invention.

FIG. 2 is a block diagram of an example of the card controller shown in FIG.

FIG. 3 is a state transition diagram of control by state transition control of a control unit.

4 is a block diagram of an example of a busy signal generation unit shown in FIG.

FIG. 5 is a timing chart showing an example of state transition control when auto chip erase is instructed to the memory card of the present embodiment.

FIG. 6 is an example operation timing chart when an auto program command is written to the flash memory by word access.

FIG. 7 is an operation timing chart of an example when an auto chip erase command is written to the flash memory by word access.

FIG. 8 is an operation timing chart of an example when an auto block erase command is written to the flash memory by word access.

FIG. 9 is a timing chart for explaining malfunction prevention at the time of inputting a block address in auto block erase.

FIG. 10 is an explanatory diagram showing an operation concept showing that another flash memory is made readable during data polling.

FIG. 11 is a timing chart of an example of a memory card reset operation during data polling.

FIG. 12 is an operation timing chart when the busy signal when the card is reset reflects the internal state of the flash memory.

FIG. 13 is a block diagram of a card controller that enables execution of an auto command to another flash memory during data polling.

FIG. 14 is a timing chart showing an example of a case where an auto chip erase command is separately executed for a plurality of flash memories in FIG.

FIG. 15 is a timing chart showing the state of the local bus during the operation shown in FIG. 14 in more detail.

FIG. 16 is a block diagram of a flash memory card having a function of detecting a high voltage drop.

17 is an operation timing chart of the flash memory card of FIG.

FIG. 18 is a block diagram of an example system configuration to which a flash memory card according to an embodiment of the present invention is applied.

FIG. 19 is an explanatory diagram showing an external terminal configuration of a flash memory.

FIG. 20 is a block diagram of an example of a flash memory.

FIG. 21 is an explanatory diagram showing types of commands set by command data for the flash memory and setting modes thereof.

FIG. 22 is an explanatory diagram showing an example of an external access mode to the memory card.

[Explanation of symbols]

1 Flash memory card 2 Local memory 3 Card controller 4 Local bus FMRY-0 to FMRY-19 Flash memory PI / O0 to PI / O7 Data input / output terminals MD0-6 Even byte common data bus MD8-14 Odd byte common data bus PD0 -19 Data bus for data polling 40 Memory control signal generation unit 41 Data bus switching unit 42 Busy signal generation unit BSYN busy signal 43 Write data storage unit 44 Control unit 45 Polling start register RESETP card reset signal 50 Auto command end determination unit 51 Busy Register unit 3-1 Card controller 60 Memory control signal generation unit 64 Control unit 65-0 to 65-19 Device 0 control unit to device 1
9 Control unit 1-1 Flash memory card 3-2 Card controller 70 High voltage Vpp drop detection circuit Vpp high voltage

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kyoo Okubo 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hiritsu Cho-LS Engineering Co., Ltd. (72) Inventor Takashi Kikuchi Tokyo 5-20-1 Kamimizuhoncho, Kodaira-shi Hitate Super L.S.I Engineering Co., Ltd. (72) Inventor Takeshi 5-20-1 Kamimizuhoncho, Kodaira-city, Tokyo・ Inside I Engineering Co., Ltd. (72) Inventor Shigeru Kadowaki 5-201-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Hiritsu Cho-LS Engineering Co., Ltd. (72) Inventor Masamichi Kishi Kodaira, Tokyo 5-20-1 Joumizuhoncho, Ichi, Japan, within Hitate Cho-LS Engineering Co., Ltd. (72) Inventor Toshio Kanno 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Company Hitachi, Ltd. Semiconductor Division (72) Inventor Hironori Iwasaki 15 Asahidai, Moroyama-cho, Iruma-gun, Saitama Higashi Eastern Semiconductor Co., Ltd. (72) Inventor Kubota Yasuro 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hirate Super In-SLI Engineering Co., Ltd. (72) Inventor Hiroshi Fukuda 5-201-1 Mizumizuhoncho, Kodaira-shi, Tokyo Hirate LSI Engineering Co., Ltd.

Claims (8)

[Claims] 1. A first card interface terminal, which is electrically erasable and writable and which outputs information for notifying the completion of a predetermined operation based on an instruction from the card interface terminal to the outside. A memory card having a plurality of non-volatile memory devices having terminals, and a card controller for selectively access-controlling the plurality of non-volatile memory devices according to information provided via the card interface terminals, The card controller outputs a busy signal indicating a busy state from the predetermined card interface terminal in synchronization with the instruction of the predetermined operation to the non-volatile storage device, and all the non-volatile storage devices instructed to perform the predetermined operation. The state in which the information for notifying the completion of the predetermined operation is output from the first terminal of A memory card comprising a busy signal generation unit for changing the busy signal to a ready state. 2. A plurality of card interface terminals and information of a data input / output terminal which is electrically erasable and writable and which is used to notify the completion of a predetermined operation based on an instruction from the card interface terminal to the outside. A plurality of non-volatile memory devices that output from a first terminal which is one of the data input / output terminals, and a plurality of polling signal lines that are individually coupled to the first terminals for each non-volatile memory device. And a local bus including other data input / output terminals of the non-volatile memory device and a data bus common to the respective non-volatile memory devices; and a local bus coupled to the local bus and given through the card interface terminal. A memory card having a card controller for selectively accessing and controlling the plurality of non-volatile storage devices according to information, The card controller outputs a busy signal indicating a busy state from the predetermined card interface terminal in synchronization with the instruction of the predetermined operation to the non-volatile storage device, and the non-volatile storage device of all the non-volatile storage devices in which the predetermined operation is instructed. A busy signal generation unit that changes the busy signal to a ready state after waiting for the information for notifying the completion of the predetermined operation from the first terminal to be transmitted through the polling signal line, and from the outside. And a data bus switching unit for disconnecting the polling signal line corresponding to the nonvolatile memory device to be accessed from the card interface terminal for data input / output according to the change of the busy signal to the busy state. ,
A memory card characterized by comprising: 3. The operation of each of the non-volatile storage devices is instructed by command data given thereto, and the card controller has a control mode according to a type of command data given from the outside. The memory card according to claim 1, wherein the memory card is generated by state transition control. 4. The memory card according to claim 3, wherein the card controller includes a control unit that performs state transition control for each nonvolatile storage device. 5. The card controller, when the busy signal generator is outputting a busy signal in a busy state,
3. The memory card according to claim 1, wherein the busy signal generation unit is controlled so as to force the busy signal into a ready state in response to a reset instruction from the card interface terminal. 6. A detection circuit for detecting an undesired decrease in high voltage for erasing or writing to a non-volatile memory device and notifying the card controller of the non-volatile memory device, wherein the card controller has a busy signal as a busy signal. 3. The memory card according to claim 1, wherein the busy signal is forced into a ready state by receiving a notification of an undesired drop of the high voltage by the detection circuit when the memory card is in the state. . 7. The non-volatile memory device is instructed to operate by command data supplied thereto, and includes a batch erase operation in memory block units as instructable operations. A plurality of batch erase target memory blocks can be specified by inputting the address once, and the card controller supplies an address for designating the erase target memory block to the nonvolatile memory device to be accessed. 3. The memory card according to claim 1, wherein the data input / output terminal of the non-volatile memory device supplies data that is not assigned as a command. 8. The non-volatile memory device is instructed to operate by command data provided thereto, and includes a batch erase operation in memory block units as an instructable operation. It is permissible to specify multiple memory blocks to be erased all at once by inputting addresses, and the card controller sends polling start data indicating that the address input to specify the memory blocks to be erased has been completed. 3. The memory card according to claim 1, further comprising a register which is writable from the outside, wherein the polling start data is written in the register to output a busy signal in a busy state. .