TW536802B - Structure and fabrication method of electrostatic discharge protection circuit - Google Patents

Structure and fabrication method of electrostatic discharge protection circuit Download PDF

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Publication number
TW536802B
TW536802B TW091108181A TW91108181A TW536802B TW 536802 B TW536802 B TW 536802B TW 091108181 A TW091108181 A TW 091108181A TW 91108181 A TW91108181 A TW 91108181A TW 536802 B TW536802 B TW 536802B
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Taiwan
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layer
electrostatic discharge
protection circuit
discharge protection
area
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TW091108181A
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English (en)
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Shiao-Shien Chen
Tsun-Lai Hsu
Tien-Hao Tang
Hua-Chou Tseng
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United Microelectronics Corp
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Priority to TW091108181A priority Critical patent/TW536802B/zh
Priority to US10/134,835 priority patent/US20030197225A1/en
Priority to US10/259,947 priority patent/US6855611B2/en
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Publication of TW536802B publication Critical patent/TW536802B/zh
Priority to US10/951,373 priority patent/US7253480B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

536802 五、發明說明（1) .本發明是有關於一種靜電放電（Electrostatic
Discharge， ESD)保護電路的結構與製造方法，且特別是 有，於一種在靜電放電保護電路中形成與埋入層， 以提ί、個低電阻路徑的靜電放電保護電路的結構與製造 方法。 σ 、靜電放電為自非導電表面之靜電移動的現象，其會造 ，，體電路（1C)中之半導體與其它電路組成之損害。例如 在地毯上行走&的人體，於相對濕度（RH)較高的情況下可檢 測2力π有幾百至幾千伏的靜態電壓，而在相對濕度較低 ，h况下可檢測出約帶有一萬伏以上的靜態電壓。而在封 衣積體電路的機器或測試積體電路的儀器，亦可能產生約 ,:至幾千伏的靜態電壓。當上述的帶 、勺 或儀m接觸到晶片時，將會向晶片放電，此靜電放= 恥間=率有可能造成晶片中的積體電路損壞或失效。 ， 為了避免靜電放電損傷晶片中的積體電路， 種防制靜電放電的方法便因應而生。最常見的習知作法是 利用硬體防制靜電放電，也就是在内部電路（internai Circuit)與每一焊墊（pad)間，均設計一晶片嵌入式 (On-Chip)的靜電放電保護電路以保護其内部電路。 一立第1圖所繪示為習知關〇3型靜電放電保護電路的結構 示意圖。 清參照第1圖，在P型基底1〇〇中設置有P井區1〇2，並 且在P井區102内設置有NM0S電晶體104與^基座連接區 114。
536802
上述的NM0S電晶體丨〇4係由閘極1〇6、源極丨〇8、汲極 構成，亚且在P井區1〇2内，P+基座連接區域114與 關㈧^晶體1〇4係由淺溝渠隔離層ιΐ2區隔開來。 f且，在P+基座連接區域11 4外側的基底1 〇 〇中設置有 18。就關⑽電晶體1 〇4而言，保護環1 18係為與P井 二 為不同摻雜形態的N+摻雜區，並且保護環US以淺溝 ^來。層1 1 6與NM0S電晶體1 〇4的p+基座連接區域〗丨4區隔 月i…、第2圖，隨著施加於沒極11 0的電廢， _合的電阻隨之下降，在電壓超過vtl後，基底1〇〇上的電& "卩牛至足夠打開源極1 〇 8侧的P N接面，此時將會使得 寄生，載子電晶體啟動而發生急回（Snapback)電壓，此急 回電壓將快速的下降至電壓VSb的值，並同時導通靜電放“ 電電流。 “ μ而，此靜電放電電流的流動路徑，通常係沿著閘介 電2的表面流動，當此電流相當大時，由於電流所產生的 熱里通#係集中於流動路徑的附近，亦即是集中於閘介電 層表面附近，此過大的熱量往往會造成閘介電層的燒炼， 使得靜電放電保護電路元件故障。 因此’本發明的目的在提出一種靜電放電保護電路的 結構與製造方法，能夠提高靜電放電保護電路的保護效 能。 本發明的另一目的在提出一種靜電放電保護電路的結 構與製造方法，能夠提高靜電放電保護電路的散熱能力:
cSSSSiwl pld 536802 電放電保護 藉由第二隔 摻雜型態與 靜電放電保 ’再於基底 入層係位於 下沈層，其 形成閘極， 中沒極電性 區域。 明係在靜電 接汲極與埋 時，由於電 在基底中流 附近，並可 靜電放電保護電路的結構，此結構包 晶體、基座連接區域、第一隔離層、 中井區係設置於基底中，電晶體係設 極、汲極與源極所組成。基座連接區 且由第一隔離層將基座連接區域與源 埋入層係設置於電晶體下方之井區盘 層設置於井區内，並且下沈層電性連 中下沈層、埋入層與井區具有相反的 五、發明說明（3) 本發明提供一種 括：基底、井區、電 下沈層、埋入層。其 置於井區内，且由間 域係設置於井區内， 極、沒極區隔開來。 基底的交界面。下沈 接埋入層與汲極。其 摻雜形態。 尚且，在上述靜 保護環，此保護環係 來，並且此保護環的 本發明提出一種 k方法係提供一基底 底中形成井區，且埋 面’再於井區中形成 層。然後，於井區内 形成源極與汲極，其 井區中形成基座連接 綜上所述，本發 成埋入層以及電性連 電放電保護電路啟動 下沈層再流至汲極的 流經過閘介電層表面 結構更可以在基底設置一 離層與基座連接區區隔開 井區為相反的摻雜型態。 遵電路的製造方法，此製 中形成埋入層。接著於基 井區與基底的水平交界 中下沈層電性連接至埋入 其後於閘極兩側的井區中 連接至下沈層，之後再於 放電保護電路的基底中形 入層的下沈層，由於在靜 係由源極流会各< 埋入層、 動，因此可以避免過大電 以避免對閘介電層產生例
536802 五、發明說明（4) ^-- 如是燒熔等的影響，進而增加靜電放電保護電路的強韌 度’以提南靜電放電保護電路的保護效能。 而且’由於電流係經由源極、埋入層、下沈層、汲極 的路徑在基底中流動’因此可以藉由基底將電^ ^動所產 生的熱量發散’進而能夠提高靜電放電保雒元件的散埶效 果。 & # 為讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉較佳實施例，並配合所附圖武，作詳細說明 如下： 圖示之標示說明： 100、20 0、3 0 0 :基底 102、20 2、30 2、30 6 : P 井區 104 、 204 、 328a 、 328b :NMOS電晶體 1 0 6、2 0 6 :閘極 108、208、332、338 :源極 110、210、334、340 :汲極 112、116、212、216、314 :淺溝渠隔離層 114、214、346、348 :P+基座連接區域 118、218、33 6、342 :保護環（Guard Ring) 22 0、318、32 0 :下沈層（Sinker Layer) 222、310、312 ··埋入層（Buried Layer) 301 :磊晶層 304 : N 井 31 6、33 0、34 4 :罩幕層
8555hvl.pul 第8頁 536802
322 、 322a 、 322b :閘介電層 32 4、32 4a、3 24b、326、32 6a、326b、326 c :導辦 360:雙載子電晶體 > 體層 40 0 :靜電放電保護電路（ESD)區 41 0 :雙載子電晶體（Bip〇ia]r)區 42 0 :互補式金氧半電晶體（CM〇s)區 較佳實施例 第3 A圖所繪示為本發明較佳實施例之靜電放電保…一 路結構的上視圖，第3B圖所繪示為本發明較佳實】例4， 電放電保護電路結構的剖面示意圖。 之靜 請同時參照第3A圖與第3B圖，本發明之靜電放電 黾路包括·基底200、P井區202、NM0S電晶體2〇4、p + 、口又 連接區域214、淺溝渠隔離層212、下沈層220盥埋入+展基座 Ρ井區20 2係設置於基底200中，其中ρ井區2〇2的推点 形態例如是第一摻雜形態。 NM0S電晶體204係設置於Ρ井區202内，此nm〇S電曰體 2 0 4係由閘極2 0 6、源極2 0 8、汲極2 1 0所構成。其中源極 208、汲極21 0設置於閘極20 6兩側的Ρ井區202中，並且源 極2 0 8、汲極2 1 0的摻雜形態例如是與Ρ井區2 〇 2的摻雜形離 相反的第二摻雜形態。 Ρ+基座連接區域214係環繞NM0S電晶體2〇4而設置於ρ 井區202中，並且在ρ井區202内，Ρ+基座連接區域214係藉
8555tut'.pul 第9頁 536802 五、發明說明（6) 由淺溝渠隔離層21 2與NM0S電晶體2〇4區隔開來 埋入層2 22係設置於電晶體2 04下方的p井區2〇2 200的交界面，其中埋入層222的摻雜形態例如是“ 20 2為不同摻雜形態的第二摻雜形態，且埋入声二 由NMOS電晶體20 4的源極208延伸至汲極21〇。曰 見又你 、下沈層2 20係設置於埋入層222與汲極21〇之 性連接埋入層22 2與汲極210，其中下沈層22〇的摻雜 例如是與P井區2 02為不同摻雜形態的第二播雜形能"，並心且 下沈層22 0的寬度小於汲極21〇的寬度。 心 並且，在此靜電放電保護電路可以更設置一保罐 218，此保護環2 18係設置於基底2〇〇中，且保護 又= 淺溝渠隔離層2 1 6與NMOS電晶體2 04的p+基座&區u ::開”中保護環218的摻雜形態為與p井㈣^ 摻雜形態的第二摻雜形態。 下沈層2 2 0可以在形成埋入層22 2冑，同樣利用一離子 =入的步驟，α於P井區2〇2中形成由？井區2 接至埋入層2 22的下沈層22〇。 电f遷 由於在基底20 0中設置下沈層22〇與埋入層2 22，當靜 2:提電供電了二‘個通雷時’在基底2°°中的下沈層220與埋入層 ^ “阻較低的路徑，因此電流將會由源極2 0 8 机埋入層2 22，再流經下沈層2 20至汲極210。 # & 2 5明較佳實施例中，係以NM〇S靜電放電保護 保错帝、、Ό 况明’然而本發明並不限定於NMOS靜電放電 ”⑺％路，亦可以應用於PM〇s靜電放電保護電路，此時例 536802 五、發明說明（7) 士疋在p型基底中形成N井區，妙 晶體。並且PM0S電晶體同 ；;後在N井區内形成PM0S電 區等構件。而PM0S靜電放電保謹沾汲極、N+基座摻雜 電晶體下方的~井區與基底的交X界广的埋入層設置於PM0S 與N井區為不同摻雜形態 摻:、中二^ PM〇S電晶體的汲極與埋入層，〗:隹下沈層電性連接 為不同摻雜形態的P型摻雜曰。’尤層例如疋與N井區 尚且在上數貫施例中楚 ^ 第二換雜形態為N型摻雜，反V第雜：態為p型摻雜，則 則第二換雜形“P型換雜弟―摻雜形態為㈣推雜， 本發明較佳實施例的靜電放電保護電路的 请參照第4A圖至第4H圖。 万法 第4A圖至第4H圖所繪示為本發明較佳實施例之靜電 電保護電路與雙載子電晶體—互補式金氧半導體製程放 (B1〇lar-CMOS，BiCMOS)製程同時進行的製造流程圖，並 且在較佳實施例中，為求簡化起見，而省略在靜電放電 護電路與CMOS形成PM0S元件的製程。 ” 首先，請參照第4A圖，於第4A圖中提供一個基底 300，並且將此基底300區分為靜電放電保護電路（ESD)區 4〇〇、雙載子電晶體（Bipolar)區410與互補式金氧半電晶 體（CMOS)區4 20。其中此基底300上先形成埋入層31〇和 31 2，其中形成埋入層3 1 0和3 1 2的方法例如是離子植入 法’再形成一層蠢晶層301 ’且蠢晶層301經由摻雜，於靜 電放電保護電路區40 0形成P井區3 02、雙載子電晶體區41〇
536802 五、發明說明（8) 30 6成。N :3:4:及於互補式金氧半電晶體區42 0形成P井區 則N # n /井區3 0 2、3 0 6的摻雜形態為第一摻雜形態， Λ 換雜形態為與P井區30 2、3〇6相反的第二摻 面、^、並且埋入層310係位於Ρ井區302與基底300的交界 、層^12則位於Ν井區304與基底300的交界面。 3 i 4，著^ /參照第4Β圖，並在磊晶層3 0 1中形成隔離層 用以〃隔離層3 1 4例如是淺溝渠隔離層，隔離層3 14係 :二兀件，或是用以區隔相同元件中的不同摻雜區。 316立/4气照第4C圖，形成罩幕層316，並以罩幕層 婼雷、、攸π /1 π對兀件表面進行摻雜步驟，以於靜電放電保 3?8 \ ^ 〇以及雙載子電晶體區4 1 0同時形成下沈層 純、羞拉。其中下沈層3 1 8、320各別與埋入層3 1 0、3 1 2電 .〇9 ’且下沈層318、32〇的摻雜形態例如與ρ井區 _ R 相反的第二摻雜形態。並且，此形成下沈層 、 的摻雜步驟例如是使用離子植入法。 雪样ίί,:請參照第則，去除罩幕層316，並於靜電放 ，：護電路區40 0、雙載子電晶體區41〇與互補式金氧半電 /曰曰體區420的表面依序形成閘介電層322、導體層32 4，然 除雙載子電晶體區410的主動區域的閘介電層322、 Vfe曰324，以暴露出雙載子電晶體區41〇的主動區域的表 面。接著，形成導體層326，以覆蓋導體層324以及雙載子 電晶體區410所暴露的表面。 接著，凊參照第4E圖，定義導體層326、導體層32 4、 閘介電層322 ’以於靜電放電保護電路區4〇〇形成由導體層
536802 五、發明說明（9) 3 2 6a、導體層32 4a、閘介電層32 2a所組成的閘極32 8a，於 雙載子電晶體區410形成導體層326c，於互補式金氧半電 晶體區420形成由導體層326a、導體層324a、閘介電層 3 22a所組成的閘極328a。 接著，請參照第4F圖，在靜電放電保護電路區4 〇 〇、 雙載子電晶體區410與互補式金氧半電晶體區42〇表面形成 圖案化的罩幕層3 3 0，然後以罩幕層3 3 〇為罩幕進行摻雜製 程’以於靜電放電保護電路區4〇〇形成NM〇s電晶體的源極 332、汲極33 4與保護環336，並且於互補式金氧半電晶體 區42 0形成NMOS電晶體的源極338、汲極340與保護環34 2。 接著’凊參照第4 G圖，去除罩幕層3 3 〇，並在靜電放 電保護電路區400、雙載子電晶體區41〇與互補式金氧半電 晶體區420表面形成圖案化的罩幕層344，然後以罩幕層 3 4 4為罩幕進行摻雜製程，以於靜電放電保護電路區4 〇 〇形 成NMOS電晶體的P+基座連接區域346，並且於互補式金氧 半電晶體區4 2 0形成刚8電晶體的？+基座連接區域3 48。 …對於ESD保護電路而言，當製程進行至糾圖時，可 完成ESD保護電路以及CM〇s的結構，最 進行後續製造雙載子電晶體的製程，以於雙載子第電 410形成雙載子電晶體36〇。其中此雙載子 以-般習知的製程製造，因此在此不再贅述。體36 0係以 尚且在上數貫施例中，第一換雜 第二摻雜形態為N型摻雜，及 /心”、、聖摻雜，則 則第二摻雜形態為P型;:雜反之弟一換雜形態為N型摻雜， 536802 五、發明說明（10) 對於BiCMOS製 構的下沈層與埋入 層同時製作，亦即 電路部分的圖案， 罩數目的情況下， 靜電保護電路。 上述本發明較 整合於BiCMOS製程 用之具有下沈層與 並不限定於BiCMOS 他製程整合的靜電 於NM0S的靜電放電 電保護電路。 綜上所述，本 成埋入層以及電性 電保護電路啟動時 流至汲極，由於電 電流經過閘介電層 等的影響，進而增 靜電放電保護電路 而且，由於電 沒極的路徑在基底 所產生的熱量發散 熱效果。 程而言，本發明的 層能夠與雙載子電 是在光罩設計時即 因此於BiCMOS製程 而形成本發明之具 佳實施例係將靜電 ，與BiCMOS製程同 埋入層的靜電保護 製程，亦可以應用 放電保護電路製程 保護電路，亦可以 發明係在靜電放電 連接埋入層與汲極 ’電流係由源極流 流係於基底中流動 表面附近，對閘介 加靜電放電保護電 的保護效能。 流係由源極流經埋 中流動，因此可以 ，進而能夠提高靜 靜電放電保護電路結 晶體的下沈層與埋入 考慮到靜電放電保護 中，能夠在不增加光 有下沈層與埋入層的 放電保護電路的製程 時進行，以製造本發 電路。然而，本發明 於任何單獨或是與其 。並且，亦不限定用 應用於PM0S的靜電放 保護電路的基底中形 的下沈層，在靜電放 經埋入層、下沈層再 ’因此可以避免過大 電層產生例如是燒熔 路的強韌度，以提高 入層、下沈層再流至 藉由基底將電流流動 電放電保護元件的散
次555丨认丨pt(j 536802 五、發明說明（11) 此外，本發明的靜電放電保護電路的製程整合於 BiCMOS製程，與BiCMOS製程同時進行的話，能夠將靜電放 電保護電路的下沈層、埋入層與雙載子電晶體的下沈層、 埋入層使用相同的光罩形成，亦即是在不增加光罩之情形 下，能夠形成具有下沈層與埋入層的靜電放電保護電路。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。
8S55twf ptd 第15頁 536802 圖式簡單說明 圖式之簡單說明： 第1圖所繪示為習知之靜電放電保護電路的結構示意 圖， 第2圖繪示寄生雙載子電晶體特性曲線圖形； 第3 A圖所繪示為本發明較佳實施例之靜電放電保護電 路結構的上視圖， 第3B圖所繪示為本發明較佳實施例之靜電放電保護電 路結構的剖面不意圖，以及 第4A圖至第4H圖所繪示為本發明較佳實施例之靜電放 電保護電路與雙載子電晶體-互補式金氧半導體製程 (Biolar-CMOS，BiCMOS)製程同時進行的製造流程示意 圖。
855Si^ t'.ptd 第16頁

Claims (1)

  1. 536802 六、申請專利範圍 1. 一種靜電放電保護電路，包括： 一基底； 一井區’設置於該基底中，具有一第一換雜形態； 一電晶體，設置於該井區内，該電晶體具有一閘極、 —汲極~ —源極； --基座連接區域，設置於該井區内並環繞該電晶體且 具有一第一摻雜形態； 一第一隔離層，設置於該井區内，其中該第一隔離層 將該基座連接區域與該電晶體區隔開來； 一埋入層，設置於該電晶體下方之該井區與該基底的 交界面，且該埋入層具有一第二摻雜形態；以及 一下沈層，設置於該埋入層與該極汲之間，且其具有 該第二摻雜形態與該埋入層、該汲極電性連接。 2. 如申請專利範圍第1項所述之靜電放電保護電路， 其中更包括於該基底中設置一保護環，其中該保護環以一 第二隔離層與該基座連接區域區隔開來。 3. 如申請專利範圍第2項所述之靜電放電保護電路， 其中該保護環具有該第二摻雜形態。 4. 如申請專利範圍第1項所述之靜電放電保護電路， 其中該下沈層的寬度小於該汲極的寬度。 5. 如申請專利範圍第1項所述之靜電放電保護電路， 其中該埋入層的寬度係由該電晶體下方的該源極延伸至該 汲極。 6. 如申請專利範圍第1項所述之靜電放電保護電路，
    8555twf ptd 第17頁 536802 六、申請專利範圍 其中該第一摻雜形態為p型换 摻雜。 夂4，則該第二摻雜形態為N型 7 ·如申請專利範圍箆] JL中兮證一谈她f ^弟員所述之靜電放電保護電路， 摻雜。’" > 悲:、、、N型摻雜，則該第二摻雜形態為P型 ==底電放電保護電路的製造方法，該製程包括: 換雜：：基底中形成一埋入層…該埋入層具有-第- 形能於Ϊί:中：成一井區’其中該井區具有-第二摻雜 心於^ ί ^ Ϊ 於該井區與該基底的水平交界面； 节埋：1!成一下沈層’纟中該下沈層電性連接至 " θ ，/、中該下沈層具有該第一摻雜形態； 於該井區内形成一閘極； 兮、及兩側的該井區中形成一源極與-沒極，其中 Μ /及極電性連接至該下沈層；以及 於該井區中形成一基座連接區域。 制、告古1申明專利範圍第8項所述之靜電放電保護電路的 衣k / ，其中形成該埋入層的方法包括離子植入法。 f迭m請專利範圍第8項所述之靜電放電保護電路的 極::至該i:該埋入層的寬度係由該電晶體下方的該源 製造1上：，申Λ專利範®第8項所述之靜電放電保護電路的 '，/、中形成該下沈層的方法包括離子植入法。
    8555i\\|’ pt〔i 第18頁 536802 六、申請專利範圍 12 4 由 製造方法Λ專:]範圍第8項所述之靜電放電保護電路的 /、甲该下沈層的寬度小於該汲極的寬度。 f造j·、、如申請專利範圍第8項所述之靜電放電保護電路的 中^第一捧雜形態為p型換雜，則該第二換 製造U·法如，申发請^專利範圍第8項所述之靜電放電保護電路的 .雜形態為p型、接第一摻雜形態為1^型摻雜，則該第二換 -雙載子電種曰半,體疋件的製造方法，該半導體元件包括 電：補式金氧半導體與-靜電放電保護 吩日成衣k方法包括下列步驟·· 區、二雙載底中已形成有-靜電放電保護電路 時於該雙載子電晶體區中形成—第ΐ埋=埋入層，亚同 於孩#電放電保護電路區中形成一 互補式金氧半電晶體區中形成—二成第-Ρ井區，於該 第-Ρ井區與該基底的水平交界面中埋於該 該第一Ν井區與該基底的水平交界面；X 里入s位於 井區區中λ成一第一下沈層並同時於該第-N 以m層該第二下沈層電性連接至該第二埋入層； …“ -P井區上形成一第一關⑽閘極，並於該第二p
    536802 六、申請專利範圍 井區上形成一第二NM0S閘極，並於該第一N井區上形成一 導體層； 於該第一 NM0S閘極兩側的該第一 P井區中形成一第一 NM0S源極與一第一NM0S汲極，同時於該第二NM0S閘極兩側 的該第二P井區中形成一第二NM0S源極與一第二NM0S汲 極； 於該第一 P井區中形成一第一 P+基座連結區域，同時 於該第二P井區中形成一第二P+基座連結區域；以及 於該導體層上形成一雙載子電晶體。 1 6 ·如申請專利範圍第1 5項所述之半導體元件的製k 方法，其中該埋入層的寬度係由該電晶體下方的該源極延 伸至該汲極。 1 7.如申請專利範圍第1 5項所述之半導體元件的製造 方法，其中該下沈層的寬度小於該汲極的寬度。 1 8.如申請專利範圍第1 5項所述之半導體元件的製造 方法，其中該第一下沈層與該第二下沈層係使用相同的製 程步驟形成。 1 9.如申請專利範圍第1 5項所述之半導體元件的製造 方法，其中該第一埋入層與第二埋入層係使用相同的製程 步驟形成。
    8555i\U ptd 第20頁
TW091108181A 2002-04-22 2002-04-22 Structure and fabrication method of electrostatic discharge protection circuit TW536802B (en)

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US10/259,947 US6855611B2 (en) 2002-04-22 2002-09-30 Fabrication method of an electrostatic discharge protection circuit with a low resistant current path
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