TW533569B - A barrier layer for interconnect structures of a semiconductor wafer and method for depositing the barrier layer - Google Patents

A barrier layer for interconnect structures of a semiconductor wafer and method for depositing the barrier layer Download PDF

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Publication number
TW533569B
TW533569B TW091101551A TW91101551A TW533569B TW 533569 B TW533569 B TW 533569B TW 091101551 A TW091101551 A TW 091101551A TW 91101551 A TW91101551 A TW 91101551A TW 533569 B TW533569 B TW 533569B
Authority
TW
Taiwan
Prior art keywords
tungsten
film
patent application
scope
item
Prior art date
Application number
TW091101551A
Other languages
English (en)
Chinese (zh)
Inventor
Siddhartha Bhowmik
Sailesh Mansinh Merchant
Darrell L Simpson
Original Assignee
Agere Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems Inc filed Critical Agere Systems Inc
Application granted granted Critical
Publication of TW533569B publication Critical patent/TW533569B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/035—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/44—Physical vapour deposition [PVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/045—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H10W20/0425—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers comprising multiple stacked seed or nucleation layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)
TW091101551A 2001-09-28 2002-01-30 A barrier layer for interconnect structures of a semiconductor wafer and method for depositing the barrier layer TW533569B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/967,094 US7071563B2 (en) 2001-09-28 2001-09-28 Barrier layer for interconnect structures of a semiconductor wafer and method for depositing the barrier layer

Publications (1)

Publication Number Publication Date
TW533569B true TW533569B (en) 2003-05-21

Family

ID=25512300

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091101551A TW533569B (en) 2001-09-28 2002-01-30 A barrier layer for interconnect structures of a semiconductor wafer and method for depositing the barrier layer

Country Status (5)

Country Link
US (1) US7071563B2 (https=)
JP (1) JP2003142424A (https=)
KR (1) KR20030027784A (https=)
GB (1) GB2380317A (https=)
TW (1) TW533569B (https=)

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US6503824B1 (en) * 2001-10-12 2003-01-07 Mosel Vitelic, Inc. Forming conductive layers on insulators by physical vapor deposition
US8271055B2 (en) * 2002-11-21 2012-09-18 International Business Machines Corporation Interface transceiver power management method and apparatus including controlled circuit complexity and power supply voltage
US7233073B2 (en) * 2003-07-31 2007-06-19 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
US8308053B2 (en) * 2005-08-31 2012-11-13 Micron Technology, Inc. Microfeature workpieces having alloyed conductive structures, and associated methods
US20090242385A1 (en) * 2008-03-28 2009-10-01 Tokyo Electron Limited Method of depositing metal-containing films by inductively coupled physical vapor deposition
DE102011006899B4 (de) * 2011-04-06 2025-01-30 Te Connectivity Germany Gmbh Verfahren zur Herstellung von Kontaktelementen durch mechanisches Aufbringen von Materialschicht mit hoher Auflösung sowie Kontaktelement und eine Vorrichtung zur Herstellung
JP7456178B2 (ja) * 2019-06-18 2024-03-27 Ｔｏｐｐａｎホールディングス株式会社 ガスバリア性積層体およびその製造方法
US11742282B2 (en) * 2020-08-07 2023-08-29 Micron Technology, Inc. Conductive interconnects

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US4647361A (en) * 1985-09-03 1987-03-03 International Business Machines Corporation Sputtering apparatus
US5229323A (en) * 1987-08-21 1993-07-20 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device with Schottky electrodes
JPS6464318A (en) 1987-09-04 1989-03-10 Hitachi Ltd Manufacture of semiconductor device
FR2624304B1 (fr) 1987-12-04 1990-05-04 Philips Nv Procede pour etablir une structure d'interconnexion electrique sur un dispositif semiconducteur au silicium
JPH01296611A (ja) * 1988-05-25 1989-11-30 Canon Inc 半導体薄膜堆積法
JPH05129226A (ja) 1991-11-01 1993-05-25 Seiko Epson Corp 半導体装置の製造方法
US5604158A (en) * 1993-03-31 1997-02-18 Intel Corporation Integrated tungsten/tungsten silicide plug process
US5340370A (en) * 1993-11-03 1994-08-23 Intel Corporation Slurries for chemical mechanical polishing
US5600182A (en) 1995-01-24 1997-02-04 Lsi Logic Corporation Barrier metal technology for tungsten plug interconnection
US5604140A (en) 1995-05-22 1997-02-18 Lg Semicon, Co. Ltd. Method for forming fine titanium nitride film and method for fabricating semiconductor element using the same
US5672543A (en) * 1996-04-29 1997-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Volcano defect-free tungsten plug
EP0841690B1 (en) * 1996-11-12 2006-03-01 Samsung Electronics Co., Ltd. Tungsten nitride (WNx) layer manufacturing method and metal wiring manufacturing method
US5985749A (en) * 1997-06-25 1999-11-16 Vlsi Technology, Inc. Method of forming a via hole structure including CVD tungsten silicide barrier layer
JP3456391B2 (ja) * 1997-07-03 2003-10-14 セイコーエプソン株式会社 半導体装置の製造方法
US5956609A (en) * 1997-08-11 1999-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method for reducing stress and improving step-coverage of tungsten interconnects and plugs
US5847463A (en) 1997-08-22 1998-12-08 Micron Technology, Inc. Local interconnect comprising titanium nitride barrier layer
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JP3436132B2 (ja) * 1998-05-13 2003-08-11 セイコーエプソン株式会社 半導体装置
US6372633B1 (en) * 1998-07-08 2002-04-16 Applied Materials, Inc. Method and apparatus for forming metal interconnects
US6037263A (en) * 1998-11-05 2000-03-14 Vanguard International Semiconductor Corporation Plasma enhanced CVD deposition of tungsten and tungsten compounds
US20020132473A1 (en) * 2001-03-13 2002-09-19 Applied Materials ,Inc. Integrated barrier layer structure for copper contact level metallization
US20020144889A1 (en) * 2001-04-09 2002-10-10 Applied Materials, Inc. Burn-in process for high density plasma PVD chamber

Also Published As

Publication number Publication date
GB2380317A (en) 2003-04-02
KR20030027784A (ko) 2003-04-07
GB0204747D0 (en) 2002-04-17
JP2003142424A (ja) 2003-05-16
US7071563B2 (en) 2006-07-04
US20030062626A1 (en) 2003-04-03

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