TW506024B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TW506024B
TW506024B TW090101994A TW90101994A TW506024B TW 506024 B TW506024 B TW 506024B TW 090101994 A TW090101994 A TW 090101994A TW 90101994 A TW90101994 A TW 90101994A TW 506024 B TW506024 B TW 506024B
Authority
TW
Taiwan
Prior art keywords
lead
trapezoidal
point
bonding
bent
Prior art date
Application number
TW090101994A
Other languages
English (en)
Inventor
Shinichi Nishiura
Original Assignee
Shinkawa Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
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Application filed by Shinkawa Kk filed Critical Shinkawa Kk
Application granted granted Critical
Publication of TW506024B publication Critical patent/TW506024B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
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    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/48095—Kinked
    • H—ELECTRICITY
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/491—Disposition
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/491—Disposition
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
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    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

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506024 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（/ ) 【發明所屬之技術領域】 本發明’關於積層複數個半導體晶片的半導體裝置。 【習知技術】 半導體裝置，最近被要求更大容量、高機能、高集積 化。爲因應該要求，已提供一封裝體，其藉由積層並搭載 複數個半導體晶片，以提高構裝密度。如此般來提高構裝 密度之封裝體中，爲防止因所鄰接之引線彼此之接觸及樹 脂封裝時之模製所引起之引線彎曲等而產生引線間短路的 事故，必須將引線之上下間隔取寬。 經積層之半導體晶片之墊側的引線部分，必須取相當 程度之上下間隔。然而，導線架之引腳側之引線部分，因 引腳結合點位於平面上，故引線之上下間隔必然變窄。因 此以往，例如特開平11 一204720號公報等所示，將導線架 之朝鄰接引腳的結合點從第2結合位置挪開。 【發明所欲解決之課題】 上述習知技術，因將引腳之結合點從第2結合位置挪 開來進行結合，故半導體裝置變大。又若結合距離變長， 則會發生由於引線之下垂所引起之引線短路。 本發明之課題，係在於提供：能圖謀小型化，同時即 使結合距離變長，不發生引線短路的半導體裝置。 【用以解決課題之手段】 爲解決上述課題本發明之第1手段，其特徵在於：將 複數個半導體晶片積層固定於導線架，將半導體晶片之第 1接合點與導線架之引腳之第2結合點間以梯形環狀之引 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----------:---裝· ----—訂----------線-----AWI (請先閱讀背面之注意事項再填寫本頁) 506024 A7 B7 五、發明說明（>) 線連接，該梯形環狀之引線係由··從第1結合點豎立之頸 部高度，連接於該頸部高度之梯痕部，連接於該梯形部、 往第2結合點之方向傾斜而結合於該第2結合點之傾斜部 所構成環狀；在最上位之引線以外之引線之前述傾斜部， 至少在最下位之引線形成彎曲部。 爲解決上述課題本發明之第2手段，其特徵在於：將 複數個半導體晶片積層固定於導線架，在半導體晶片之第 1結合點與導線架之引腳之第2結合點間以梯形環狀之引 線連接，該梯形環狀之引線係由：從第1結合點豎立之頸 部高度，連接於該頸部高度之梯形部，連接於該梯形部、 往第2結合點之方向傾斜而結合於該第2結合點之傾斜部 所構成環狀；最上位之引線以外之引線之前述傾斜部，係 形成有第3彎曲部，並由連結第2彎曲部(梯形部與傾斜部 之連接部)及前述第3彎曲部之傾斜角大的梯形部側傾斜部 、以及連結前述第3彎曲部與第2接合點而傾斜角比前述 梯形部側傾斜部小之引腳側傾斜部所構成；前述第2彎曲 部中，下方之第2彎曲部最離遠第2結合點，越往上方之 第2彎曲部越靠第2結合點側；又從下方之梯形部側傾斜 部至上方之梯形部側傾斜部，越往上位之傾斜部傾斜角越 大，從下方之引腳側傾斜部至上方之引腳側傾斜部，越往 上位之傾斜部傾斜角越大。 【發明之實施形態】 以圖1說明本發明之第1實施形態。在具有引腳1之 導線架2，積層搭載3個半導體晶片3A，3B，3C。在此， 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) --裝 訂.---------線-- 經濟部智慧財產局員工消費合作社印製 506024 A7 B7 五、發明說明（3) 導線架2與半導體晶片3A，半導體晶片3A與3B，半導體 晶片3B與3C，各係以未圖示之i著片或接著劑固定。在 半導體晶片3A，3B，3C之電極之第1結合點4A，4B，4C 及引腳1之第2結合點5A，5B，5C，以未圖示之引線結合 裝置將引線6A，6B，6C連接爲梯形環狀。又，第2結合 點5A，5B，5C之位置，係沿相對於各引腳1之直角方向 排列成直線狀。 引線6A，6B，6C，係呈下列形狀··由將形成於插通 在未圖示之打線裝置毛細管之引線之前端的球體，接合於 第1接合點4A，4B，4C而豎立之頸部高度7A，7B，7C， 連接於該頸部高度7A，7B，7C之梯形部8A，8B，8C，及 連接於該梯形部8A，8B，8C傾斜於第2結合點5A，5B， 5C之方向而結合於該第2結合點5A，5B，5C之傾斜部9A ，9B，9C所形成。 在頸部高度7A，7B，7C與梯形部8A，8B ’ 8C之連 接部，形成第1彎曲部15A，15B，15C，在梯形部8A ’ 8B ，8C與傾斜部9A，9B，9C之連接部，形成第2彎曲部 16A，16B，16C。最上位之引線6C之傾斜部9C以外之引 線6A，6B之傾斜部9A，9B，係由傾斜角大之梯形部側傾 斜部17A，17B，及傾斜角比該梯形部側傾斜部17A ’ 17B 小之引腳側傾斜部18A，18B所形成，在梯形部側傾斜部 17A，17B與引腳側傾斜部18A，18B之連接部’形成第3 彎曲部19A，19B。 第2彎曲部16A，16B，16C，第2彎曲部16A最離遠 6 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) i裝 訂---------線----- 經濟部智慧財產局員工消費合作社印製 506024 A7 B7 五、發明說明（f) 於第2接合點5A，第2彎曲部16B，16C依序挪移於第2 結合點5B，5C，且以依序變高之务式形成。梯形部側傾斜 部17A，17B，傾斜部9C之傾斜角，形成爲梯形部側傾斜 部17A最小，梯形部側傾斜部17B，傾斜部9C依序變大。 又引腳側傾斜部18A，18B，傾斜部9C之傾斜角，形成爲 引腳側傾斜部18A最小，引腳側傾斜部18B，傾斜部9C依 序變大。 如上所述梯形環狀之引線6A，6B，例如能以特開平 10—199916號公報所示之引線結合方法形成。又梯形環狀 之引線6C，則能以在前述公報作爲習知技術所列舉之引線 結合方法形成。 如上所述，引線6A，6B，6C之第2彎曲部16A，16B ，16C，下方之第2彎曲部16A最離遠於第2結合點5A， 越上方之第2彎曲部16B，16C越靠第2結合點5B，5C側 ，又梯形部側傾斜部17A，17B，傾斜部9C之傾斜角，依 序變大，又引腳側傾斜部18A，18B，傾斜部9C之傾斜角 ，亦依序變大。因此，即使第2結合點5A，5B，5C呈直 線狀，因第2結合點5A，5B，5C側之引腳側傾斜部18A ，18B，傾斜部9C之間隔變寬，故能防止引線6A，6B， 6C同伴之接觸及灌注樹脂時之造模所引起之引線6A，6B ，6C之彎曲等。即，第2結合點5A，5B，5C之位置能沿 相對於各引腳1之直角方向排列成直線狀，故能圖謀半導 體裝置之小型化。又即使結合距離變長亦不會發生引線短 路。 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -丨裝 —訂---------線----- 經濟部智慧財產局員工消費合作社印製 506024
五、發明說明（f) ---------------裝 (請先閱讀背面之注意事項再填寫本頁) 圖2至圖6，係顯示本發明之第2至第6實施形態。 以下，對與前述第1實施形態相幽或相當部分使用同一符 號，而省略其詳細說明。 •線- 圖2，係顯示本發明之第2實施形態。圖1，係就適用 在引線6A，6B，6C形成爲俯視不交叉之情形說明。圖2， 係顯不引線6A對引線6B，6C形成爲俯視交叉之情形。在 該情形，亦與前述第1實施形態同樣，引線6A，6B，6C 之第2彎曲部16A，16B，16C，下方之第2彎曲部16A最 離遠第2結合點5A，越往上方之第2彎曲部16B，16C越 靠第2結合點5B，5C側，又梯形部側傾斜部17A，17B， 傾斜部9C之傾斜角，依序變大，又引腳側傾斜部18A， 18B，傾斜部9C之傾斜角，亦依序變大。因此，即使第2 結合點5A、5B、5C之位置沿相對於各引腳1之直角方向 排列成直線狀，因第2結合點5A，5B，5C側之引腳側傾 斜部18A，18B，傾斜部9C之間隔變寬，故能獲得與圖1 之第1實施形態同樣之效果。 經濟部智慧財產局員工消費合作社印製 圖3及圖4，係顯示本發明之第3至第4實施形態。 圖1及圖2，係就適用於積層3個半導體晶片3A，3B，3C 者之情形說明。圖3及圖4，係顯示適用於積層2個半導 體晶片3A，3C者之情形。該情形，亦引線6A，6C之第 2彎曲部16A，16C，下方之第2彎曲部16A最離遠第2結 合點5A，越往上方之第2彎曲部16C越靠第2結合點5C 側，又梯形部側傾斜部17A，傾斜部9C之傾斜角，依序變 大，又引腳側傾斜部18A，傾斜部9C之傾斜角，亦依序變 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 506024 _____B7__ 五、發明說明（t)) 大。因此，即使第2結合點5A，5C之位置沿相對於各引 腳1之直角方向排列成直線狀，g第2結合點5A，5C側 之引腳側傾斜部18A，傾斜部9C之間隔變寬，故能獲得與 圖1之第1實施形態同樣之效果。即，所積層之半導體晶 片3A ’ 3B ’ 3C · · ·之數目，不限定於前述之3個或2個 ，即使是4個以上亦能同樣適用。 圖5及圖6，係顯示本發明之第5至第6實施形態。 在圖1及圖2，係僅圖示對各半導體晶片3A，3B，3C各有 1個第1結合點4A，4B，4C，僅圖示對應其第1結合點4A ，4B，4C之引腳1。然而，一般，各半導體晶片3A，3B ，3C之第1結合點4A，4B，4C，係順沿各半導體晶片3A ，：3B，3C之各邊複數設置，對應各自之第1結合點4A， 4B，4C設置引腳1。圖5及圖6，係作爲1例，顯示適用 於在半導體晶片3A除沿各邊之第1結合點4A以外具有第 1結合點4A1者之情形。
該情形亦與第1實施形態同樣，引線6A，6A1，6B， 6C之第2彎曲部16A，16A1，16B，16C，下方之第2彎 曲部16A最離遠第2結合點5A，越往上方之第2彎曲部 16A1，16B，16C越靠第2結合點5A ：l，5B，5C側，又梯 形部側傾斜部17A，17A1，17B，傾斜部9C及引腳側傾斜 部18A，18A1，18B，.傾斜部9C之傾斜角，依序變大。因 此，即使第2結合點5A，5A1，5B，5C之位置沿相對於各 引腳1之直角方向排列成直線狀，因第2結合點5A，5A1 ，5B，5C側之引腳側傾斜部18A，18A1，18B，傾斜部9C 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)
506024 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（^)) 之間隔變寬，故能獲得與圖1之第1實施形態同樣之效果 。圖中，19A1係顯示引線6A1之窠3彎曲部。 又，在上述各實施形態，雖在最上位之引線6C以外 之引線6A，6A1，6B之傾斜部9A，9A1，9B，全部形成第 3彎曲點19A，19A1，19B，但至少在最下位之引線6A形 成第3結合點19A，亦具有效果。 【發明之效果】 本發明，因將複數個半導體晶片積層固定於導線架， 將半導體晶片之第1結合點與導線架之引腳之第2結合點 間以梯形環狀之引線連接，該梯形環狀之引線係由：從第 1結合點豎立之頸部高度，連接於該頸部高度之梯形部， 連接於該梯形部，傾斜於第2結合點之方向，而結合於該 第2結合點之傾斜部三者所構成，在最上位之引線以外之 引線之前述傾斜部，至少在最下位引線形成彎曲部，故能 圖謀半導體裝置之小型化，同時即使結合距離變長亦不會 發生引線短路。 【圖式之簡單說明】 圖1，係顯示本發明之半導體裝置之第1實施形態， (a)係前視說明圖，（b)係俯視說明圖。 圖2，係顯示本發明之半導體裝置之第2實施形態， ⑻係前視說明圖，（b)係俯視說明圖。 圖3，係顯示本發明之半導體裝置之第3實施形態， (a)係前視說明圖，（b)係俯視說明圖。 圖4，係顯示本發明之半導體裝置之第4實施形態， 10 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 丨裝 -{ ·ϋ ί 1· 一 οτ I n ί I n n I— n I d n m n . 506024 A7 B7 五、發明說明（/ ) ⑷係前視說明圖，（b)係俯視說明圖。 圖5，係顯示本發明之半導體'裝置之第 ⑷係前視說明圖，（b)係俯視說明圖。 圖6,係顯示本發明之半導體裝置之第 (a)係前視說明圖，（b)係俯視說明圖。 【符號說明】 實施形態 實施形態 1 引腳 2 導線架 3A 3B， 3C 半導體晶片 4A 4A1 ，4B， ，4C 第1結合點 5A 5A1 ，5B， ，5C 第2結合點 6A 6A1 ，6B， -6C 引線 7A 7A1 ，7B， 、1C 頸部高度 8A 8A1 ，8B， ^ 8C 梯形部 9A 9A1 ，9B， -9C 傾斜部 經濟部智慧財產局員工消費合作社印製 15A，15A1，15B 16A，16A：i，16B 17A，17A：l，17B 18A，18Α；ί，18B 19Α，19Α卜 19Β
15C 16C 第1彎曲部 第2彎曲部 梯形部側傾斜部 引腳側傾斜部 第3彎曲部 11 -------r I -------. ----—訂.丨丨 ------I ------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）

Claims (1)

  1. 506024 A8 B8 C8 D8 六、申請專利範圍 1、 一種半導體裝置，其特徵係：將複數個半導體晶片 積層固定於導線架，將半導體晶片之第1結合點與導線架 之引腳之第2結合點間以梯形環狀之引線連接，該梯形環 狀之引線係由·從第1結合點暨JJL之頸部筒度，連接於該 頸部高度之梯形部，及連接於該梯形部、往第2結合點之 方向傾斜而結合於該第2接合點之傾斜部三者所構成； 在最上位引線以外的引線之前述傾斜部，至少在最下 位之引線形成彎曲部。 2、 一種半導體裝置，其特徵係：將複數個半導體晶片 積層固定於導線架，將半導體晶片之第1結合點與導線架 之引腳之第2結合點間以梯形環狀之引線連接，該梯形環 狀之引線係由：從第1結合點豎立之頸部高度，連接於該 頸部高度之梯形部，及連接於該梯形部、往第2結合點之 方向傾斜而結合於該第2接合點之傾斜部三者所構成； 最上位引線以外的引線之前述傾斜部，係形成有第3 彎曲部，並由連結第2彎曲部(梯形部與傾斜部之連接部) 及則述第3彎曲部之傾斜角大的梯形部側傾斜部、以及連 結前述第3彎曲部與第2結合點之傾斜角比前述梯形部側 傾斜部小之引腳側傾斜部所形成； 前述第2彎曲部中，下方之第2彎曲部最離遠第2結 合點，越往上方之第2彎曲部越靠第2結合點側； 又從下方之梯形部側傾斜部至上方之梯形部側傾斜部 ，越往上位之傾斜部其傾斜角越大，從下方之引腳側傾斜 部至上方之引腳側傾斜部，越往上位之傾斜部其傾斜角越 1 本紙張尺度適用中國國家標準（CNS)A4規袼（210 X 297公釐） ------------^---裝·* (請先閱讀背面之注意事項再填寫本頁) 訂： -線 經濟部智慧財產局員工消費合作社印製 506024 A8 B8 C8 D8 六、申請專利範圍 大 ---I---J------. IAW----— 訂-丨 I (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）
TW090101994A 2000-06-02 2001-02-01 Semiconductor device TW506024B (en)

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US8575719B2 (en) 2000-04-28 2013-11-05 Sandisk 3D Llc Silicon nitride antifuse for use in diode-antifuse memory arrays
AU2001286432A1 (en) 2000-08-14 2002-02-25 Matrix Semiconductor, Inc. Dense arrays and charge storage devices, and methods for making same
JP2002124626A (ja) * 2000-10-16 2002-04-26 Hitachi Ltd 半導体装置
US7352199B2 (en) * 2001-02-20 2008-04-01 Sandisk Corporation Memory card with enhanced testability and methods of making and using the same
US6843421B2 (en) 2001-08-13 2005-01-18 Matrix Semiconductor, Inc. Molded memory module and method of making the module absent a substrate support
US6525953B1 (en) 2001-08-13 2003-02-25 Matrix Semiconductor, Inc. Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication
US6624485B2 (en) 2001-11-05 2003-09-23 Matrix Semiconductor, Inc. Three-dimensional, mask-programmed read only memory
US6731011B2 (en) 2002-02-19 2004-05-04 Matrix Semiconductor, Inc. Memory module having interconnected and stacked integrated circuits
JP3888438B2 (ja) * 2002-02-25 2007-03-07 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
US6853049B2 (en) 2002-03-13 2005-02-08 Matrix Semiconductor, Inc. Silicide-silicon oxide-semiconductor antifuse device and method of making
US6933223B1 (en) * 2004-04-15 2005-08-23 National Semiconductor Corporation Ultra-low loop wire bonding
JP2008034567A (ja) * 2006-07-27 2008-02-14 Fujitsu Ltd 半導体装置及びその製造方法
KR100843441B1 (ko) * 2007-01-02 2008-07-03 삼성전기주식회사 멀티칩 패키지
JP5595694B2 (ja) 2009-01-15 2014-09-24 パナソニック株式会社 半導体装置
US9478495B1 (en) 2015-10-26 2016-10-25 Sandisk Technologies Llc Three dimensional memory device containing aluminum source contact via structure and method of making thereof

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