TW501201B - Semiconductor device and its production process - Google Patents

Semiconductor device and its production process Download PDF

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Publication number
TW501201B
TW501201B TW089122811A TW89122811A TW501201B TW 501201 B TW501201 B TW 501201B TW 089122811 A TW089122811 A TW 089122811A TW 89122811 A TW89122811 A TW 89122811A TW 501201 B TW501201 B TW 501201B
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TW
Taiwan
Prior art keywords
copper
layer
wiring layer
metal wiring
film
Prior art date
Application number
TW089122811A
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English (en)
Inventor
Kazunori Fujisawa
Nobuyoshi Awaya
Original Assignee
Sharp Kk
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Publication of TW501201B publication Critical patent/TW501201B/zh

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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
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501201 五、發明說明（1) 發明標題 半導體裝置及其製 衣&方法 發明背景 1.發明領域 本發明與半導體裝置及製造方法有 導體裝置及製造方法有關，該方法可^三更詳細的，與半 鋁焊墊，直接地讓導線接合在以鋼需要形成接合用之 溫μ 馬主要成分之金屬接線 2,相關技藝之說明 内含銅之金屬接線層具有 阻值。因此，它可以降低半 線層所導致的信號延遲。特 密度電流時，内含銅之金屬 度。從這個角度看，銅已開 材質。 :ϋ电阻’顯示出良好的移動 導f裝置之積體電路中金屬接 別疋§ 4半導體裝置操作在高 接線層可以確保極高的可靠 始取代銘’成為金屬接線層的 、而現今，内含銅之金屬接線層則主要是使用在具高速度 邏輯電路（像是，微處理器）之半導體裝置中。採用覆晶2 術來封裝該半導體裝置，此技術會在半導體裝置（半導體 曰曰片）上形成一個凸塊。在一般用途之半導體裝置中，其 所接合的乃是以金或鋁所做成的導線。此種接合所牵涉到 的最低加熱溫度大約是攝氏2 0 0度。因為銅在此溫度時很 谷易氧化深達其内部，所以，要在不影響裝置品質的情況 下執行接合動作是很困難的。 為了克服此麻煩，提出一種方法，其可在插進（或不 501201 五、發明說明（2) 一'"' — - 插進）金屬的擴散障壁層的情況下，於銅製的金屬接線層 上形成一链焊墊（看曰本未檢核專利品號hei 8 ( 1 9 96 )- 78410 以及HEI 1 1 ( 1 9 9 9 )- 1 3 5 50 6 )。 現在參考圖3 (a)至3 (e )，說明上述方法之其中一例。 先於矽基板1上，形成一擴散層丨〇，再以二氧化矽、氮 化矽或相類似的絕緣材質做出内層介電薄膜2。接著，1 忒内層介電薄膜2中，開一個接觸孔。為了強化稍後鋼接 線層5形成於該内層介電薄膜2上的黏著力，我們以化學氣 相沈積法形成一層助長黏著層4。此助長黏著層4還可當作 擴散障壁薄膜，避免銅從該銅接線層5擴散至該内層介電 薄膜2。以直流濺鍍法在該助長黏著層4之上形成一銅膜， 則該接觸孔會被銅膜5，所填滿（看圖3(a))。 接著，在該銅膜5,上形成一抗反射薄膜u(看圖3(b))。 接下來，以光照相製版及蝕刻步驟，將該鋼膜5,做成具 所欲圖案之銅接線層5。接著，在該銅接線層5的表面形成 一層由絕緣材質（像是二氧化矽，氮化矽或相似材質）所作 成的表面保護膜1 2。再進一步地，選擇性地去除表面保護 膜12及抗反射薄膜11，以曝露出部份的銅接線層$。因 此，開了一個焊墊區7a (看圖3 (c))。 在開了焊墊區7a之後，則在該焊墊區7a的開口中，形成 厚度分別為大約2 0至1 〇 〇毫微米及大約2微米之擴散障壁層 3(像是氮化鈦）以及抗氧化金屬膜丨3(像是A1SiCu )。接 著’僅將焊墊區7 a附近的擴散障壁層3及抗氧化金屬膜）3 留下來（看圖（3d))。 '
501201 五、發明說明（3) '---- 在作接合時不論是使用超音波導線接合（使用此法，接 合面要加熱到攝氏2 0 0度或更高），還是熱壓縮導線接合 (使用此法，接合面要加熱到攝氏4〇〇度或更高），採用"了 U在焊塾區7a中之銅接線層5上覆蓋抗氧化金屬膜13的 結構丄均可使該銅接線層5在接合期間免於被氧化。圖 3(e)說明了導線8接合在焊墊區7a中的狀況。 =4所示之斷面圖，為一半導體裝置例，其具有兩個内 線可接合於此之接線層，接合方式則揭示於曰本 未檢核專利品號HEI 1 1 ( 1 999 )_ 1 3 5 5 〇6中。此半導體的製 程如下.首先，以鑲嵌法形成一銅接線層5b，在i上 -層絕緣膜6 ’然後開一個接合焊墊部份。接二 處 絕緣膜6之上覆蓋一層含鋁之薄膜9，接著再以光昭相黎;版 及钮亥j步驟，部份地去除該含紹之薄膜9，將該接墊 部= 的含銘膜留下來；接下來，將金、㉟或相似材質製 之V、，泉8，接合至邊接合焊墊部份。在此圖中，“至^表 示内層介電薄膜，33至3(：為擴散障壁 散障壁薄膜，5a則為銅接線層。 〇巧们擴 在，3(a)至3(e)所不的方法申，該擴散障壁層及抗氧化 =表面上’然後再以光照相製版及餘刻 ν知將之k擇性地去除，留τ在接合焊塾中的部份。因 此’此方法需要很多的製造步驟，導致製造成本的增加。 圖4中所不的方法，其中在該鋼接線層上所 之塾面，這需要額外的沈積銘或：及 擴政障土金屬之y驟，以及光照相製版步驟及蝕刻步驟或
第7頁 501201 五、發明說明（4) 是化學機械研磨步驟。因此，此方法需要較以鋁作内連接 更多的製造步驟，這導致了製造成本的增加。 發明摘要 於是，本發明提供出一種製造半導體裝置之方法，其所 包含之步驟：於半導體基板上形成一以銅為主要成分之金 屬接線層；於最終半導體基板的整個表面上，形成一絕緣 薄膜；僅將與金或铭導線接合處之絕緣薄膜予以去除，以 便曝露部份的金屬接線層；在該金屬接線層曝露部份的表 面層中，形成一層銅的石夕化物或是一層銅與硼的化合物； 以及將導線接合至該銅的矽化物層的表面或該銅與硼之化 合物層的表面。 另外，本發明提供出一種半導體裝置其包含，於半導體 基板上之一以銅為主要成份之金屬接線層；以及一用以接 合導線之銅矽化物層或銅與硼之化合物層，該佈局層形成 在部份金屬接線層的表層中。 本發明的這些及其他目標，在經以下之詳細說明後，將 變得顯明。不過，應注意，該詳細的說明及特定的例子雖 然指明了本發明之具體實施方式，但其僅止於說明用；習 於此藝人士只要是在本發明之精神與範圍内，針對這些例 子之各種變更及修改是輕而易舉的。 圖式之簡要說明 圖1(a)至1(e)是斷面圖，其說明了本發明製造半導體裝 置之方法； 圖2是本發明之半導體裝置的斷面圖。
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五、發明說明（5) 了先前技藝製造半導體 圖3(a)至3(e)是斷面圖，其說明 裝置之方法； 圖。 要詳細說明本發 不應以此為本發明 &圖4是先前技藝之半導體裝置的斷面 車父佳具體實施例之說明 現在參考著圖1(a)至1(e)以及圖2， 月。應注意，這些圖式旨在呈現範例 之限。 = i(a)至1(e)是斷面圖，其依序地說明了本發明製造 :趑裝置之方法例。雖然此處所舉之例是將本笋明之方
具有㈣接線層之裝置上，但本發明之^法亦可 早個接線層的結構上，或是具有三或多.個接 層接線結構上。 …固接線層之 首先 成一内 是任何 是基本 像是碎 元件， 的元件 可作SiON、 氧化矽 的。可 防止銅 ’以化學氣 層介電層2a 已知的基板 的基板，像 化嫁基板。 可以事先形 ，在圖1 ( a ) 為該内層介 摻了磷的氧 等，除這些 提供出關於 擴散之絕緣 相沈積法或旋轉塗 及一擴散障壁層3a 地限制 鍺基板 像是電 上。這 予省略 ，沒有特別 是矽基板及 另外 些 成在該基板 至1 (e)中均 電膜之材質 化物、摻了 之外，具低 該内層介電 薄膜，都可 為··二 硼和磷 介電常 膜之蝕 以作為 佈法’在基板1上形 。此處，該基板可以 。譬如’該基板可以 ’或是化合物基板， 晶體，負載等這樣的 些可能出現在基板上 〇 氧化矽、氮化矽、 的氧化物、含氟之二 數之材質都是可以 刻選擇比率及有能力 該擴散障壁層。此種
：)U1厶U丄 五、發明說明（6) 絕緣膜包括条^ ^ ^ 接下爽化夕’石反化石夕等，均為其例。 木’以光照相製版步驟及蝕列 層之接觸孔及泪、、番 少哪汉蝕刻步驟，形成第一接線 序地形成用^ =溝在忒内連接用之渠溝形成之後，再依 著，以= : = 接線層之銅擴散障壁膜及銅膜。接 剖份予以去二：：f將该銅擴散障壁膜及銅膜不需要的 5a所構成的第_ 伙出由銅擴散障壁膜4a及銅接線層 膜、鉻；U、線層。該銅擴散障壁層可以由组膜、鎢 相似材ΐ膜：=膜二：膜、軸膜，膜、_膜或 似法來做1 _法、化學氣相沈積法或相類 或相類似法來成形。另外 匕：m積纟：電鍍法 銅銀合金獏、鋼夢入金膜$ , 要成份的薄膜像是， 膜。 °金膜或相類似膜，都可以用作為該銅 第二銅接線層的成形方式與第_ 、 、 (看圖接線層的成形方式相同 (看圖(b及 =(c))。在該二圖中，⑪至 ΐ第障r’4b為銅擴散障壁膜二b為 。亥第一銅接線層。因考慮到要在該第 化及硼化，所以依以下步驟 ^接線層表面上石夕 接線層的厚度最好是。.5至2::路在接合焊墊部份中的銅 -二譬如二Λ氣相沈積法，在整個表面上形成 版步驟及飯刻步驟，將位在接合焊^;/^用光照相製 表面曝露出來（看圖！⑷）。卜塾部份中的銅接線層的 之後，將位在接合焊塾部份中的銅表面放在反應腔中加 第10頁 501201 五、發明說明（7) 熱’腔中之空氣抽離僅保有氮氣或是真空。僅保有氮氣或 疋真空的理由是，有銅曝露於外之晶圓若在空氣中加熱， 鋼έ被氧化。因此’欲執行本發明’最好是使用具真空腔 之裝置。 〃 接下來，將矽烷（Si Η4)氣體或二硼烷（Β2Η6)氣體導入反 應腔中。銅的表面曝露在該氣體中，在該曝露銅的表面上 就會形成一銅矽化物層7或銅硼化合物層7 (看圖1 ( e))。除 了矽烷氣體之外，矽化用之氣體還可以是二矽烷（Si2H6)氣 體，二氟矽烷（SiH2F2)氣體，三矽烷（Si3H8)氣體。 此處’在將基板放入反應腔之前’最好是先去除可能會 出現在銅表面的氧化物薄膜，以便所選的曝露鋼面是乾淨 的。使用有能力選擇性地去除銅氧化物之蝕刻液，像是氣 氟酸，檸檬酸或相類似酸，可以將該氧化物薄膜予以去 除。 根據上述之本發明方法，因為只有在該接合焊墊部份中 的銅表面會被石夕化或謂化，所以該銅接線層的阻值很難受 到影響。反倒是，為了要能徹底的避免接合處遭到氧化， 該銅表面最好是能矽化或硼化至1 0毫微米至1 〇 〇毫微米 厚。 相反地，根據先前之銅接線層表面的矽化技術，譬如， 日本未檢核專利品號HE I 9 ( 1 9 9 7) - 3 2 1 0 4 5中所揭示的石夕化 技術，銅接線層的整個頂面及侧壁都需要矽化。因此若十 足地矽化，則阻值就會上升，其結果是，使用銅接線層的 好處就會喪失。若矽化的程度是在電阻值可接受的範圍
501201 五、發明說明（8) · " " 内’則當我們以較低的壓力，用化學氣相沈積法來做二氧 化石夕薄膜時，該銅接線層尚能抵抗幾秒鐘，但當我們將導 線接合在銅所曝露的接合焊墊區時，該銅接線層將會曝露 在加熱或潮濕的大氣中，其最終會無可抵抗地遭到氧化。 我們可根據裝置的尺寸、晶圓的尺寸及反應腔中的總壓 力，將基板的溫度，氣體的流率以及曝光的時間調整到最 ^的狀況。譬如，若一個6英吋的晶圓是在一個半徑3〇公 =、深30公分之柱狀反應腔中的直徑為2〇公分的碟狀加熱 器上加熱，則該基板的溫度，氣體的流率以及曝光的時間 就可以是攝氏3 0 0至40 0度，每分鐘10至1〇〇西西，以及3〇曰 秒至2分鐘。反應腔中的壓力可以是大氣壓力或〇· i至托 5壓力。若是在大氣壓力下執行矽化或硼化，貝4最 ,:? 1 :升之*率’導入混著矽烷或硼烷之惰性氣體(像 疋’ SI)來控制矽烷或二硼烷的部份麗力。 物mi種條件，以便該銅矽化物層或該銅硼化入 :層中之銅的顯阻性可以在2.5至5微歐公分的範圍内。; ’：據本發明’該矽化或硼化僅發生在該接合 開口中’除開此，該接線層的其他部份則完 匕
的保護之下。因此，在本發明中，僅曝露出的銅：電緣： :有增加。銅表面的矽化或硼化可以一 /到J ;足夠的抗氧化性為止，不會對電路的效能有不利“具 接著， 中，再以 將最終得到的半導體裝 已知的接合技術將譬如 置加以切割並固定在封裝 ’金製之導線8接合至該
501201 五、發明說明（9) 銅接線層（看圖2 )。 根據本發明，（1)可直接地將導線接合至銅接線層之焊 墊部份，毋需在該焊墊部份中形成鋁焊墊，以及（2 )因為 只有在該接合焊墊部份中之銅的抗氧化性有增進，所以可 在不導致部分接線層電阻值增加的情況下，增進該接合焊 墊部份之抗氧化性，這對該半導體裝置之電路效能是有幫 助的。
另外，根據本發明，提供出一可確保導線穩定地接合至 該銅接線層之半導體裝置，是有可能的。
第13頁 501201 圖式簡單說明
1IIHI 第14頁

Claims (1)

  1. 501201 案號89] 六、申請專利範圍
    :簡 充 Q月 日_修正名 1. 一種半導體裝置之製造方法，其包含以下步驟： 於半導體基板上形成一以銅為主要成分之金屬接線層； 於最終半導體基板的整個表面上，形成一絕緣薄膜； 僅將與金或鋁導線接合處之絕緣薄膜予以去除，以便曝 露部份的金屬接線層； 在該金屬接線層曝露部份的表面層中，形成一層銅的矽 化物或是一層銅與棚的化合物；以及 將導線接合至該銅之矽化物層的表面或該銅與硼之化合 物層的表面。
    2. 如申請專利範圍第1項之方法，其中該形成在該以銅 為主要成分之金屬接線層表面之銅的矽化物層或銅與硼的 化合物層，其所具有的厚度為10至100毫微米。 3. 如申請專利範圍第1項之方法，其中該銅與硼的化合 物層乃以二硼烷與該含銅之金屬接線層起反應所形成。 4. 如申請專利範圍第1項之方法，其中該銅的矽化物層 或銅與硼的化合物層所具有的電阻值為2. 5至5微歐公分。 5. 如申請專利範圍第1項製造半導體之方法，其中從 銅，銅銀合金以及銅锆合金層中，挑選出該金屬接線層。 6. —種半導體裝置，包含：
    一金屬接線層，其位在半導體基板之上，内含以銅為主 要成分；以及 一銅的矽化物層或銅與硼的化合物層，其係接合導線 用，該層形成在部份該金屬接線層之表面層中。
    O:\67\67333-910709.ptc 第15頁
TW089122811A 2000-01-21 2000-10-30 Semiconductor device and its production process TW501201B (en)

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