TW497235B - Circuit board having center-directional package lands and ball grid array package using the circuit board - Google Patents

Circuit board having center-directional package lands and ball grid array package using the circuit board Download PDF

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Publication number
TW497235B
TW497235B TW90115165A TW90115165A TW497235B TW 497235 B TW497235 B TW 497235B TW 90115165 A TW90115165 A TW 90115165A TW 90115165 A TW90115165 A TW 90115165A TW 497235 B TW497235 B TW 497235B
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TW
Taiwan
Prior art keywords
ball
solder
circuit board
solder ball
mounting surface
Prior art date
Application number
TW90115165A
Other languages
English (en)
Inventor
Hyung-Seop Kim
Original Assignee
Samsung Electronics Co Ltd
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Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of TW497235B publication Critical patent/TW497235B/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/114—Pad being close to via, but not surrounding the via
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09281—Layout details of a single conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

497235
發明背景 l.發明範疇 本發明有關半導體封裝之技術，尤其，有關—種電路板 其中知球綷接區直接朝向該板的中心及使用該電路板之 NSMD(非軟焊罩定義）球栅陣列封裝。 2.相關技藝説明
裝 訂
在半導體封裝工業中，對較高性能、更可靠、體積更小 且質更輕1C裝置的需求日漸增加，因此對較小元件的封装 及較高之輸入/輸出插腳數目的要求也就越形增力σ。四列扁 平封装（QFP)與球柵陣列封裝斤(3八）提供大數目之I/O插 腳’符合現代IC技術之需求。爲了可以安置增加I/O插腳的 需要，該四列扁平.封裝技術被迫使用越來越細的引線（lead) 間距’其造成更脆弱 '較薄的引線。因此’該球柵陣列封 裝技術對應付高I/O的需求較有效，而還能使該封裝裝置的 總體積保持較小，並且能使用一較大的間距，使得内連的 設計更加自由。該球柵陣列封裝封装係爲一區域（area)封 裝，其利用整個或是部分的内連装置映罩表面 (footprint)，其焊球材質通常爲一軟焊合金或有時爲其他 金屬。該球柵陣列封裝頗有好處，因爲其可以降低大於^ 分之30的正常引線框塑膠封裝，並使該球間距小於1·〇〇也 米，以具體化該晶片刻度或是晶片大小封装。 在該球栅陣列封裝封裝中，可靠性是相當重要的果題 尤其’是if球與球、焊接區間的，例如性疋極 具重要性。當該焊接點斷掉時，電路徑便斷掉，…果L成 本紙張尺度適用中國國家標竿(CNS) A4規格(210 X 297公釐） 497235 A7 B7
五、發明説明（2 ) 裝置故障的危機。還有，如果在焊接點出現裂痕，在接合 點的電阻便增加，使得裝置的電性變得撲朔迷離。在接合 點的電阻增加，在該信號路徑上產生一個莫須有的直流電 壓降，且可能在RC電路中引起一個充電延遲以及在系統層 面之雜訊。 爲了保持焊球與球焊接區間的強度，例如在美國專利序 號5,796，163中有一個傳統的方法，以一金屬區域環繞介窗 孔等，該等介窗孔以非導電之插梢如環氧樹脂軟焊罩做爲 一球焊接區，來形成焊球點。該插梢介窗孔技術在美國專 利 5,875，1〇2、5,936,848及 5,706，178 中都有討論。 裝 訂
在以上之先前美國專利5,875,102中，每一個介窗孔有— 部分仓1於一軟焊襯墊中以增加該基板的路由空間，及_部 分位於該軟焊襯墊外面以允許自該介窗孔向外釋放氣體 (Gutgassing)。在美國專利5,936,848中所揭露的技術係= 用一插梢介窗孔，而美國專利5,706,178則說明於焊球坪接 區^形成之一介窗孔結構。還有，美國專利5,872,399在焊 球绛接區形成一小凹洞（dimple)，而美國專利6〇28,366於 球绛接區中使用一溝槽，兩者都增加焊球與該球焊接區間 發明總結 本發明之一目標係爲改良焊球與球烊接區 靠性。 f ·、沽的可 本發明之另一目標係爲防 間的焊點上。 止裂痕發生於焊球與球焊接區 5- 五、發明説明（3 ) 爲達到本發明的目標，發明者將注意力集中在球柵陣列 封裝的可靠性大部分與該封裝襯墊的設計有關的事實上。 在視察並分析了焊點裂痕的成因之後，發明者發現裂痕發 生於施應力的方向。發明者發現當一應力施於焊點的方向 如圖2中的前頭方向時，在該焊點中以，A，表示的圈，即該焊 點受應力的啓始部分，最容易產生裂痕。例如，該應力可 以因爲在封裝之可靠性測試時，基板12與該半導體晶片2〇 間熱膨脹係數不匹配而產生，在測試中的熱週期中，封裝 受到熱然後在室溫中冷卻。 根據本發明，一電路板具有一晶片安裝表面，於其中形 成布線圖案，以及一焊球安裝表面，於其中安装有複數個 详球並電内$至該等布線圖纟。該電路板包含複數個球焊 接^，每一個球焊接區分別與該等焊球之一直接相連；由 焊球罩足義之焊球開口區通常沉積於該焊球安裝表面， 並將該軟焊焊接區由該焊球罩曝光；複數個圖案連接裝 置，每一個裝置都連接至對應之一球焊接區；及導電布線 圖案與該等圖案連接裝置鏈接並電内連至該等焊球。複數 個圖案連接裝置被安排朝向該焊球安裝表面之一中心點。 從本發明之一觀點，一球柵陣列封裝包含具有中心方向 性的焊球焊接區類型之該電路板。該球柵陣列封裝爲一 NSMD(非教焊罩定義）之結構，其中該球焊接區的大小小於 該球焊接區開口區域。 以上並其他之特性與好處將於以下參考所附之圖式的詳 細説明中更加清楚明白。重要的是，圖式並沒有按實際的 -6- ^紙張尺度適用中國國家操準(CNS) A4規格(210父297公|) —-- 497235 A7 B7 五、發明説明（4 ) 大小來繪製，而且本發明尚有其他之具體實施例並未—— 説明。 圖式簡單説明 圖1爲一橫剖面視圖，示一球栅陣列封裝及一安裝球柵陣 列封裝之電路板，如本發明之一具體實施例； 圖2爲一部分放大之視圖，示該焊球焊接點與該球柵陣列 封裝中應力所施之方向間的關係； 圖3爲該球柵陣列封裝之一底視圖，示該焊球焊接區圖 案； 圖4爲該球柵陣列封裝之焊球焊接區圖案的部分放大視 圖； 圖5 a與5b分別爲一傳統球柵卩丰列封裝的底視圖與部分放 大圖，用來評量該焊接球焊點的可靠度； 圖6a與6b分別爲另一先前球柵陣列封裝的底視圖與部分 放大圖，用來評量該焊接球焊點的可靠度； 圖7a與7b分別爲另一先前球栅陣列封裝的底視圖與部分 放大圖，用來評量該焊接球焊點的可靠度；及 圖8a與8b分別爲如本發明之球柵陣列封裝的底視圖與部 分放大圖，用來評量該焊接球焊點的可靠度。 較佳具體實施例的詳細説明 圖1示範根據本發明應用之一球柵陣列封裝及該球柵陣列 封裝所安裝之一電路板。圖1中所示之封裝爲一塑膠封裝， 其使用過塑造（over-molding)與打線技術。然而，吾人應 該注意本發明並不受限於此塑膠封裝。對熟知此項技藝之 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 497235 A7 _____ B7 五、發明説明（5 ) 人士而言’本發明可以應用於使用聚合物帶的TAB帶封 裝’及錫錯合金（如百分之10的錫與百分之90的鉛）及一金 屬蓋封裝以及一陶瓷封裝。該球柵陣列封裝裝置1〇包括一 基板12、一半導體晶片20及焊接球25。該基板12爲一 BT(Bismaleimide_Triazine)樹脂基板或是一環氧樹脂玻 璃基板（也稱爲’FR-4,基板）。在基板12之一晶片安裝表面上 佈有一模襯墊14、金屬繞線16及一軟焊罩19，而該基板12 底表面或是焊球安裝表面有一球焊接區18與一軟焊罩19。 孩模觀塾14及金屬繞線16爲以一微影技術所形成之銅質圖 案。當所需求之輸入/輸出（I/O)插腳相當少時，該金屬圖案 16可以只形成於該基板的兩邊。當I/O插腳數高時，該金屬 圖术1 6形成於该基板的内層以及該基板的兩邊。該半導體 晶片2〇以使用~黏附劑22(例如銀環氧樹脂）的方式連附於 S模襯墊14上。該半導體晶片14及金屬繞線16以金屬線24 電内連。晶片安裝表面上之金屬繞線16可以經由該穿孔“ 延伸至孩展表面。從晶片20所產生的熱可以經由該熱介窗 孔17散發。遠球焊接區18被該軟、厚罩19環繞 (C1rcumVented)。以將該焊球等乃置於該球焊接區以上^ 進灯reflow焊接的方式，將焊球等μ坪接於球谭接區^。 此時，一焊球焊接點27以焊球與焊接區間金屬與金屬結點 的方式形成。該半導體晶片20與該金屬繞線16以一封^材 料（encapsulam)如塑膠樹脂26保護，以形成一封裝體。 該球柵陣列強封裝10安裝於一電路板3〇上，例如^ 一包 含一記憶體模組之模組板30，以表面安裝該封裝的^方式二 -8- 本紙張尺度適用中® G標準(CNS) Α4規格(210 X 297公爱厂 ---— ___ _ _
裝 訂 % 497235 A7 B7 五、發明説明（6 ) 使得該焊球25可熔連附至該導電襯墊32。該焊球點27的可 靠度受到該導電襯墊32的設計影響。然而，從半導體封裝 的觀點，該設計的影響不如該焊球焊接區類型的影響（即球 焊接區與導電繞線的設計）大。 圖3爲根據本發明之該球栅陣列封裝之一底視圖，示該焊 球安裝表面。該焊球安裝表面相對晶片安裝表面、在該基 板的對邊。該焊球安裝表面50，除了該球焊接區60外，其 整個表面施以一軟焊罩52。該等球焊接區62在該球焊接開 口區域60之内。該結構稱爲NSMD(非軟焊罩定義）。該等 球焊接區62連帶至該圖案連接部分65。 根據本發明，該焊球焊接區類型的設計使得整個圖案連 接部分65朝向封裝的中心點55。更特定地説/該焊球焊接 區類型的設計係使得該圖案連接部分65位於圖4中所示中心 方向區域B之内。該中心方向區域B具有一等邊三角形的形 狀，具有一底邊與兩斜邊。該底邊爲穿過該球焊接區62中 心的直徑R並垂直於一條連接該封裝底表面50之中心55的 線。兩斜邊爲兩直線C1與C2，分別連接底邊的兩端至該中 心55。該圖案連接部分65和電内連該等球焊接區62與該等 介窗孔68之該金屬布線圖案66形成爲一體。該圖案連接部 分65的寬度W以小於該球焊接區62的直徑R爲較佳。 焊球焊接區以如圖3與4所示的設計，其對施於方向D1、 D2、D3與D4的應力之阻抗、因而使焊接球點的可靠性大 大地增加。 爲了評量不同焊接球點的可靠度，圖5至8示範四種焊球 -9- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 497235 A7 B7 五、發明説明（7 ) 焊接區的類型。 類型1具有如圖5中所示之圖案。此焊球焊接區70是以隨 機的方式安排，並無朝向封裝的中心，而且球焊接區開口 區域76的直徑爲380微米，其小於圖5b中所示之球焊接區 78的大小450微米。此類型稱爲一 SMD(軟焊罩定義）的結 構。第1類型之圖案連接部分74至該介窗孔72的寬度爲250 微米。 第二類爲一NSMD(非軟焊罩定義）的結構，具有一非方法 性之焊球焊接區80，如圖6a與6b中所示，且該球焊接區88 的大小爲270微米，該球焊接區開口區域86的大小爲400微 米，而且，該圖案連接部分84連接至該介窗孔82的寬度爲 75微米。第三類爲一NSMD(非款焊罩定義）的結構，具有 一非方法性之焊球焊接區類型90，如圖7a與7b中所示。且 該球焊接區96的大小爲270微米，該球焊接區開口區域98 的大小爲400微米，而且該圖案連接部分94的寬度爲250微 米。 第四類爲一NSMD(非軟焊罩定義）的結構，具有本發明之 非方法性焊球焊接區類型100，如圖8a與8b所示。該球焊接 ，區62的大小爲270微米，該球焊接區開口區域60的大小爲 400微米，而且該圖案連接部分65的寬度爲75微米。 在對以上所列之四類型的球柵陣列封裝進行熱循環，從 攝氏-25度至攝氏125度，發現在該焊球焊接點内的裂痕， 如示於以下之表1中。該熱循環進行的時間爲30分鐘，且該 球柵睁列封裝爲一多晶片封裝，其中的晶片積有同步 -10- 本紙張尺度適用中國國家標準(CNS) A4規格（210 X 297公釐） 497235 A7 B7 五、發明説明（8 ) (synchronous)動態隨機存取記憶體（DRAM)及一 NOR型之 閃速記憶體。 取樣數 TC300 TC 700 TC 1000 TC 1200 TC 1400 TC 1600 類型1 180 0 0 0 0 2 1 類型2 180 0 評量失敗因爲所有的H奢都姑 障 類型3 180 0 0 0 0 3 7 類型4 180 0 0 0 0 0 0 <表1>在焊球焊接區的裂痕 比較1，3，4類型的結果，發現在SMD結構中的焊球焊接 區的可靠度較在NSMD結構中的爲低。還有，從類型1與？ 的結果中可看出圖案連接部分對該焊球焊接區的可靠度具 有相當大的影響。 在该S M D結構中’该爭焊球被連附於該坪球、焊接區的平 坦表面上，而當施一預先決定量之應力時，裂痕產生於該 焊球與 '焊接區間相介面的表面。該裂痕在裂痕開始之後進 行地非常快。從另一方面來看，因爲該焊接點形成的形狀 是使該焊球包圍在該球焊接區，該應力被施在該NSMD結 構的焊接區的兩邊與上表面，且因此對應力的阻抗高於該 SMD結構。 第3類型通常爲一 N S M D結構，然而當從施於該焊球接區 的取大應力的方向看來時’其與SMD結構並無不同，因爲 該圖案連接部分的寬度爲250微米，與該球焊接區大小27〇 微米差不多。因此，比較類型1與3，該焊球焊接點在當該 -11 - I紙張尺度通用+國國家標準(CNS) Α4規格(210X297公釐) '"' ------^— 497235 A7 B7 五、發明説明（9 ) 圖案連接部分較小時較可靠。 同時，在類型2中，裂痕發生在TC700中的所有取樣中， 如以下之表2所示，且因此可以評量焊球焊接點精確之可靠 度。 當進行從攝氏-25度至攝氏125度的熱循環時，以上四類 的封裝都具有直徑爲0.4毫米、圖案式裂痕發生，如表2所 示。 取樣數 TC300 TC700 TC 1000 TC 1200 TC 1400 TC 1600 類型1 180 0 0 0 0 0 0 類型2 180 51 129 類型3 180 0 0 0 0 0 0 類型4 180 0 15 21 7 8 8 <表2>圖案式裂痕 在此，吾人應注意本發明之第四類的圖案裂痕全都位於 該焊球焊接區在圖8a中註爲圓圈100A之處。該焊接區圖案 100A並不具有圖案連接部分65直接朝向該封裝的中心，其 與其餘之圖案100不同。 · 當該焊球焊接區類型1與4應用不是該以上之多晶片之其 他封裝時，焊球焊接區裂痕發生如表3所示。 -12- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 497235 A7 B7 五、發明説明（1〇 ) 取樣數 TC300 TC 800 TC 1000 TC 1200 TC 1500 TC 1800 類型1 180 0 1 0 126 一 類型4 180 0 0 0 0 0 0 <表3 >烊球焊接點裂痕 焊球的材料與該焊球焊接點可靠度之間的關係示於以下 的表4中。在此，材料1代表具有分另U爲百分之03與百分之 3 7的錫與鉛之共晶焊球，而材料2加了銅。 取樣數 TC300 TC 800 TC 1000 TC 1200 TC 1500 TC 1800 材料1 180 0 1 20 瓣 材料2 180 0 0 0 0 2 1 〈表4> 如表4中所示，當加入銅時，該焊球焊接點比較可靠。 在以上本發明之較佳具體實施例中所揭露的圖式與規格 中，雖然使用特定的字眼，但是其含意都只爲一般性及敘 述性，並不是用來限制於以下申請專利的範圍。 -13- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐）

Claims (1)

  1. 497235 A8 R8 C8 Π8 f、申請專利範圍 1. 一種球栅陣列封裝，其包括一電路板，該電路板具有一 晶片安裝表面，，於其中安裝一半導體晶片·並形成布線圖 案，及一焊球安裝表面，安裝複數個焊球電内連至該等 布線圖案，該電路板包含： 複數個球焊接區，每一個球焊接區直接與對應焊球之 一相連； 由一焊球罩定義之焊球開口區，其通常沉積於該焊球 安裝表面上，並由該焊球罩曝露出該焊球焊接區； 複數個圖案連接裝置，每一個裝置都連接至對應之一 球焊接區；及 導電布線圖案，與該等圖案連接裝置鏈接，並電内連 至該等焊球， 其中該等複數個圖案連接裝置被安排朝向該焊球安裝 表面之一中心點。 2·如申請專利範圍第1項之球柵陣列封裝，其中該球焊接開 口區大於該球焊接區。 3 ·如申請專利範圍第1或第2項之球柵陣列封裝，其中該等 圖案連接裝置的寬度小於該球焊接區的大小。 4.如申請專利範圍第1或第2項之球柵陣列封裝，其中每一 個圖案連接部分，其與對應之球焊接區連接於一朝向中 心之區域、於每一個圖案連接部分都朝向該焊球安裝表 面之中心之處。 5 ·如申請專利範圍第1或第2項之球柵陣列封裝，其中該焊 球的組成爲含銅之錫錯合金。 -14- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 訂---------線· 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 497235 A8 B8 C8 D8 六、申請專利範圍 6. —種電路板，有一半導體晶片安裝於其上，並具有一晶 片安裝表面，於其中形成布線圖案，及一焊球安裝表 面，於其中安裝複數個焊球並電内連至該等布線圖案， 該電路板包含·· 複數個球焊接區，每一個球焊接區直接與對應之複數 焊球之一相連； 由一焊球罩定義之焊球開口區，其通常沉積於該焊球 安裝表面上，並由該焊球罩曝露出該焊球焊接區； 複數個圖案連接裝置，每一個裝置都連接至對應之一 球焊接區；及 導電布線圖案，與該等圖案連接裝置鏈接，並電内連 至該等焊球， 其中該等複數個圖案連接裝置被安排朝向該焊球安裝 表面之一中心點。 7. 如申請專利範圍第6項之電路板，其中該焊球開口區大於 該球焊接區的大小。 8. 如申請專利範圍第6或第7項之電路板，其中該圖案連接 裝置的寬度小於該球焊接區的大小。 9. 如申請專利範圍第6或第7項之電路板，其中每一個圖案 連接部分，其與對應之一球焊接區連接於一朝向中心之 區域、於每一個圖案連接部分都朝向該焊球安裝表面之 中心之處。 -15- 本紙張尺度適用中國國家標準（CNS)A4規格（21〇χ 297公t ) .---.---------------訂---------線—AWI (請先閱讀背面之注意事項再填寫本頁)
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