TW497189B - Manufacturing method for semiconductor device - Google Patents

Abstract

The object of the present invention is to improve the yield rate of the semiconductor device. The solution is that, in the manufacturing process of the semiconductor device, on the surface of the back of the semiconductor wafer, it provides a process for forming labels on the back area of the semiconductor wafer corresponding to the forming areas for each die, respectively, which is after the process of forming a plurality of die forming areas with circuits thereon and before the process of forming the protruded electrodes on the forming areas for each die.

Description

497189 A7 _ B7 V. Description of the invention (1) (Technical field to which the invention belongs) The present invention relates to the manufacturing technology of semiconductor devices, and in particular, to relocating electrode pads in a semiconductor wafer state, and forming protruding electrodes on the reconfigured electrode pads. Effective technology for semiconductor device manufacturing. (Know-how) Semiconductor devices assembled in small electronic devices such as mobile phones, portable information processing terminals, and portable personal computers need to be thin, small, and multi-terminal. As a semiconductor device to which such a requirement is applied, a semiconductor device called C S P (Chip Sue Package) is developed. Various types of such CS P semiconductor devices have been proposed and commercialized. In recent years, for example, the Nikkei Microelectronic Components (August 1998, page 4 to page 71) issued by Nikkei BP, describes the wafer process (front-end process) and the packaging process (back-end process). ) A new CSP type semiconductor device (hereinafter referred to as a wafer-level CSP type semiconductor device) manufactured by integrated manufacturing technology was developed. The wafer-level CSP-type semiconductor device has a planar size that is substantially the same as that of the semiconductor wafer, and a CSP-type semiconductor device (hereinafter referred to as a wafer-level CSP-type semiconductor) cut out of the semiconductor wafer and packaged and manufactured. Device) compared to achieve miniaturization and cost reduction. The wafer-level CSP type semiconductor device mainly includes a semiconductor wafer forming a circuit, and a circuit forming surface (a main surface) of a front surface and a back surface of the semiconductor wafer (the main surface facing each other and the other main surface). The pad rearrangement layer formed above, and placed on the pad rearrangement layer as an outer-II ϋ ϋ II ^ IIIIIII (Please read the precautions on the back before filling this page)

—I --- ^ Order --------- line II Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The paper size applies to the Chinese National Standard (CNS) A4 (210 X 297 mm) -4- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 497189 A7 B7 V. Description of the invention) The protruding electrode of the terminal for connection. The main structure of a semiconductor wafer includes: a semiconductor substrate; a plurality of insulating layers and wiring layers on a circuit forming surface (a main surface) of the front and back surfaces of the semiconductor substrate (a main surface and the other main surface facing each other) A multilayer wiring layer; and a surface protection film formed like covering the multilayer wiring layer. An electrode pad is formed on the uppermost wiring layer of the multilayer wiring layer, and a joint opening is formed on the surface protective film to expose the electrode pad. The pad re-arrangement layer is a layer for forming electrode pads having a larger arrangement pitch than the electrode pads of the semiconductor wafer. The electrode pads of the pad rearrangement layer are electrically connected to the corresponding electrode pads of the semiconductor wafer, and are arranged at the same arrangement pitch as that of the electrode pads of the mounting substrate on which the semiconductor device is mounted. The projected electrode movement vector search area is on the electrode pad of the pad reconfiguration layer, and is electrically and mechanically connected. (Problems to be Solved by the Invention) The present inventors found that the development of a wafer-level c S P type semiconductor device has the following problems. (1) The wafer-level CMOS semiconductor device is mounted in a state where the protruding electrodes are positioned on the mounting surface of the mounting substrate. Therefore, wafer-level c S P type semiconductor devices need to form identification marks such as product name, company name, product type, and manufacturing lot number on the back side of the semiconductor wafer. The formation of the identification mark is better than before the semiconductor wafer is divided into each wafer formation area, that is, in the state of the semiconductor wafer. The reason is that after the semiconductor wafer is divided into each wafer forming region, the processing unit and wafer state are hundreds of times compared, and the processing is complicated, which will affect the quality and cost. This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -5------------------- 4 ----- Order --- ------ Line '(I first read the note on f? Matters and then fill out this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 497189 A7 B7 V. Description of the invention (β) Identification under wafer status The formation of the mark can be a semiconductor crystal corresponding to a plurality of wafer formation areas formed on a circuit formation surface (a main surface) of a front surface and a back surface of the semiconductor wafer (one main surface and the other main surface facing each other). Recognition marks are formed on the back side (the other main side) of the circle. However, the formation of the identification mark of the wafer state is performed by sucking and fixing the semiconductor wafer on the adsorption platform of the mark forming device. Therefore, when the identification mark is formed after the protrusion electrode is formed, the protrusion electrode is easily deformed and becomes a wafer-level CS P type. The main reason for the decrease in the yield of semiconductor devices. Also, the back surface of the semiconductor wafer is uneven due to the unevenness of the protruding electrode. It is possible to use a non-contact type such as a direct-printing mark forming device or a non-contact type such as an inkjet type marking forming device. Defective identification mark has occurred, resulting in a decrease in the yield of wafer-level c S P type semiconductor devices. (2) The semiconductor wafer tends to have a larger diameter in order to increase the yield of the semiconductor wafer. The semiconductor wafer is also easily deformed along with it. Therefore, the larger the diameter of the semiconductor wafer, the thicker the semiconductor wafer. However, the thickness of semiconductor devices that are assembled in small electronic devices such as mobile phones, portable information processing terminals, and portable personal computers must be reduced. Therefore, after the wafer front-end processing is applied, the back surface of the semiconductor wafer needs to be honed to be thinned, that is, the back surface honing process is performed. However, the back surface cutting process is performed by sucking and fixing the semiconductor wafer on the suction platform of the cutting device. Therefore, when the back surface shaving process is performed after the bump electrodes are formed, the unevenness of the bump electrodes affects the thickness of the semiconductor wafer. When the thickness of the semiconductor wafer is not uniform, the slicing process of dividing the semiconductor wafer into individual wafer formation regions is likely to cause cracks in the semiconductor wafer and reduce the yield of wafer-level C S P type semiconductor devices. This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) -6--I ^ 1 ^ 1 ϋ 1 ϋ ϋ. Ϋ ϋ 1¾ ^ 1 ϋ JW Order ---------线 — ^ Γ ---- V (Please read the precautions on the t side before filling out this page) 497189 A7 --B7 V. Description of the invention (4) (3) After forming the identification mark on the back side of the semiconductor wafer, perform the back During the cutting process, the stress is concentrated on the unevenness of the identification mark, and the semiconductor wafer capacity (please read the precautions on the back before filling this page) is prone to cracks, which leads to a reduction in the yield of wafer-level CSP semiconductor devices. (4) As a semiconductor device with a built-in memory circuit, such as DRAM (Dynamic Random Access Memory), SRAM (S Static Random Access Memory), it can distinguish some good memories, but when used, it is used to transfer each block of the memory circuit. Good or bad information (partial status: block part, address part, I / 〇 part), a lot of information needs to be memorized. The method of memory information known to semiconductor chips has a limited amount of information, and a method of classifying memory information according to the order or type of the fixtures in parallel can be considered. However, the feature information is managed side by side in accordance with the fixture. When the sequence on the fixture is changed due to negligence, the information will be mistransmitted, causing manufacturing problems such as lower yield. It is realistic to consider the number of varieties when preparing the jig as part of the classification. In other words, the information is equivalent to the loss after leaving the jig. In addition, the information memory carried out by the chip-level C S P semiconductor device only includes the manufacturing information of semiconductor chips. It is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and does not include some of the information on the utilization of good products. The information that can be physically stored is also limited. The object of the present invention is to provide a technology that can improve the yield of semiconductor devices. Another object of the present invention is to provide a technology that can use some good products stably and safely. The objects and features of the present invention can be understood from the following description. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -7-Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 497189 A7 --B7 V. Description of the invention @) (Method for solving the problem) The representativeness of the invention is briefly explained as follows. (1) In the method of manufacturing a semiconductor device, after the process of forming a plurality of wafer formation areas with a circuit system on the surface of the front and back surfaces of the semiconductor wafer, the process of forming a bump electrode on each of the above wafer formation areas is 0U. A process of forming an identification mark in a region on the back side of the semiconductor wafer corresponding to each of the wafer formation regions is provided. (2) In the method of manufacturing a semiconductor device, after the process of forming a plurality of wafer formation areas with a circuit system on the surface of the front and back surfaces of the semiconductor wafer, the process of forming a protruding electrode on each of the wafer formation areas is provided. The process of cutting the back of the semiconductor wafer. (3) In the method for manufacturing a semiconductor device according to the above (2), after the process of cutting the back surface of the semiconductor wafer, a process of forming an identification mark on the back side region of the semiconductor wafer corresponding to each of the wafer formation regions is provided. . (4) The method for manufacturing a semiconductor device includes: after the process of forming a plurality of wafer formation regions with circuits on the surface of the front and back surfaces of the semiconductor wafer, measuring the above before the semiconductor wafer is divided into the respective wafer formation regions; Engineering of electrical characteristics of circuits in each wafer formation region; and forming identification marks including characteristic information such as electrical characteristics of the above circuits obtained by the measurement process on the back side of the semiconductor wafer corresponding to each of the wafer formation regions. engineering. According to the above method (1), when an identification mark is formed on the back side of the semiconductor wafer, no protruding electrode is formed on the surface side of the semiconductor wafer. The size of the paper is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm). ) -8--I -—- II ϋ ϋ ϋ n ϋ. ^ 1 * -ϋ IIJ · ϋ ϋ one by one " J ϋ ϋ ϋ I · ϋ ϋ · ϋ II ϋ ^ 1 IL · ϋ-(Please first Read the notes on the t 'side and fill in this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperatives printed 497189 A7 _ B7 V. Description of the invention φ) The adsorption platform of the forming device adsorbs and fixes a semiconductor wafer. prevent. Further, defective identification marks due to unevenness on the back surface of the semiconductor wafer caused by unevenness of the protruding electrode can be prevented. As a result, the yield of the semiconductor device can be improved. According to the above method (2), when the back surface of the semiconductor wafer is chipped, no protruding electrode is formed on the surface side of the semiconductor wafer, and unevenness of the semiconductor wafer thickness caused by the unevenness of the protruding electrode can be prevented. As a result, in the slicing process in which a semiconductor wafer is divided into individual wafer formation regions, cracks in the semiconductor wafer caused by uneven thickness can be prevented, and the yield of semiconductor devices can be improved. According to the above method (3), when the back surface of the semiconductor wafer is machined, no identification mark is formed on the back side of the semiconductor wafer, so that the semiconductor wafer crack caused by the stress concentrated on the unevenness of the identification mark can be prevented. As a result, the yield of the semiconductor device can be improved. According to the above method (4), part of the good-quality information management semiconductor device can be added, and it will not be affected by unstable conditions such as the position in the fixture, and stable and safe semiconductor device management can be performed. In addition, the semiconductor device can be processed independently, and the convenience when used as a memory module element can be improved. (Embodiment of the invention) The following describes the configuration of an embodiment of a wafer-level CMOS semiconductor device to which the present invention is applied. In the drawings for describing the embodiment, those having the same function are assigned the same reference numerals, and redundant descriptions are omitted. FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention. Figure 2 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -9--------- I -------- 11 — IJ order · ---- --- ^^ J (Please read the phonetic on the back? Matters before filling out this page) -I ϋ it ϋ ϋ ϋ 1 ϋ I II H ϋ Printed by the Intellectual Property Bureau Staff Consumer Cooperative of the Ministry of Economic Affairs 497189 A7 ---- -B7 V. Description of the invention (7) is a bottom view of the above semiconductor device. FIG. 3 is a cross-sectional view of an important part of the semiconductor device, and FIG. 4 is an enlarged cross-sectional view of a part of FIG. 3. As shown in Figs. 1 and 2, the plane of the wafer-level cS P-type semiconductor device 20 of this embodiment is formed in a square shape, and in this embodiment, for example, a rectangle of 5 mm x 8 mm is formed. The semiconductor device 20, as shown in FIG. 3, mainly includes a semiconductor wafer 15 and a surface (a main surface and another main surface opposite to each other) on the front and rear surfaces of the semiconductor wafer 15 (a The main pad) has a pad re-arrangement layer 16 formed on the circuit formation surface 15 X, and a protruding electrode 11 disposed on the pad re-arrangement layer 16 as an external connection terminal. The planar dimensions of the semiconductor wafer 15 and the semiconductor device 20 are formed in the same planar dimension. As shown in FIG. 3 and FIG. 4, the semiconductor wafer 15 mainly includes a semiconductor substrate 1 A and surfaces on the front and back surfaces of the semiconductor substrate 1 a (the main surface and the other main surface facing each other). A multi-layered wiring layer 2 having a plurality of layers of an insulating layer and a wiring layer laminated on the circuit formation surface (on one main surface), and a surface protective film 3 formed to cover the multilayered wiring layer 2. The semiconductor substrate 1 A is formed of, for example, single crystal silicon, the insulating layer of the multilayer wiring layer 2 is formed of, for example, a silicon oxide film, the wiring layer of the multilayer wiring layer 2 is formed of, for example, an aluminum film or an aluminum alloy film, and the surface protective film 3 is formed of, for example, nitride A silicon film is formed. A plurality of electrode pads 2A are formed at the central portion of the circuit formation surface of the semiconductor wafer 15 along the longitudinal direction. Most of the electrode pads 2A form the uppermost wiring layer among the multilayer wiring layers 2 of the semiconductor wafer 15 respectively. The uppermost wiring layer has been formed on the upper surface of the protective film 3, which is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) at this paper size. -10- ----------- -------- r --- ^ Order --------- Line Win (Please read the phonetic on f *? Matters before filling out this page) 497189 Employee Consumer Cooperatives, Bureau of Intellectual Property, Ministry of Economic Affairs Printed A7 B7 V. Description of the invention (8) The surface protection film 3 forms an opening 3 A that exposes the surface of the electrode pad 2 A (see FIG. 4). The planar shape of most electrode pads 2 A is, for example, a quadrangular shape of 2 5 V m X 2 5 // m. In addition, most of the electrode pads 2 A are arranged at a pitch of about 8 5 // m, for example. A semiconductor circuit 15 is formed with, for example, 6 4 MB (million bits) D R AM as a memory circuit, and the memory array of the D R AM is composed of, for example, 4 blocks. As shown in FIG. 3 and FIG. 4, the pad rearrangement layer 16 mainly includes an insulating layer 6 formed on the surface protection film 3, a majority of wirings 7 extending over the insulation layer 6, and a plurality of wirings 7 covering the wirings. An insulating layer 8 on the insulating layer 6 and a plurality of detection electrode pads 9 A and a plurality of electrode pads 9 B formed on the insulating layer 8. One end of the plurality of wirings 7 is electrically and mechanically connected to the plurality of electrode pads 2 A through an opening 6 A formed in the insulating layer 6 and an opening 3 A formed in the surface protective film 3. Of most of the wirings 7, about half of the other end of the wiring 7 is led out of one of the two long sides of the opposite side of the semiconductor device 20, and the other end of the other wiring 7 is led out of the opposite side 2 of the semiconductor device 20 The other long side of the long side (see FIG. 2). The majority of the electrode pads 9A for detection are electrically and mechanically connected to one end side of the plurality of wirings 7 through an opening 8A (see FIG. 4) formed in the insulating layer 8. The plurality of electrode pads 9 B are electrically and mechanically connected to one end side of the plurality of wirings 7 through an opening 8 B (see FIG. 3) formed in the insulating layer 8. The electrode pads 9 A and 9 B for detection are formed in the same layer. In addition, the detection electrode pad 9A may not be formed. The size of this paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) -11- ^ 1 ϋ e ^ i Βϋ — 1 n I ϋ. ^ 1 ϋ II J1 ϋ one by one, I 1_1 Βϋ I ϋϋ ϋ ϋ tb ϋ ϋ I τι ϋ ϋ 1 · ϋ 1 ^ 1-^ 1 H ^ 1 ϋ ϋ ^ 1 ^ 1-^ 1-(Please read the note on the back? Matters before filling out this page) Bureau of Intellectual Property, Ministry of Economic Affairs Printed by the employee consumer cooperative 497189 A7 B7 V. Description of the invention) Most of the electrode pads 9 B are electrically and mechanically connected to the pad rearrangement layer 16 as a plurality of protruding electrodes 1 1 arranged as terminals for external connection. Most of the protruding electrodes 11 are formed of a metal material composed of, for example, 63 wt% lead (Pb) to 37 wt% tin (Sη). The pad rearrangement layer 16 is a rearranged layer of electrode pads 2 Α having a larger pitch than the semiconductor pads 1 5 of the semiconductor wafer, and the electrode pads 9 B of the rearrangement layer 16. The arrangement pitch is the same as the arrangement pitch of the electrode pads of the mounting substrate mounted on the semiconductor device 20. Most electrode pads 9 B are not limited to this. For example, as shown in FIG. The two long sides are arranged in two rows along the long side. The electrode pads 9 B of each row are arranged at a pitch of about 0.5 mm, for example. The planar shape of most of the electrode pads 9 B is formed, for example, in a circular shape with a diameter of about 0.25 mm. Most of the protruding electrodes 11 can be formed in a spherical shape, for example, and the height (the distance from the insulating layer 8 to the topmost portion) is, for example, about 0.15 mm. In addition, FIG. 2 shows only 22 protruding electrodes 11 for easy viewing, but a 64 MB DRAM has about 50 to 60 electrode pads 9 B and protruding electrodes 11. The insulation layer 6 and the insulation layer 8 in the pad rearrangement layer 16 are used to reduce the stress caused by the thermal expansion difference between the mounting substrate 11 and the mounting substrate 11 after the semiconductor device 20 is mounted on the mounting substrate. The film or the oxidizing gas is formed of a material having a relatively low elastic modulus, and is formed at a thickness thicker than that of the surface protective film 3. In this embodiment, the insulating layer 6 and the insulating layer 8 are formed of, for example, a polyimide resin, and the insulating layer 6 is, for example, about 5 to 1 〇 0 vm thick. Mm) -12 ^-! 黻 _! (Please read the notes on the back before filling this page) -ϋ

Order --------- line J 497189 A7 V. Description of the invention (10) Degree formation 'The insulating layer 8 is also formed, for example, at a thickness of about 5-1 0 0 // m. The wiring 7 is formed of, for example, a copper film having high electrical conductivity. The electrode pad 9 B is not limited to this, but in order to ensure the wettability of the protruding electrode 11 when it is formed, it can be printed by, for example, an alloy consisting of Cr 旲, 72a t% Ni—28a t% Cu. A hafnium-made, gold (Au) film is sequentially deposited on the electrode 11. It is hardly formed as shown in FIG. 3 when the semiconductor surface is formed, and the semiconductor surface is formed as a mask. , Can be suppressed as shown in Figure 1, mark identification mark 1 3. Information for identification mark, for example, it is formed by the mark revealing information such as product code, etc. The status of the inherent information of the two-dimensional code tag device 2 that recognizes a lot of information is divided into states. Block part, address record 1 2, identification mark 1 3. The laser marking method is formed, and the laser mark irradiates the laser light so that the laser light irradiates the marking method. No pre-treatment of the mark formation is required. The identification after the formation of the mark is as follows, and the body device 20 is manufactured according to FIGS. 5 to 2. The layered film is formed and diffuses into the protrusions. The back surface layer 10 of the wafer 15 is formed. The marking resin is formed. The epoxy layer 10 is formed of the formation layer 10 of the epoxy resin layer 10, which is formed by a name, a company name, and a brand mark 13. In the part of the identification target such as DRA M, the I /, 0 part is based on the marking notation of the process, and the part is fused to form the target sweeping process or the target mark is not easy to destroy.突 1 5 Υ Forms a layer of thermal hard peeling. Identify the target semiconductor type, make a small area (1 3 points, good product), and other process formation area records to form a record, cover the back 10 to instantiate the resin and record 12 and create a batch number in the wafer. Record semiconducting information (Ministry. In the process of identification, the field surface method is used. The laser-grade dry cs P type semiconducting paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -13 -n 11 ϋ n ϋ ΙΊ n I ijw ϋ ϋ Bi-i ϋ I l 11 I ϋ ϋ I (Please read the note on the back? Matters before filling out this page) 497189 A7 Printed and manufactured by the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperative Explained Flow Wafer Plan View 'Circular Plan View and Reconfiguration Engineering Description Wafer backing, Figure 12 is a view showing the important part of the cross-section manufacturing equipment, Figure 15, Figure 16 and the plan view of the circle and A plan view of an important part of a semiconductor wafer. Prepare, for example, about 7 semiconductor substrates. Circle 1 is applied to the surface of the semiconductor wafer 1 (a circuit-forming surface with a forming region 4 is a circuit forming surface separated from each other). , Electrode pad 2 process map Figure 7 and part of the semi-conducted semiconductor engineering description form a layer diagram. Figure 1 is a cross-sectional view of the important part of the important part of the figure 17 mark. Figure 5. Invention Description (11) Figure 5 It is a semiconductor wafer used for semiconductor processing for semiconductor device manufacturing, and FIG. 10 is a partial cross-sectional view of an electrode pad. FIG. 11 is an important part of a wafer. Bottom view of the semiconductor wafer used in the manufacturing process for the detection of semiconductor probes. Bottom view of the semiconductor wafer used in the slanting process. Semiconductor crystals used in the engineering description. A semiconductor wafer made of silicon (Second, the semiconductor crystal is shown in Figs. 7 and 8 on one main surface and the other main surface) 1 X, and a region 4 is formed in a row and column shape. Most of the wafers 1 have a line The area 5 is arranged in 4, which is a front view of a semiconductor wafer 1-body component, a multilayer wiring layer 2 6-series semiconductor 8-series wafer, FIG. 9 important semiconductor wafer formation process 3 series semiconductor, FIG. 1 4 series engineering The cross-section view of the electrode formation is shown in the figure, and the cross-section view of the figure is shown in Figure 20. The system is a single crystal with a thickness of 2 5 // m. The engineering process before (A), the surface of the surface (the main surface opposite to each other). Most of the wafers forming the surface DRA M are cut through the semiconductor wafer. Most of the wafers are formed in a region 1 X, which respectively form a semiconductor A, a surface protection film 3, and 丨! (This page) [Order --------- line «2M scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -14 497189 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of Invention (12) Open □ 3 A.

Secondly, a pad re-arrangement layer 16 (B) is formed in each wafer formation area 4. Specifically, first, an insulating layer made of, for example, polyimide resin is formed on the surface protection film 3 by a spin coating method. 6. The insulating layer 6 is formed, for example, at a thickness of about 5 // m. Thereafter, an opening 6 A is formed in the insulating layer 6 so that the surface of the electrode pad 2 A is exposed. The engineering formula so far is shown in Figure 9. After that, a conductive film of a copper film is formed on the insulating layer 6 including the opening 6 A by a low-voltage C V D (Chemical Vapor Deposition) method or a sputtering method. Thereafter, the copper film is patterned to form the wiring 7. After that, an insulating layer 8 made of, for example, polyimide resin is formed on the insulating layer .6 including the wiring 7 by spin coating. The insulating layer 8 is formed, for example, at a thickness of about 5 m. Thereafter, an opening 8A is formed in the insulating layer 8 to expose one end side of the wiring 7 and an opening 8B is exposed to the other end side of the wiring 7. Thereafter, a laminated film such as a Cr film, an alloy film composed of 72a t% Ni-28a t% Cu, and a gold (Au) film is sequentially formed on the insulating layer 8 including the openings 8A and 8B. Thereafter, the laminated film is patterned to form the electrode pads 9 A for detection and the electrode pads 9 B. In this way, at the same time when the pad re-arrangement layer 16 is formed, an electrode pad 9 B having an arrangement pitch larger than that of the electrode pad 2 A is formed. The engineering formula so far is shown in FIG. 100, and the back surface 1 Y of the semiconductor wafer 1 is chipped as shown in FIG. 11 to be thinned (C). In this embodiment, the thickness of the semiconductor wafer 1 is chipped to, for example, approximately 4 0 0 β m. In this project, the adsorption platform of the semiconductor wafer 1 on the cutting device is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) at this paper scale. -15----------- I -------- r--1 Order ----- 1 --- (Please read the notes on the back before filling this page) 497189

V. Description of the invention (13) The employee's cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the circuit formation surface 1 on the X side in a state of adsorption and fixing on the adsorption platform, but because the circuit formation surface 1 of the semiconductor wafer 1 did not form a protruding electrode 1 1 Therefore, the unevenness of the thickness of the semiconductor wafer 1 caused by the unevenness of the protruding electrode 11 can be prevented. In this process, when the back surface 1 of the semiconductor wafer 1 is γ-cleaved, because the identification marks 1 2 and 1 3 are not formed on the back surface 1 γ side of the semiconductor wafer 1, stress is concentrated on the irregularities of the identification marks 1 2, 1 3. The occurrence of cracks in the semiconductor wafer 1 can be prevented. Thereafter, as shown in FIG. 12, a mark formation layer 10 (D) is formed on the back surface 1 γ of the semiconductor wafer 1 so as to cover the back surface 1 Y. The mark-forming layer 1.0 of this embodiment is not limited to this. For example, a thermosetting resin in which epoxy resin is added with carbon and an organic solvent is formed on the back surface 1 Y of the semiconductor wafer 1 by a spin coating method, and thereafter, It is also possible to harden the thermosetting resin by heat treatment. In this process, the 'semiconductor wafer 1 is attached to the adsorption platform of the film-forming device by positioning the circuit formation surface 1 on the X side and fixed to the adsorption platform, but the circuit formation of the semiconductor wafer 1 Since the protruding electrode 11 is not formed on the X side of the surface 1, the mark forming layer 10 can be formed without being affected by the unevenness of the protruding electrode 11. In addition, the mark forming layer 10 'may be bonded to the back surface 1 Y of the semiconductor wafer 1 by heat-pressing a resin film made of an epoxy-based resin with carbon and a thermosetting resin. In this case, the mark formation layer 10 can be formed without being affected by the unevenness of the bump electrode 11. Thereafter, the semiconductor manufacturing apparatus 300A of FIG. 13 is used for probe detection (E) and mark formation (F). Semiconductor manufacturing equipment 3 〇 A -----------, order --------- line '(Please read the precautions on the back before filling out this (Page) This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) -16- Printed by the Employees ’Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 497189 A7 V. Description of the invention (14) Preparation of the probe detection unit 3 1. Mark forming part 3 2. Loading part 3 3. Buffer part 3 4. Unloading part 35. The loading section 3 3 supplies the semiconductor wafer 1 to the probe detection section 31. The buffer portion 34 is configured to store the processed semiconductor wafer 1 by the probe detection portion 31 and supply the stored semiconductor wafer to the mark forming portion 32. The unloading section 35 is used to store the semiconductor wafer 1 processed by the mark forming section 32. In the semiconductor manufacturing apparatus 3 0 A of this embodiment, it is not necessary to form a mark on the back side of the semiconductor wafer 1 in a reversed state of the semiconductor wafer 1 processed by the probe detection section 31. The probe detection (E) is to first fix and fix the semiconductor wafer 1 supplied from the loading section 3 3 to the suction platform 3 1 A. The adsorption and fixation of the semiconductor wafer 1 is performed with the back surface 1 Y of the semiconductor wafer 1 positioned on the adsorption platform 3 1 A. Suction platform 3 1A is a structure that can move in the X-Y direction (plane direction) and Z direction (up-down direction). The probe card 36 is fixed and arranged on the support table 31B above the adsorption platform 31A. After that, as shown in FIG. 14, the adsorption platform 3 1 A is raised to bring the semiconductor wafer 1 close to the probe card 36, and after positioning the positions of the semiconductor wafer 1 and the probe card 36, the wafer formation area of the semiconductor wafer 1 is formed. The electrode pad 4 for detection 9 A contacts the probe 3 6 A of the probe card 36. After that, the electrical characteristics of the circuit of each chip forming area 4 are connected to the probe 3 6 A of the probe card 36. The purple detector measures the characteristic information such as the electrical characteristic results of each circuit and the position information of each chip formation area 4 in the information storage device of the detector. According to this process, electrical characteristics such as good products, defective products, high-quality products, and operating frequency are judged for each wafer formation area 4. The semiconductor wafer that has been tested by the probe 1 is stored in the buffer section 3 4 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -17- ϋ i · — I ϋ ϋ ϋ ϋ ϋ ϋ ϋ ϋ ϋ ϋ ϋ-J- ϋ ϋ IV 1 ^ ϋ n H ϋ I ϋ ϋ 1 I ϋ ϋ ϋ .1- ϋ ϋ ϋ η ϋ ϋ I- ^ 1 1 · I ϋ ϋ ϋ I ϋ ^ I _ (Please first Read the notes on the back and fill in this page) 497189 A7 _ B7 V. Description of the invention (15) 'After' is provided to the mark forming section 32. At this time, the supply of the mark forming portion 32 of the semiconductor wafer 1 with the characteristic information and position information of each wafer forming region 4 of the semiconductor wafer 1 is transmitted to the mark forming portion 32. The mark formation (F) is to first fix and fix the semiconductor wafer 1 supplied from the buffer portion 34 to the suction platform 3 2 A. The adsorption and fixing of the semiconductor wafer 1 is performed with the circuit formation surface 1 of the semiconductor wafer 1 positioned at the adsorption platform 3 2 A. The adsorption platform 3 2 A is the same as the adsorption platform 3 1 A, which is X — γ. Possible configurations for moving in the z-direction and z-direction. A laser oscillator 3 2 B and a meandering lens 3 2 D are arranged below the suction platform 3 2 A. Thereafter, the position information of each wafer formation area 4 is transformed into the position coordinates in the back surface of the semiconductor wafer 1 according to the position coordinates in the circuit formation surface 1 X of the semiconductor wafer 1, and the positions of each wafer formation area 4 are converted according to the position coordinates. The poor information is shown in Fig. 15 and is not in the Y-side area of the back surface 1 of the semiconductor wafer 1 corresponding to each wafer formation area 4. The laser marking method is used to form characteristic information including the electrical characteristics of each circuit obtained by the probe detection. Identification mark 1 3. In addition, on the Y 1 side of the back surface 1 of the semiconductor wafer 1 corresponding to each wafer formation area 4, laser marking is used to form information common to one semiconductor wafer 1 such as product name, company name, variety, manufacturing lot number, etc. Mark 1 2. The identification mark 1 3 is formed by a two-dimensional code mark with a small area and a large amount of information. The identification mark 1 2 and the identification mark 1 3 are formed by a laser marking method, as shown in FIG. 1 〇 The surface is irradiated with laser light 3 2 C, and the laser light 3 2 C is partially irradiated. Therefore, the identification mark 1 2, 1 3 is not easy to destroy after the mark is formed, but the Chinese national standard (CNS) applies to the semiconductor crystal paper scale. A4 specification (210 X 297 mm) -18- 丨 丨 丨: mi (Please read the precautions on the back before filling this page)

Order --------- Line II Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 497189 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (16) The back of the circle 1 1 Y, that is, It is difficult to directly form an identification mark on a semiconductor substrate by a laser marking method. The reason is that the back surface 1 Y of the semiconductor wafer 1 may be damaged and the semiconductor wafer 1 may be easily cracked. Therefore, the conventional technology does not use a laser marking method to form an identification mark on the back side 1 of the semiconductor wafer 1. However, in this embodiment, as described above, by forming a mark formation layer 10 on the back side of the semiconductor wafer 1, Therefore, identification marks 1 2, 1 3 can be formed on the back 1 Y side of the semiconductor wafer 1 by laser marking. In this project, the semiconductor wafer 1 is attached to the adsorption platform 3 2 A on the mark forming section (mark formation device) 3 2 and the positioning circuit formation surface 1 is adsorbed and fixed to the adsorption platform 3 2 A in the X state. Since the protruding electrode 11 is not formed on the circuit forming surface 1 X side, the deformation of the protruding electrode 11 caused by the adsorption platform 3 2A of the mark forming portion 32 and the semiconductor wafer 1 being adsorbed and fixed can be prevented. Further, the defects of the identification marks 1 2, 1 3 caused by the unevenness of the semiconductor wafer 1 on the back surface 1 Y caused by the unevenness of the protruding electrode 11 can be prevented. In this process, the mark-forming layer 10 is formed of an epoxy-based thermosetting resin to which carbon is added. When the laser light irradiates the mark-forming layer 10, the carbon in the laser light irradiated portion melts away, and the irradiated portion becomes white and remains, so that an identification mark with good visibility can be formed. In addition, the probe detection is performed by making the probe 3 6 A contact the circuit formation surface 1 of the semiconductor wafer 1 on the X side to measure electrical characteristics, and the mark formation is performed on the back surface 1 of the semiconductor wafer 1 on the Y side. When the coordinate system is used as the coordinate system of the same device, the positive and negative directions of the semiconductor wafer 1 are reversed. Therefore, it is necessary to perform the conversion in the mark formation process. This paper size applies to China National Standard (CNS) A4 (210 χ 297 mm) -19- ------ I ------------- r --- * ^- ------- ^ ----- ^ --- (Please read the notes on the back before filling this page) -ϋ n ϋ I · ϋ -ϋ ϋ ^ 1 ^ 1 n 497189 A7 B7 5 2. Description of the invention (17), as shown in FIG. 17 and FIG. 18, a protruding electrode 11 (G) is formed on an electrode pad 9B of each wafer forming region 4 of the semiconductor wafer 1. The formation of the protruding electrode 11 is not limited to this. For example, a spherical solder material can be supplied to the electrode pad 9B by a solder ball supply method, and then the spherical solder material can be melted by an infrared reflow method. The bump electrode 11 may be formed by, for example, printing a solder paste on the electrode pad 9B by a screen printing method, and then melting the solder paste by an infrared reflow method. After that, a burn-in test (Η) is performed in a wafer state. The burn-in test is to perform the circuit operation of each wafer formation area 4 under the use conditions (additional conditions) that are extremely severe compared with the customer's use conditions, so that the customer can accelerate the occurrence of possible defects during use, in the initial stage before production to the customer Selection test to exclude defective products. After that, a semiconductor wafer 1 is mounted on the adhesive layer 4 0 A of the dicing film 40. The mounting of the semiconductor wafer 1 is performed with the circuit formation surface 1 of the semiconductor wafer 1 in an X-up state. After that, the semiconductor wafer 1, the mark formation layer 10, and the pad rearrangement layer 16 are divided into respective wafer formation regions 4 (I) by a slicing device. Accordingly, the semiconductor device 20 is roughly completed as shown in FIG. Afterwards', as shown in FIG. 19, the semiconductor device 20 is pushed up by the push pin 4 2 above the picking device from below the dicing film 40, and then sent to the pickup like the semiconductor device 20 pushed up. As shown in FIG. 20, the suction chuck 4 3 (J) of the device allows the semiconductor device 20 to be housed in a jig 4 4 (K). The storage of the semiconductor device 20 of the jig 44 is carried out with the identification marks 1 2, 13 facing upward. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -20-(Please read the note on the back? Matters before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs — 1 ϋ I Ji ϋ ϋν 1: mouth, ϋ ϋ I ϋ ϋ ϋ ϋ I ^ 1 IH ϋ ~ ϋ ϋ ϋ—497 497189 A7

The manufacturing of a memory module (electronic device) for assembling a wafer-level cs p-type semiconductor device 20 according to FIGS. 21 and 22 will be described below. Fig. 2 is a flowchart for explaining the manufacture of the 1 series memory module, and Fig. 2 is a cross-sectional view of the Wu series of the 2 series memory. First, most semiconductor devices 20 (L) are mounted on the surface (one main surface) side of the front and back surfaces (one main surface and the other main surface facing each other) of the mounting substrate 51, and then heat-treated. A plurality of semiconductor devices 20 (M) are mounted on the surface side of the mounting substrate 51. After that, the majority of the semiconductor devices 20 (N) are mounted on the back side of the mounting substrate 51, and heat treatment is applied to mount the majority of the semiconductor devices 20 (0) on the back side of the mounting substrate 51. After 'the functional test (P) of most semiconductor devices 20 is performed, after the resin 5 2 (Q) is filled between the mounting substrate 51 and the semiconductor device 20, the functional test (R) of most semiconductor devices 20 is performed again . Follow this to complete the memory module 50. According to this embodiment, the following effects can be obtained. (1) In the manufacture of the semiconductor device 20, after the process of forming the majority of the wafer formation regions 4 with DRA M on the circuit formation surface 1 X of the semiconductor wafer 1, before the process of forming the bump electrodes 11 in each wafer formation region 4 It is provided with a process of forming identification marks 1 2 and 1 3 on the back surface 1 side area of the semiconductor wafer 1 corresponding to each wafer formation area 4. Accordingly, when an identification mark is formed on the back surface 1 of the semiconductor wafer 1, since the protruding electrode 1 1 is not formed on the X-side of the circuit formation surface 1 of the semiconductor wafer 1, the adsorption platform 3 2 A of the mark formation portion 3 2 adsorbs and fixes the semiconductor. Deformation of the protruding electrode 11 generated during the wafer 1 can be prevented. Also 'protruding electrode 1 1 This paper size applies to Chinese National Standard (CNS) A4 specifications (210 X 297 mm) -21-(Please read the note on the back? Matters before filling out this page) Staff Consumption of Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the cooperative-I · III J- IIJ ^ 11111111 --- A---"497189

5. Description of the invention (19) The irregularity of the identification mark caused by the unevenness of the back surface 1 Y of the semiconductor wafer 1 caused by the unevenness of the semiconductor wafer 1 can be prevented. As a result, the yield of the semiconductor device 20 can be improved (please read the precautions on the back before filling in this page) (2) Manufacturing of the semiconductor device 2 0, forming the circuit with the DRAM 1 on the circuit forming surface 1 of the semiconductor wafer 1 After most of the processes of forming the wafers 4, the process of “cutting the back surface 1 Y of the semiconductor wafer 1” is provided “before the process of forming the bump electrodes 11 1 in each of the wafers forming regions 4”. When the semiconductor wafer 1 is chipped accordingly, the unevenness of the thickness of the semiconductor wafer 1 caused by the unevenness of the protruding electrode 11 can be prevented because the protruding electrode 11 is not formed on the X-side of the circuit formation surface 1 of the semiconductor wafer 1. As a result, in the dividing process in which the semiconductor wafer 1 is divided into individual wafer formation regions 4, cracks in the semiconductor wafer 1 caused by uneven thickness can be prevented, and the yield of the semiconductor device 20 can be improved. (3) In the manufacturing of the semiconductor device 20, after the process of cutting the back surface 1 Y of the semiconductor wafer 1, there is a process of forming identification marks on the back surface 1 of the semiconductor wafer 1 corresponding to each wafer formation area 4 . When printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the semiconductor wafer 1 was tortured due to the fact that no identification marks were formed on the back side 1 of the semiconductor wafer 1 and the Y side of the stress concentration identification marks. Cracking is prevented. As a result, the yield of the semiconductor device 20 can be improved. (4) In the manufacture of the semiconductor device 20, the mark forming layer 10 is formed of an epoxy-based thermosetting resin with carbon added. When the laser light is irradiated to the mark forming layer 10, the carbon in the laser light irradiated portion is melted and the irradiated portion is irradiated. Whitening residue. Therefore, an identification mark with good visibility can be formed. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) -22-A7

V. Description of the invention such as) (5) In the manufacture of semiconductor devices 20, the majority of the wafer formation areas with DRA M are formed on the circuit formation surface 1 X side of the semiconductor wafer 丄 After the process, the semiconductor wafer 1 is divided into individual wafers. Before the formation of the region 4, the process of measuring the electrical characteristics of the DRA M of each wafer formation region 4 is provided, and each of the D r A including the above measurement process is formed on the back surface 1 γ side of the semiconductor wafer 1 corresponding to each wafer formation region 4. The identification of the electrical information such as the electrical characteristics of M. Based on this, a part of the good-quality information management semiconductor device 20 can be added, and the semiconductor device 20 can be managed stably and safely without being affected by unstable conditions such as the position inside the jig. Also, the semiconductor device has a high degree of independent processing freedom, and it is convenient to use as an assembly component of a memory module. (6) In the manufacture of the semiconductor device 20, the identification mark 13 is formed by a two-dimensional code mark. Therefore, more information can be stored in a small area, and the machine can read it quickly, and the production efficiency of the control electrode (50) of the memory module can be improved. In the description of this embodiment, the identification mark is formed by multiplication by laser marking. However, the identification mark may be formed by an inkjet marking method using a direct printing mark forming device or an inkjet type mark forming device. In this case, the formation of the identification mark on the back surface 1 γ of the semiconductor wafer 1 may be g, but since the mark formation layer 10 has better adhesion than the ink, the identification mark is not easy to fall off. In this embodiment, an example is described in which the identification mark 1 2 or 13 is formed on the mark formation layer 10 by a laser marking method, but it may be formed without a mark (please read the precautions on the back before filling this page). Printed by the Ministry of Intellectual Property Bureau's Consumer Cooperative

I ϋ J- ii ii ϋ »Order --------- line --------- 7 I This paper size applies to China National Standard (CNS) A4 specification (210 X 297 metric t)- 23- 497189 A7

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention P) Layer 10 is directly formed by the laser marking method with identification marks 1 2, 1 3 on the back 1 Y side of the semiconductor wafer 1. In this case, mark formation is performed with a mark depth (the depth of the fused silicon) at which the semiconductor wafer 1 does not crack, for example, a shallow mark depth of about 2 to 3 // m. In this embodiment, an example is described in which identification marks 1 2 and 13 are formed on the mark formation layer 10 by a laser marking method, but the identification mark 1 may be directly formed by an inkjet marking method without providing the mark formation layer 10. 2, 1 3 are formed on the back surface 1 Y side of the semiconductor wafer 1. In this embodiment, the burn-in test of the wafer state is used for description, but the burn-in test may be performed after the slicing process, that is, after the semiconductor wafer 1 is divided into semiconductor devices 20. In this embodiment, a semiconductor manufacturing device 3 0 A for forming a mark without reversing the upper and lower directions of the semiconductor wafer 1 is used as an example for explanation, but as shown in FIG. 23 (schematic configuration diagram), it is used for a probe. A semiconductor manufacturing apparatus 3 0 B having a wafer reversing mechanism 37 between the detection section 31 and the mark forming section 32 may be used. The wafer reversing mechanism 37 reverses the up and down direction of the semiconductor wafer 1 and supplies the semiconductor wafer 1 to the mark forming section 32. In addition, in this embodiment, a tester is used to test the electrical characteristics of the circuits in each wafer formation area 4, and the characteristic information such as the electrical characteristics of each circuit and the position information of each wafer formation area 4 are simultaneously stored in the information storage device of the inspection machine. As an example, the position information of each wafer formation area 4 is converted from the position coordinates in the circuit formation surface 1 X of the semiconductor wafer 1 to the position coordinates of the back side 1 of the semiconductor wafer 1 as an example, but each wafer can also be made The position information of the formation area 4 is formed by the circuit formation surface 1 of the semiconductor wafer 1. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -24-— — — —I— i — — — — —. I — — III Erding — — — i I · (Please read the note on the back? Matters and then fill out this page} 497189 A7 --- ____ B7___ V. Sample description) Coordinate transformation to semiconductor wafer The position coordinates of the back side of 1 and the Y side are stored in the information storage device of the detector. The present invention has been described based on the embodiments, but the present invention is not limited to the above embodiments, and various changes can be made without departing from the gist of the present invention. For example, the present invention can be applied to an electronic device in which a semiconductor wafer (bare die) is worn on a women's substrate in a bare state. (Effects of the Invention) The effects of the present invention are briefly described as follows. According to the present invention, the yield of the semiconductor device can be improved. Stable and safe use of some good products. (Brief description of the drawings) FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a bottom view of a semiconductor device according to an embodiment of the present invention. FIG. 3 is a cross-sectional view of an important part of a semiconductor device according to an embodiment of the present invention. 1 ^ 1 ϋ ϋ ϋ ϋ ϋ ϋ ϋ ί I ϋ ^ 1 J. / I ϋ. Yi-kou * · I n (Please read the note on the back? Matters before filling out this page) Line 丨 & Intellectual Property of the Ministry of Economic Affairs Bureau staff consumer cooperatives printed maps and process flow packs. The implementation of the expansion of the semi-broken body of the body guide surface is as follows: I know the three parts of the layout. The book is used to make the shape of the semi-broken guide. The face of a picture shows the origin of flat hair: Crystal 6 The figure of the guide half of the figure The figure of the decent guide half of the round crystalline body Use medium-range crystals and medium-range papers to comply with China National Standard (CNS) A4 (210 X 297 mm) -25-Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 497189 A7 --B7 V. Description of Invention @ 3 ) FIG. 8 is a cross-sectional view of an important part of a semiconductor wafer used in a semiconductor device manufacturing process according to an embodiment of the present invention. Fig. 9 is a cross-sectional view of an important part of a semiconductor wafer used in a process for forming a pad re-arrangement layer in a semiconductor device manufacturing process according to an embodiment of the present invention. FIG. 10 is a cross-sectional view of an important part of a semiconductor wafer used in a process for forming a pad re-arrangement layer in a semiconductor device manufacturing process according to an embodiment of the present invention. FIG. 11: A cross-sectional view of an important part of a semiconductor wafer used for explaining a wafer back-side cutting process in a semiconductor device manufacturing process according to an embodiment of the present invention. A cross-sectional view of an important part of a semiconductor wafer used in the formation engineering process of the mark formation layer in FIG. FIG. 13 is a schematic configuration diagram of a semiconductor manufacturing apparatus used for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 14 is a perspective view for explaining a probe detection process in a semiconductor device manufacturing process according to an embodiment of the present invention. Fig. 15 · Bottom view of a semiconductor wafer used for the explanation of a mark formation process in a semiconductor device manufacturing process according to an embodiment of the present invention. FIG. 16 is a plan view of a semiconductor wafer used in the process of forming a protruding electrode in a semiconductor device manufacturing process according to an embodiment of the present invention. Figure 17: A cross-sectional view of an important part of a semiconductor wafer used in the process of forming a protruding electrode in a semiconductor device manufacturing process according to an embodiment of the present invention. (Centi) -26-^ 1 «_ϋ ϋ ϋ ϋ ϋ I ϋ 1 IJ ϋ ϋ —m --OJ ϋ ϋ ^ 1 1 (Please read the notes on the back before filling out this page) 497189 A7

V. Description of the Invention) Figure 18: A cross-sectional view of an important part used in the slicing process description in the manufacturing process of a semiconductor device according to an embodiment of the present invention. FIG. 19 is a cross-sectional view of an important part for explaining a pick-up process in a semiconductor device manufacturing process according to an embodiment of the present invention. FIG. 20 is a cross-sectional view of an important part for explaining a jig storage process in a semiconductor device manufacturing process according to an embodiment of the present invention. Fig. 2 · A flowchart for explaining the manufacturing of a memory module incorporating a semiconductor device according to an embodiment of the present invention. Fig. 22 is a sectional view of a memory module incorporating a semiconductor device according to an embodiment of the present invention. FIG. 23 is a schematic configuration diagram of another semiconductor manufacturing device used in semiconductor fabrication and manufacturing according to an embodiment of the present invention. im ---- 1—tr ----- (Please read the precautions on the back before filling out this page) The Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs printed the note No. 122345678 Fu semiconductor wafer multilayer wiring layer electrode pads Surface protection film Wafer formation area Line drawing area Insulation layer Wiring insulation layer This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) -27- — Line — Peak ---- :! J 丨 丨 497189 A7 B7 V. Description of the invention Calcium 9 A 9 B 10 11 15 16 2〇3 0 A 3〇B 3 1 3 1 A 3 1 B 3 2 3 2 A 3 2 B 3 2 C 3 2 D 3 3 3 4 3 5 3 6 3 6 A 3 7 4〇 Detecting electrode pads Electrode pad mark formation layer protrusion electrode Semiconductor wafer pad relocation layer Semiconductor device Semiconductor manufacturing device Semiconductor manufacturing device Probe detection unit Adsorption platform support table Marking section adsorption platform laser oscillator laser light zigzag lens loading section buffer section unloading section probe card probe wafer reversing mechanism slice film (please read the precautions on the back before filling this page)

--I-^ ---- Order --------- J Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economy The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -28-497189 A7 _B7 V. Description of the invention 4) 〇A Adhesive layer 4 2 Push-up pin 4 3 Suction chuck 4 4 Fixture 5 〇 Memory module 5 1 Mounting substrate 5 2 Resin (Please read the note on the back first Please fill in this page again for matters) -----. J --- • Order · -------- j Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Employees' Cooperatives This paper is printed in accordance with China National Standard (CNS) A4 (210 X 297 mm) • 29-

Claims (1)

497189 C] ou A8 B8 C8 D8 a〇 ^ [\ 丄 Dagger application for patent scope No. 89 105366 patent application printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Employee Consumption Cooperative Patent Amendment in Chinese Application for Patent Scope Amendment in January 1990 A method for manufacturing a semiconductor device, which is characterized in that: after a process of forming a plurality of wafer formation regions with circuits on a surface of a front surface and a back surface of a semiconductor wafer, and before a process of forming a protruding electrode on each of the wafer formation regions, The process of forming an identification mark on the back side area of the semiconductor wafer corresponding to each of the wafer formation areas. 2 · A method for manufacturing a semiconductor device, characterized in that, after a process of forming a plurality of wafer formation regions with circuits on a surface of a front surface and a back surface of a semiconductor wafer, the semiconductor wafer is divided into the respective wafer formation regions. Prior to the project, there are a process of re-arranging electrode pads in each of the wafer formation areas, and a process of forming a protruding electrode on the re-arranged electrode pad; and, after the electrode pad re-arrangement process, Prior to the formation process, a process of forming an identification mark in a region on the back side of the semiconductor wafer corresponding to each of the wafer formation regions is provided. 3. The method for manufacturing a semiconductor device according to item 1 or 2 of the scope of patent application, wherein the identification mark is formed on the back of the semiconductor wafer by laser-marking or ink_marking. 4. For the manufacturing method of semiconductor device in the scope of patent application No. 1 or 2, in which the paper size is applicable to China National Standard (CNS) A4 specification (210X297 cm) (Please read the precautions on the back before filling this page) 497189 A8 B8 C8 ____ D8 VI. Scope of patent application The above identification marks are formed on the back surface of the semiconductor wafer by a laser marking method or an inkjet marking method. (Please read the precautions on the back before filling in this page.) 5 · If you are manufacturing a semiconductor device in the scope of patent application No. 1 or 2, the above-mentioned mark-forming layer is made of epoxy resin with carbon added. 6 · A method for manufacturing a semiconductor device, characterized in that: after a process of forming a plurality of wafer formation regions with circuits on a surface of a front surface and a back surface of a semiconductor wafer, a process of forming a protruding electrode on each of the wafer formation regions described above Previously, a process for cutting the back surface of the semiconductor wafer was provided. 7-A method for manufacturing a semiconductor device, characterized in that, after a process of forming a plurality of wafer formation regions with circuits on a surface of a front surface and a back surface of a semiconductor wafer, the semiconductor wafer is divided into the respective wafer formation regions. Before the project, the process of re-arranging electrode pads in the above-mentioned wafer formation areas and the process of forming protruding electrodes on the re-arranged electrode pads are provided; The Ministry of Economic Affairs ’Intellectual Property Bureau employee ’s consumer co-operative printed pole formation project has the process of cutting the back side of the semiconductor wafer. 0 8 If a method of manufacturing a semiconductor device is applied for a patent scope item 6 or 7, After the process of forming the back surface of the semiconductor wafer and before the process of forming the protruding electrodes, a process of forming an identification mark in the region of the back side of the semiconductor wafer corresponding to each of the wafer formation regions is provided. This paper size applies to China National Standard (CNS) A4 (210X297 mm) -2-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 497189 A8 B8 C8 __ D8 VI. Patent Application Scope 9 · If the scope of patent application is 6 or The method for manufacturing a semiconductor device according to item 7, wherein the identification mark is formed on the back surface of the semiconductor wafer by laser-marking or ink-marking. 10. The method for manufacturing a semiconductor device according to item 6 or 7 of the scope of patent application, wherein the identification mark is a mark formation layer formed on the back surface of the semiconductor wafer by a laser marking method or an inkjet marking method. 1 1 · The method for manufacturing a semiconductor device according to claim 6 or 7, wherein the mark-forming layer is made of an epoxy resin with carbon added. 12 · A method for manufacturing a semiconductor device, comprising: a process of forming a plurality of wafer-forming regions having circuits on a surface on a front surface and a back surface of a semiconductor wafer; and a process of measuring electrical characteristics of the circuit in each of the wafer-forming regions. ; A process of forming an identification mark including characteristic information such as electrical characteristic results of the circuits obtained by the measurement process on the back side of the semiconductor wafer corresponding to the respective wafer formation regions. 1 3 · The method for manufacturing a semiconductor device according to item 12 of the scope of patent application, wherein after the wafer formation area formation process described above, and before the identification mark formation process is provided, the process of repositioning electrode pads in the wafer formation area is provided. 1 4 · If the semiconductor device is manufactured under the scope of patent application No. 13, the paper size is applicable to the Chinese National Standard (CNS) A4 specification (21〇 > < 297 mm) _ 3 · (Please read the notes on the back first (Fill in this page again) 497189 B8 C8 D8 々, patent application method, which (please read the precautions on the back before filling out this page) After the above electrode pad relocation process, before the above identification mark formation process, have engineering. 1 5 · The method for manufacturing a semiconductor device according to item 13 or 14 of the scope of patent application, wherein after the identification mark formation process, a process of forming a protruding electrode on the electrode pads repositioned is provided. 16. The method for manufacturing a semiconductor device according to item 15 of the scope of application for a patent, wherein the process of forming the protruding electrodes is followed by a process of dividing each of the semiconductor wafers into respective wafer formation regions. 17 · The method for manufacturing a semiconductor device according to item 12 of the patent application range, wherein the identification mark is formed by a two-dimensional code mark. 18 · The method for manufacturing a semiconductor device according to item 12 of the scope of patent application, wherein the identification mark is formed on the back surface of the semiconductor wafer by an inkjet marking method. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 19 · For the method of manufacturing a semiconductor device as described in item 12 of the patent application scope, the above identification mark is a mark forming layer formed on the back of the semiconductor wafer by laser marking method Or inkjet marking method. 2 · If the manufacturing method of the semiconductor device in item 19 of the scope of patent application, the paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -4 · 497189 A8 B8 C8 ____D8 The mark forming layer is made of carbon-added epoxy resin. 21 · —A method for manufacturing a semiconductor device, which is characterized by: (Please read the precautions on the back before filling this page) (1) The process of preparing a semiconductor wafer with a plurality of wafer formation regions The main surface of the jig and the back surface facing the main surface are formed with integrated circuits and a plurality of electrodes on the main surface, and are separated by a plurality of separation lines; (2) the back surface of the semiconductor wafer is cut by (3) a process of thinning the semiconductor wafer; (3) a process of forming an identification mark by laser on the back of the thinned semiconductor wafer after the process (2); (4) the process of (3) ), A process of forming a plurality of protruding electrodes on a plurality of electrodes formed on the main surface of the semiconductor wafer; (5) after the process (4), dividing the semiconductor wafer along the plurality of division lines, This is a process for forming a plurality of semiconductor wafers each having the plurality of protruding electrodes. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 2 Z. For example, the method of manufacturing a semiconductor device under the scope of patent application No. 21. The method is after the above-mentioned project (2) and before the above-mentioned project (3). The process of forming a resin layer on the back surface of the semiconductor wafer, the identification mark is formed on the resin layer, and the resin layer is divided by the above process (5), and formed on most semiconductor wafers on which the resin layer is formed on the back surface. This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) _ 5 _