KR100590639B1 - A method of manufacturing a semiconductor device - Google Patents

Abstract

In the method of manufacturing a semiconductor device, after the step of forming a plurality of chip formation regions having a circuit on the surface of the front and back surfaces of the semiconductor wafer, each of the chips before the step of forming a bump electrode on each chip formation region. And forming an identification mark in the region on the back side of the semiconductor wafer corresponding to the formation region.

Semiconductor wafer, bump electrode, electrode pad

Description

A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

1 is a plan view of a semiconductor device according to one embodiment of the present invention.

2 is a bottom view of a semiconductor device according to one embodiment of the present invention.

3 is an essential part cross sectional view of a semiconductor device of one embodiment of the present invention;

4 is an enlarged cross-sectional view of a portion of FIG. 3;

5 is a flowchart for explaining fabrication of a semiconductor device according to one embodiment of the present invention.

6 is a plan view of a semiconductor wafer used in the manufacture of a semiconductor device of one embodiment of the present invention;

7 is a plan view of a semiconductor wafer for explaining a wafer preprocessing process in the manufacture of a semiconductor device of one embodiment of the present invention;

8 is an essential part cross sectional view of a semiconductor wafer for explaining wafer preprocessing in the manufacture of a semiconductor device as one embodiment of the present invention;

9 is an essential part cross sectional view of a semiconductor wafer for explaining a step of forming a pad rearrangement layer in the manufacture of a semiconductor device of one embodiment of the present invention;

Fig. 10 is a sectional view of an essential part of a semiconductor wafer, for explaining a step of forming a pad rearrangement layer in the manufacture of a semiconductor device of one embodiment of the present invention.

11 is an essential part cross sectional view of a semiconductor wafer for explaining a wafer back surface grinding step in the manufacture of a semiconductor device of one embodiment of the present invention;

12 is an essential part cross sectional view of a semiconductor wafer for explaining a step of forming a mark forming layer in the manufacture of a semiconductor device of one embodiment of the present invention;

Fig. 13 is a schematic configuration diagram of a semiconductor manufacturing apparatus used for manufacturing a semiconductor device of one embodiment of the present invention.

14 is a perspective view for explaining a probe inspection step in the manufacture of a semiconductor device according to one embodiment of the present invention;

Fig. 15 is a bottom view of a semiconductor wafer for explaining a marking step in the manufacture of a semiconductor device of one embodiment of the present invention.

16 is a plan view of a semiconductor wafer for explaining a step of forming a bump electrode in the manufacture of a semiconductor device of one embodiment of the present invention;

17 is an essential part cross sectional view of the semiconductor wafer for explaining a step of forming a bump electrode in the manufacture of a semiconductor device of one embodiment of the present invention;

18 is an essential part cross sectional view for explaining a dicing step in the manufacture of a semiconductor device according to one embodiment of the present invention;

19 is an essential part cross sectional view for explaining a pickup step in the manufacture of a semiconductor device according to one embodiment of the present invention;

20 is an essential part cross sectional view for explaining a jig packing step in the manufacture of a semiconductor device of one embodiment of the present invention;

21 is a flowchart for explaining fabrication of a memory module incorporating a semiconductor device according to one embodiment of the present invention.

22 is a cross-sectional view of a memory module incorporating a semiconductor device according to one embodiment of the present invention.

Fig. 23 is a schematic structural diagram of another semiconductor manufacturing apparatus used for manufacturing a semiconductor device of one embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

1: semiconductor wafer

2: multilayer wiring layer

2a: electrode pad

3: surface protective film

4: chip formation area

5: dicing area

6: insulation layer

7: wiring

8: insulation layer

9a: electrode pad for inspection

9b: electrode pad

10: mark formation layer

11: bump electrode

15: semiconductor chip

16: pad repositioning layer

20: semiconductor device

30a, 30b: semiconductor manufacturing apparatus

31: probe inspection unit

31a: adsorption stage

31b: support

32: marking part

32a: adsorption stage

32b: laser oscillator

32c: laser light

32d: banding mirror

33: loader

34: buffer section

35: unloader

36: probe card

36a: probe needle

37: wafer inversion mechanism part

40: dicing sheet

40a: adhesive sheet

42: push up

43: collet

44: tray

50: memory module

51: mounting board

52: resin

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly, to an effective technique applied to a manufacturing technique of a semiconductor device in which electrode pads are rearranged in the state of a semiconductor wafer and bump electrodes are formed on the rearranged electrode pads.

In semiconductor devices incorporated in small electronic devices such as mobile phones, portable information processing terminal devices, and portable personal computers, thinning, miniaturization, and multipinning are required. Therefore, a semiconductor device called a CSP (Chip Size Package) type has been developed as a semiconductor device suitable for such a demand. In this CSP type semiconductor device, various structures have been proposed and commercialized, but as recently described in, for example, Nikon Micro Devices (August 1998, pages 44 to 71) published by Nikkei BP, Inc. A new CSP type semiconductor device (hereinafter referred to as a wafer level CSP type semiconductor device) manufactured by a manufacturing technique integrating a process and a package process (post process) has been developed. In this wafer level CSP type semiconductor device, since the planar size of the package becomes almost the same as that of the semiconductor chip, the CSP type semiconductor device manufactured by performing a package process for each semiconductor chip divided from the semiconductor wafer (hereinafter referred to as chip level CSP). The size and cost can be reduced.

The wafer level CSP type semiconductor device mainly includes a semiconductor chip having a circuit formed thereon, a pad rearrangement layer formed on a circuit formation surface which is a surface (circumferential surface) of front and back surfaces (circumferential and opposing major surfaces) of the semiconductor chip; It is a structure provided with the bump electrode arrange | positioned as a terminal for external connection on the pad rearrangement layer. The semiconductor chip mainly comprises a semiconductor substrate and a multilayer wiring layer in which a plurality of insulating layers and wiring layers are stacked on the circuit forming surface, which is the surface (circumferential surface) of the front and back surfaces (circumferential and opposing major surfaces) of the semiconductor substrate. It is a structure provided with the surface protection film formed so that the multilayer wiring layer may be covered. The electrode pad is formed in the wiring layer of the uppermost layer of a multilayer wiring layer, and the bonding opening which exposes an electrode pad is formed in the surface protection film. The pad rearrangement layer is a layer for forming an electrode pad having a wide array pitch with respect to the electrode pad of the semiconductor chip. The electrode pads of the pad rearrangement layer are electrically connected to the electrode pads of the corresponding semiconductor chips, and are arranged at the same arrangement pitch as the arrangement pitch of the electrode pads of the mounting substrate on which the semiconductor device is mounted. The bump electrodes are formed on the electrode pads of the repositioning layer and are electrically and mechanically connected.

The present inventors have found the following problems before developing a wafer level CSP type semiconductor device.

(1) The wafer level CSP semiconductor device is mounted in a state in which bump electrodes are faced to the mounting surface of the mounting substrate. Therefore, in the wafer level CSP type semiconductor device, it is necessary to form identification marks such as product names, company names, varieties, manufacturing lot numbers, and the like on the back side of the semiconductor chip. The identification mark is preferably formed before the semiconductor wafer is divided into respective chip formation regions, that is, in the state of the semiconductor wafer. The reason is that after dividing the semiconductor wafer into each chip formation region, the processing unit expands several hundred times as compared to the wafer state, which makes the processing complicated and affects quality and cost.

The formation of the identification mark in the wafer state is the back surface side of the semiconductor wafer corresponding to each of the plurality of chip formation regions formed on the circuit formation surface that is the surface (circumferential surface) in the front and back surfaces (circumferential and opposing major surfaces) of the semiconductor wafer. This can be done by forming identification marks in the areas on the other main surface side.

However, since the identification mark is formed in the wafer state by adsorbing and fixing the semiconductor wafer to the adsorption stage of the marking apparatus, when the identification mark is formed after the bump electrode is formed, the bump electrode is easily deformed and the wafer level is easily formed. It becomes a factor which reduces the yield of a CSP type semiconductor device. In addition, since the back surface of the semiconductor wafer becomes uneven due to the bumps and bumps of the bump electrodes, defects occur in the identification marks regardless of the contact type such as a direct printing marking device or the non-contact type such as an ink jet marking device. The yield of a level CSP semiconductor device falls.

(2) Although semiconductor wafers tend to be large-sized in order to increase the chip acquisition rate, the semiconductor wafers tend to bend as a result, so that the thickness of the semiconductor wafers increases with large-sized diameters. On the other hand, thinning is required in the semiconductor device incorporated in small electronic devices, such as a mobile telephone, a portable information processing terminal device, and a portable personal computer. Therefore, after performing pre-wafer process, the back grind process which grinds the back surface of a semiconductor wafer and makes thickness thin is needed.

However, since the back grind treatment is carried out by adsorption and fixing the semiconductor wafer to the adsorption stage of the grinding apparatus, when the back grind treatment is performed after the bump electrodes are formed, the thickness of the semiconductor wafer becomes uneven under the influence of bumps and bumps. . In the case where the thickness of the semiconductor wafer becomes uneven, cracks are likely to occur in the semiconductor wafer in the dicing step of dividing the semiconductor wafer into individual chip formation regions, so that the yield of the wafer-level CSP type semiconductor device decreases.

(3) When the back grinding process is performed after the identification mark is formed on the back side of the semiconductor wafer, the stress concentrates on the unevenness of the identification mark, and cracks easily occur in the semiconductor wafer, so that the yield of the wafer-level CSP type semiconductor device This degrades.

(4) As a circuit, for example, in a semiconductor device incorporating a memory circuit such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), a partial product (partially good memory) is selected and used as an example. However, in the case of utilization, a large amount of information can be recorded in order to convey the information (good or bad) of each mat of the memory circuit (state of the part: bank partial, address partial, I / O partial). There is a need. Since there is a limit to the amount of information in the conventional method of recording information on a semiconductor chip, a method of recording information by dividing the tray for each order or type of trays is considered.

However, managing the characteristic information in the order in which the trays are arranged leads to a manufacturing problem such as a decrease in yield when wrong information is transmitted when the order on the tray is inadvertently changed. Preparing a tray for the kind of part is not realistic considering the number of varieties, and there is no change in losing information when you leave the tray. In addition, the information recording performed in the chip level CSP type semiconductor device includes only the manufacturing information of the semiconductor chip, and does not include the information for utilizing the partial product, but also the information that can be physically recorded.

An object of the present invention is to provide a technique capable of improving the yield of a semiconductor device.

Another object of the present invention is to provide a technology capable of performing a partial product stably and safely.

The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.

The outline of a representative of the inventions disclosed herein is briefly described as follows.

(1) In the method of manufacturing a semiconductor device, after the step of forming a plurality of chip formation regions having a circuit system on the surface of the front and back surfaces of the semiconductor wafer, before the step of forming bump electrodes on the respective chip formation regions. And forming identification marks in regions on the back surface side of the semiconductor wafer corresponding to the respective chip formation regions.

(2) In the method of manufacturing a semiconductor device, after the step of forming a plurality of chip formation regions having a circuit system on the surface of the front and back surfaces of the semiconductor wafer, before the step of forming bump electrodes on the respective chip formation regions. A step of grinding the back surface of the semiconductor wafer is provided.

(3) In the method for manufacturing a semiconductor device according to the above means (2), after the step of grinding the back surface of the semiconductor wafer, identification marks are formed in the areas on the back surface side of the semiconductor wafer corresponding to the respective chip formation regions, respectively. It is equipped with the process of doing.

(4) In the method of manufacturing a semiconductor device, after the step of forming a plurality of chip formation regions having a circuit on the surface of the front and back surfaces of the semiconductor wafer, before the step of dividing the semiconductor wafer into the respective chip formation regions. A step of measuring electrical characteristics of a circuit of each chip forming region, and characteristic information based on the result of electrical characteristics of each of the circuits obtained in the measuring step on the back side of the semiconductor wafer corresponding to each of the chip forming regions; A step of forming an identification mark is provided.

According to the said means 1, when forming an identification mark in the back surface side of a semiconductor wafer, since the bump electrode is not formed in the surface side of a semiconductor wafer, deformation of the bump electrode which arises by adsorption-fixing a semiconductor wafer to the adsorption stage of a marking apparatus is carried out. Can be prevented. Moreover, the defect of the identification mark which arises by the unevenness | corrugation of the back surface of the semiconductor wafer resulting from the unevenness | corrugation of bump electrode can be prevented. As a result, the yield of a semiconductor device can be improved.

According to the said means (2), since the bump electrode is not formed in the surface side of a semiconductor wafer when grinding the back surface of a semiconductor wafer, the nonuniformity of the thickness of a semiconductor wafer resulting from the unevenness | corrugation of a bump electrode can be prevented. As a result, in the dicing step of dividing the semiconductor wafer into respective chip formation regions, cracks in the semiconductor wafer caused by uneven thickness can be prevented, so that the yield of the semiconductor device can be improved.

According to the said means (3), when grinding the back surface of a semiconductor wafer, since the identification mark is not formed in the back surface side of a semiconductor wafer, the crack of a semiconductor wafer which arises by stress concentrate | concentrating on the unevenness of an identification mark can be prevented. As a result, the yield of a semiconductor device can be improved.

According to the means (4), since the semiconductor device can be managed with the partial product information, it is possible to manage the semiconductor device stably and safely without being influenced by unstable conditions such as the position in the tray.

In addition, since the handing in the semiconductor device alone can be freed, the convenience in use as an assembly component to the memory module is improved.

Hereinafter, the configuration of the present invention will be described with an embodiment in which the present invention is applied to a wafer level CSP (Chip Size Package) semiconductor device. In addition, in the figure for demonstrating embodiment, the thing with the same function attaches | subjects the same code | symbol, and the description of the repetition is abbreviate | omitted.

1 is a plan view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a bottom view of the semiconductor device, FIG. 3 is a sectional view of an essential part of the semiconductor device, and FIG. 4 is an enlarged sectional view of a portion of FIG.

As shown in Figs. 1 and 2, the wafer level CSP type semiconductor device 20 of this embodiment has a flat surface in a quadrangular shape, and in this embodiment has a rectangular shape of 5 [mm] x 8 [mm], for example. Formed. As shown in FIG. 3, the semiconductor device 20 is mainly a semiconductor chip 15 and a circuit which is a surface (circumferential surface) of front and back surfaces (circumferential surfaces and other main surfaces facing each other) of the semiconductor chip 15. The pad rearrangement layer 16 formed on the formation surface 15X and the some bump electrode 11 arrange | positioned as the terminal for external connection on this pad rearrangement layer 16 are comprised.

The semiconductor chip 15 is formed in the same plane size as that of the semiconductor device 20. As shown in Figs. 3 and 4, the semiconductor chip 15 mainly includes a semiconductor substrate 1A and a circuit formation surface which is a surface among front and back surfaces (one main surface and the other main surface facing each other) of the semiconductor substrate 1A. The multilayer wiring layer 2 which overlapped each of an insulating layer and wiring layer in multiple stages above, and the surface protection film 3 formed so that this multilayer wiring layer 2 may be covered may be provided. The semiconductor substrate 1A is formed of, for example, single crystal silicon, and the insulating layer of the multilayer wiring layer 2 is formed of, for example, a silicon oxide film, and the wiring layer of the multilayer wiring layer 2 is, for example, an aluminum (Al) film or aluminum. It is formed of an alloy film, and the surface protective film 3 is formed of, for example, a silicon nitride film.

A plurality of electrode pads 2A are arranged in the center portion of the circuit formation surface of the semiconductor chip 15 along the long side direction. Each of the plurality of electrode pads 2A is formed on the uppermost wiring layer of the multilayer wiring layer 2 of the semiconductor chip 15. The uppermost wiring layer is covered with the surface protective film 3 formed on the upper layer, and the surface protective film 3 is formed with an opening 3A (see Fig. 4) exposing the surface of the electrode pad 2A. The planar shape of each of the plurality of electrode pads 2A is formed in a square shape of, for example, 25 [µm] × 25 [µm]. In addition, each of the plurality of electrode pads 2A is disposed at an array pitch of about 85 [μm], for example.

In the semiconductor chip 15, for example, a 64 megabit DRAM (Dynamic Random Access Memory) is formed as a memory circuit. The memory array of this DRAM has a 4-bank configuration, for example.

As shown in FIG. 3 and FIG. 4, the pad repositioning layer 16 mainly includes an insulating layer 6 formed on the surface protective film 3 and a plurality of wirings 7 extending on the insulating layer 6. ), An insulating layer 8 formed on the insulating layer 6 so as to cover the plurality of wirings 7, a plurality of electrode pads 9A for inspection and a plurality of electrodes formed on the upper layer of the insulating layer 8. It is the structure provided with the pad 9B.

One end of each of the plurality of wirings 7 is electrically and mechanically connected to each of the plurality of electrode pads 2A through an opening 6A formed in the insulating layer 6 and an opening 3A formed in the surface protective film 3. Connected. The other end of each of the wirings 7, which is approximately half of the plurality of wirings 7, is drawn out to one long side of one of the two long sides facing the semiconductor device 20, and the other end of each of the remaining wirings 7 is a semiconductor. The device 20 is drawn out to the other long side of two long sides facing each other (see FIG. 2).

Each of the plurality of inspection electrode pads 9A is electrically and mechanically connected to one end of each of the plurality of wirings 7 through an opening 8A (see FIG. 4) formed in the insulating layer 8. Each of the plurality of electrode pads 9B is electrically and mechanically connected to one end of each of the plurality of wirings 7 through an opening 8B (see FIG. 3) formed in the insulating layer 8. Each of the inspection electrode pad 9A and the electrode pad 9B is formed in the same layer. In addition, the inspection electrode pad 9A may not be formed.

Each of the plurality of electrode pads 9B is electrically and mechanically connected to a plurality of bump electrodes 11 arranged on the pad rearrangement layer 16 as terminals for external connection. Each of the plurality of bump electrodes 11 is formed of a metal material having, for example, 63 [wt%] lead (Pb) -37 [wt%] tin (Sn) composition.

The pad rearrangement layer 16 is a layer for rearranging the electrode pads 9B having a wide array pitch with respect to the electrode pads 2A of the semiconductor chip 15, and the electrode pads 9B of the pad rearrangement layer 16 are semiconductors. The arrangement 20 is arranged at the same arrangement pitch as the arrangement pitch of the electrode pads of the mounting substrate on which the device 20 is mounted.

Each of the plurality of electrode pads 9B is not limited to this, but as shown in FIG. 2, the semiconductor device 20 is disposed in two rows along each long side of two long sides facing each other. . The electrode pads 9B in each row are arranged at an array pitch of about 0.5 [mm], for example. The planar shape of each of the plurality of electrode pads 9B is formed in a circle having a diameter of about 0.25 [mm], for example. Each of the plurality of bump electrodes 11 is formed in a ball shape, for example, and its height (distance from the insulating layer 8 to the top) is, for example, about 0.15 [mm].

In addition, in FIG. 2, only 22 bump electrodes 11 are shown in order to make a drawing easy to see, but in the case of 64 megabit DRAM, about 50-60 electrode pads 9B and bump electrodes 11 are provided.

In the pad repositioning layer 16, each of the insulating layer 6 and the insulating layer 8 mounts the semiconductor device 20 on the mounting substrate, and then the stress generated by the thermal expansion difference with the mounting substrate is the bump electrode 11. In order to reduce the concentration on the surface), the material is formed of a material having a lower elastic modulus than the silicon nitride film or the silicon oxide film and is formed to a thickness thicker than the surface protective film 3. In this embodiment, each of the insulating layers 6 and 8 is formed of, for example, a polyimide resin, and the insulating layer 6 is formed to a thickness of, for example, about 5 to 100 [μm], and the insulating layer ( 8) is formed in the thickness of about 5-100 [micrometer], for example.

The wiring 7 is formed of, for example, a copper (Cu) film having high electrical conductivity. Although the electrode pad 9B is not limited to this, in order to ensure wettability when forming the bump electrode 11, for example, a chromium (Cr) film, 72 [at%] nickel (Ni)-28 [at% ] It is formed of a laminated film obtained by sequentially laminating an alloy film having a copper (Cu) composition and a gold (Au) film. In addition, the gold film diffuses into the bumps and almost disappears when the bump electrodes 11 are formed.

As shown in FIG. 3, the mark formation layer 10 is provided in the back surface 15Y of the semiconductor chip 15 so that the back surface 15Y may be covered. This mark formation layer 10 is formed with the epoxy type thermosetting resin which carbon was added, for example. Since the epoxy thermosetting resin has high adhesiveness with silicone, peeling of the mark formation layer 10 can be suppressed.

As shown in FIG. 1, the mark formation layer 10 is provided with an identification mark 12 and an identification mark 13. The identification mark 12 is formed with the mark which displays the information common to one semiconductor wafer, for example, information, such as a product name, a company name, a variety, a manufacturing lot number. The identification mark 13 is formed of a two-dimensional code mark that can record a large amount of information in a small area. In this identification mark 13, information unique to the semiconductor device 20, for example, partial product information of a DRAM (partial state: bank partial, address partial, I / O partial), and the like are recorded. Each of these identification marks 12, 13 is formed by a laser marking method in a marking process during a manufacturing process. The laser marking method is a method of irradiating a laser beam onto the surface of a mark formation region and burning the portion to which the laser beam is irradiated. The laser marking method does not require cleaning treatment before marking or drying treatment after marking, and it is difficult to eliminate the phenomenon that the identification mark is turned off after marking.

Next, manufacturing of the wafer level CSP type semiconductor device 20 will be described with reference to FIGS. 5 to 20.

FIG. 5 is a flowchart for explaining the manufacture of a semiconductor device, FIG. 6 is a plan view of a semiconductor wafer used for manufacturing a semiconductor device, and FIGS. 7 and 8 are a plan view of a semiconductor wafer for explaining a pre-wafer process. 9 is a sectional view of an essential part of the semiconductor wafer for explaining the electrode pad rearrangement process, and FIG. 11 is a sectional view of the essential part of the semiconductor wafer for explaining the wafer back grinding process, and FIG. 13 is a schematic cross-sectional view of a semiconductor manufacturing apparatus used for manufacturing a semiconductor device, FIG. 14 is a perspective view for explaining a probe inspection step, and FIG. 15. Is a bottom view of a semiconductor wafer for explaining the marking process, and FIGS. 16 and 17 illustrate a process for forming bumps. 18 is a sectional view of the main part of the semiconductor wafer for explaining the dicing process, FIG. 19 is a sectional view of the main part for explaining the picking process, and FIG. 20 is a jig packing. It is a top view of the principal part for demonstrating a process.

First, as shown in FIG. 6, a semiconductor wafer (semiconductor substrate; 1) made of single crystal silicon having a thickness of about 725 [µm] is prepared as a semiconductor wafer.

Next, the pre-wafer process <A> is performed on the semiconductor wafer 1, and as shown in FIGS. 7 and 8, one of the front and back surfaces (one main surface and the other main surface facing each other) of the semiconductor wafer 1. A plurality of chip formation regions 4 having DRAMs as circuits are formed in a matrix on the circuit formation surface 1X which is the surface (circumferential surface). Each of the plurality of chip formation regions 4 is disposed in a state spaced apart from each other through a dicing region (scribe region) 5 for cutting the semiconductor wafer 1. Each of the plurality of chip formation regions 4 mainly contains a semiconductor element, a multilayer wiring layer 2, an electrode pad 2A, a surface protective film 3, an opening 3A, and the like on the circuit formation surface 1X of the semiconductor wafer 1. It is formed by forming a.

Next, the pad rearrangement layer 16 is formed in each chip formation region 4 <B>. Specifically, first, an insulating layer 6 made of, for example, a polyimide resin is formed on the entire surface of the surface protective film 3 by a rotation coating method. The insulating layer 6 is formed to a thickness of, for example, about 5 [μm]. Next, an opening 6A exposing the surface of the electrode pad 2A is formed in the insulating layer 6. The process so far is shown in FIG. Next, for example, a copper (Cu) film is formed on the entire surface on the insulating layer 6 including the opening 6A by a low pressure CVD (chemical vapor deposition) method or a sputtering method. Next, the copper film is patterned to form the wiring 7. Next, an insulating layer 8 made of, for example, a polyimide resin is formed on the entire surface of the insulating layer 6 including the wiring 7 on the rotary coating method. The insulating layer 8 is formed to a thickness of, for example, about 5 [μm]. Next, an opening 8A that exposes one end side of the wiring 7 and an opening 8B that exposes the other end side of the wiring 7 are formed in the insulating layer 8. Next, for example, a chromium (Cr) film, 72 [at%] nickel (Ni) -28 [at%] copper, on the entire surface on the insulating layer 8 including the opening 8A and the opening 8B. Each of an alloy film having a (Cu) composition and a gold (Au) film is sequentially stacked to form a laminated film. Next, the laminated film is patterned to form the inspection electrode pad 9A and the electrode pad 9B. Thereby, the pad rearrangement layer 16 is formed, and the electrode pad 9B of an array pitch wider than the array pitch of the electrode pad 2A is formed. The process to here is shown in FIG.

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Next, as shown in FIG. 11, the back surface 1Y of the semiconductor wafer 1 is ground to make the thickness thinner <C>. In this embodiment, the semiconductor wafer 1 is ground until the thickness becomes, for example, about 400 [µm].

In this step, the semiconductor wafer 1 is adsorbed and fixed to the adsorption stage in a state where the circuit formation surface 1X side is faced to the adsorption stage of the grinding apparatus, but the bump electrode is provided on the circuit formation surface 1X side of the semiconductor wafer 1. Since 11 is formed, the thickness nonuniformity of the semiconductor wafer 1 resulting from the unevenness | corrugation of the bump electrode 11 can be prevented.

In this step, when grinding the back surface 1Y of the semiconductor wafer 1, the identification marks 12 and 13 are not formed on the back surface 1Y side of the semiconductor wafer 1, so that the identification marks 12 and 13 are used. This can prevent cracking of the semiconductor wafer 1 caused by concentration of stress in the unevenness.

Next, as shown in FIG. 12, the mark formation layer 10 which covers the back surface 1Y is formed in the back surface 1Y of the semiconductor wafer 1 <D>. Although the mark forming layer 10 of this embodiment is not limited to this, The thermosetting resin which carbon and the organic solvent were added to the epoxy resin is formed in the back surface 1Y of the semiconductor wafer 1 by the rotary coating method, and thereafter. It is formed by performing heat treatment to cure the thermosetting resin.

In this step, the semiconductor wafer 1 is adsorbed and fixed to the adsorption stage in a state where the circuit formation surface 1X is faced to the adsorption stage of the film forming apparatus, but the bump electrode (bump) is formed on the circuit formation surface 1X side of the semiconductor wafer 1. Since the 11) is not formed, the mark forming layer 10 can be formed without being affected by the unevenness of the bump electrode 11.

As the mark forming layer 10, a resin film made of a thermosetting resin in which carbon is added to an epoxy resin may be adhered to the back surface 1Y of the semiconductor wafer 1 while being bonded to each other. Also in this case, the mark forming layer 10 can be formed without being affected by the unevenness of the bump electrode 11.

Next, probe inspection <E> and marking <F> are performed using the semiconductor manufacturing apparatus 30A shown in FIG. The semiconductor manufacturing apparatus 30A includes a probe inspection unit 31, a marking unit 32, a loader unit 33, a buffer unit 34, an unloader unit 35, and the like. The loader part 33 supplies the semiconductor wafer 1 to the probe inspection part 31. The buffer part 34 accommodates the semiconductor wafer 1 processed by the probe test | inspection part 31, and supplies the semiconductor wafer accommodated after that to the marking part 32. FIG. The unloader part 35 accommodates the semiconductor wafer 1 processed by the marking part 32. The semiconductor manufacturing apparatus 30A of this embodiment marks on the back surface side of the semiconductor wafer 1 without inverting the up-down direction of the semiconductor wafer 1 processed by the probe test | inspection part 31. FIG.

Probe inspection <E> first adsorbs and fixes the semiconductor wafer 1 supplied from the loader part 33 by the adsorption stage 31A. Adsorption | suction fixing of the semiconductor wafer 1 is performed in the state which the back surface 1Y of the semiconductor wafer 1 faces in the adsorption stage 31A. The suction stage 31A is configured to be movable in the X-Y direction (plane direction) and the Z direction (up-down direction). The probe card 36 fixed to the support 31B is arrange | positioned above the suction stage 31A.

Next, as shown in FIG. 14, the adsorption stage 31A is raised to bring the semiconductor wafer 1 closer to the probe card 36, thereby aligning the position of the semiconductor wafer 1 with the probe card 36. After that, the probe needle 36A of the probe card 36 is brought into contact with the inspection electrode pad 9A of the chip formation region 4 of the semiconductor wafer 1.

Next, the electrical characteristics of the circuit of each chip formation area 4 are measured by the tester electrically connected with the probe needle 36A of the probe card 36, and the characteristic information based on the electrical characteristic result of each circuit is measured, respectively. The information recording device of the tester is stored together with the positional information of the chip formation region 4. By this step, the grades of electrical characteristics such as good products, defective products, partial products, operating frequency, and the like are determined for each chip formation region 4. The semiconductor wafer 1 in which the probe inspection is completed is stored in the buffer portion 34, and then supplied to the marking portion 32. At this time, together with the supply of the semiconductor wafer 1 to the marking portion 32, the characteristic information and the positional information of each chip formation region 4 in the semiconductor wafer 1 are transmitted to the marking portion 32.

Marking <F> first adsorbs and fixes the semiconductor wafer 1 supplied from the buffer part 34 to the adsorption stage 32A. Adsorption fixing of the semiconductor wafer 1 is performed in the state where the circuit formation surface 1X of the semiconductor wafer 1 faces the adsorption stage 32A. The adsorption stage 32A is configured to be movable in the X-Y direction and the Z direction similarly to the adsorption stage 31A described above. Below the adsorption stage 32A, the laser oscillator 32B and the bending mirror 32D are arrange | positioned.

Next, the positional information of each chip formation region 4 is converted from the positional coordinates on the circuit formation surface 1X of the semiconductor wafer 1 to the positional coordinates on the rear surface of the semiconductor wafer 1, and the converted angles According to the positional information of the chip formation region 4, as shown in FIG. 15, each circuit obtained by probe inspection in the area | region of the back surface 1Y side of the semiconductor wafer 1 corresponding to each chip formation region 4 is shown. The identification mark 13 containing the characteristic information based on the electrical characteristic result of is formed by the laser marking method. In addition, information common to one semiconductor wafer 1 on the back surface 1Y side of the semiconductor wafer 1 corresponding to each chip formation region 4, for example, product name, company name, variety, manufacturing lot number The identification mark 12, etc., is also formed by the laser marking method. The identification mark 13 is formed of a two-dimensional code mark capable of recording a large amount of information in a small area. In the formation of the identification marks 12 and 13 by the laser marking method, as shown in FIG. 13, the surface of the mark forming layer 10 is irradiated with the laser light 32C and the portion irradiated with the laser light 32C is burned out. Since the extinction phenomenon that the identification marks 12 and 13 disappear after marking is difficult to occur, it is difficult to form the identification mark immediately on the back surface 1Y of the semiconductor wafer 1, that is, the semiconductor substrate by laser marking. Do. The reason for this is that the back surface 1Y of the semiconductor wafer 1 is scratched, so that cracks are likely to occur in the semiconductor wafer 1. Therefore, although the identification mark was not formed by the laser marking method on the back surface 1Y side of the semiconductor wafer 1, the mark formation layer 10 is provided on the back surface side of the semiconductor wafer 1 as in the present embodiment. By placing it, the identification marks 12 and 13 can be formed on the back surface 1Y side of the semiconductor wafer 1 by the laser marking method.

In this step, the semiconductor wafer 1 is adsorbed and fixed to the adsorption stage 32A in a state in which the circuit formation surface 1X side is faced to the adsorption stage 32A of the marking portion (marking device) 32, but the semiconductor wafer ( Since the bump electrode 11 is not formed in the circuit formation surface 1X side of 1), the deformation of the bump electrode 11 which arises by adsorption-fixing the semiconductor wafer 1 to the adsorption stage 32A of the marking part 32 is carried out. Can be prevented. Moreover, the defect of the identification mark 1213 which arises from the unevenness | corrugation of the back surface 1Y of the semiconductor wafer 1 resulting from the unevenness | corrugation of the bump electrode 11 can be prevented.

In this step, the mark forming layer 10 is formed of an epoxy thermosetting resin to which carbon is added. When laser mark is irradiated to this mark formation layer 10, the carbon of the part to which the laser beam was irradiated evaporates and the irradiated part remains white. Therefore, an identification mark with good visibility can be formed.

In addition, since the probe inspection contacts the probe needle 36A to the circuit formation surface 1X side of the semiconductor wafer 1, electrical characteristics are measured, and marking is performed on the back surface 1Y side of the semiconductor wafer 1, Since the order and coordinates of the chip formation region 4 are positive and negative opposite to the direction in which the semiconductor wafer 1 is turned upside down as the coordinate system of the same device, the conversion is necessary in the marking step.

Next, as shown in FIGS. 17 and 18, bump electrodes 11 are formed on the electrode pads 9B of the chip formation regions 4 of the semiconductor wafer 1 <G>. Although the bump electrode 11 is not limited to this, for example, a spherical solder material is supplied on the electrode pad 9B by a ball supply method, and then the spherical solder material is melted by an infrared reflow method. . The bump electrode 11 may be formed by printing a solder paste material on the electrode pad 9B by screen printing, for example, and then melting the solder paste material by infrared reflow.

Next, a burn-in test is performed in the state of the wafer level <H>. The burn-in test performs the circuit operation of each chip formation region 4 under severe use conditions (additional state) compared to the use condition at the customer, and becomes a defect during use at the customer, in a sense, accelerating the defect. This is a screening test aimed at eliminating defects at the initial stage prior to shipment to the customer.

Next, the semiconductor wafer 1 is attached to the adhesion layer 40A side of the dicing sheet 40. The semiconductor wafer 1 is mounted in a state in which the circuit formation surface 1X of the semiconductor wafer 1 is upward.

Next, in the dicing apparatus, the semiconductor wafer 1, the mark formation layer 10 and the pad rearrangement layer 16 are divided for each chip formation region 4 <I>. As a result, as shown in FIG. 18, the semiconductor device 20 is almost completed.

Next, as shown in FIG. 19, the semiconductor device 20 is pushed upward by the picking-up needle 42 of the pick-up device from the lower side of the dicing sheet 40 and thereafter raised to the upper side ( 20 is conveyed to the suction collet 43 of the pick-up apparatus, and as shown in FIG. 20, the semiconductor device 20 is accommodated in the tray 44. <K>. Storing of the semiconductor device 20 in the tray 44 is performed in the state which identification mark 12, 13 was made upward.

Next, manufacturing of the memory module (electronic device) in which the wafer level CSP semiconductor device 20 is assembled will be described with reference to FIGS. 21 and 22.

21 is a flowchart for explaining the manufacture of a memory module, and FIG. 22 is a cross-sectional view of the memory module.

First, a plurality of semiconductor devices 20 are mounted on the front (circumferential surface) side of the front and back surfaces (circumferential and opposing major surfaces) of the mounting substrate 51, and then subjected to heat treatment thereafter, whereby the mounting substrate is subjected to heat treatment. On the surface side of 51, a plurality of semiconductor devices 20 are mounted <M>. Next, the plurality of semiconductor devices 20 are mounted on the back surface side of the mounting substrate 51 and then subjected to heat treatment, whereby the plurality of semiconductor devices 20 are placed on the back surface side of the mounting substrate 51. It is mounted <O>. Next, each functional test of the plurality of semiconductor devices 20 is performed <P>, thereafter, the resin 52 is filled between the mounting substrate 51 and the semiconductor device 20, and then <Q>. Again, a functional test of each of the plurality of semiconductor devices 20 is performed <R>. As a result, the memory module 50 is almost completed.

Thus, according to this embodiment, the following effects are obtained.

(1) In the manufacture of the semiconductor device 20, after the step of forming a plurality of chip formation regions 4 including DRAM on the circuit formation surface 1X of the semiconductor wafer 1, each chip formation region ( 4) forming the identification marks 12 and 13 in the regions on the back surface 1Y side of the semiconductor wafer 1 corresponding to the respective chip formation regions 4 before the process of forming the bump electrodes 11 on each. It is provided.

As a result, when forming the identification mark on the back surface 1Y side of the semiconductor wafer 1, since the bump electrode 11 is not formed on the circuit formation surface 1X side of the semiconductor wafer 1, the marking portion (marking) It is possible to prevent deformation of the bump electrode 11 generated by adsorbing and fixing the semiconductor wafer 1 to the adsorption stage 32A of the apparatus. Moreover, the defect of the identification mark which arises by the unevenness | corrugation of the back surface 1Y of the semiconductor wafer 1 resulting from the unevenness | corrugation of the bump electrode 11 can be prevented. As a result, the yield of the semiconductor device 20 can be improved.

(2) In the manufacture of the semiconductor device 20, after the step of forming a plurality of chip formation regions 4 including DRAM on the circuit formation surface 1X of the semiconductor wafer 1, each chip formation region ( 4) The process of grinding the back surface 1Y of the semiconductor wafer 1 is provided before the process of forming the bump electrode 11 on it.

Accordingly, when the back surface 1Y of the semiconductor wafer 1 is ground, the bump electrode 11 is not formed on the circuit formation surface 1X side of the semiconductor wafer 1, so that the bumps 11 are uneven. Unevenness of the thickness of the semiconductor wafer 1 which arises can be prevented. As a result, in the dicing process of dividing the semiconductor wafer 1 for each chip formation region 4, the crack of the semiconductor wafer 1 which arises because of the thickness nonuniformity can be prevented, so that the yield of the semiconductor device 20 can be Improvement can be aimed at.

(3) In the manufacture of the semiconductor device 20, after the step of grinding the back surface 1Y of the semiconductor wafer 1, the respective chip formation regions 4 and the back surface 1Y side of the semiconductor wafer 1 corresponding to each other. The process of forming an identification mark in each area is provided.

Accordingly, when the back surface 1Y of the semiconductor wafer 1 is ground, no identification mark is formed on the back surface 1Y side of the semiconductor wafer 1, so that the semiconductor wafer 1 caused by stress concentration on the unevenness of the identification mark. ) Cracks can be prevented. As a result, the yield of the semiconductor device 20 can be improved.                     

(4) In the manufacture of the semiconductor device 20, the mark forming layer 10 is formed of epoxy-based thermosetting resin to which carbon is added. Accordingly, when the laser beam is irradiated to the mark forming layer 10, the carbon in the portion irradiated with the laser light evaporates and the irradiated portion remains white. Therefore, an identification mark with good visibility can be formed.

(5) In the manufacture of the semiconductor device 20, after the step of forming a plurality of chip formation regions 4 having DRAM as a circuit on the circuit formation surface 1X of the semiconductor wafer 1, the semiconductor wafer 1 Measuring the electrical characteristics of the DRAM of each chip forming region 4 before the step of dividing the chip into each chip forming region 4 and the back surface 1Y of the semiconductor wafer 1 corresponding to each chip forming region 4. And a step of forming an identification mark 13 including characteristic information based on an electrical characteristic result of each DRAM obtained in the measurement step on the c) side.

As a result, since the semiconductor device 20 can be managed with partial product information, it is possible to manage the stable and safe semiconductor device 20 without being influenced by unstable conditions such as the position in the tray.

In addition, since the handing to the semiconductor device alone can be freed, the convenience in use as an assembly part to the memory module is improved.

(6) In the manufacture of the semiconductor device 20, the identification mark 13 is formed of a two-dimensional code mark. In this case, a large amount of information can be recorded in a small area, and the machine-readable reading can be performed quickly, thereby improving the production efficiency of the memory module 50.

Incidentally, in the present embodiment, a description has been given of an example in which the identification mark is formed by a laser marking method. However, the identification mark may be formed by an ink marking method using a direct printing marking apparatus, an ink jet marking apparatus, or the like. In this case, the identification mark can be formed on the back surface 1Y of the semiconductor wafer 1, but since the adhesion of ink is good on the mark forming layer 10 side, the identification mark becomes difficult to fall off.

In addition, in this embodiment, the example in which the identification marks 12 and 13 were formed in the mark forming layer 10 by the laser marking method was described. However, the back surface 1Y of the semiconductor wafer 1 without the mark forming layer 10 provided. ), The identification marks 12 and 13 may be formed by the laser marking method immediately. In this case, marking is performed at a mark depth (depth of silicon to be burned) at which the crack does not occur in the semiconductor wafer 1, for example, at a shallow mark depth of about 2 to 3 [μm].

In addition, in this embodiment, the example in which the identification marks 12 and 13 were formed in the mark forming layer 10 by the laser marking method was described. However, the back surface 1Y of the semiconductor wafer 1 without the mark forming layer 10 provided. ), The identification marks 12 and 13 may be formed by the ink marking method.

In addition, although the burn-in test in the wafer level state was demonstrated in this embodiment, a burn-in test may be performed after a dicing process, ie, after dividing the semiconductor wafer 1 into individual semiconductor devices 20.

In addition, in this embodiment, although the example using the semiconductor manufacturing apparatus 30A which marks without inverting the up-down direction of the semiconductor wafer 1 was demonstrated, as shown in FIG. 23 (a schematic block diagram), a probe The semiconductor manufacturing apparatus 30B provided with the wafer inversion mechanism part 37 between the test | inspection part 31 and the marking part 32 may be used. The wafer inversion mechanism part 37 supplies the semiconductor wafer 1 to the marking part 32 after inverting the up-down direction of the semiconductor wafer 1.

In the present embodiment, the electrical characteristics of the circuits of the respective chip formation regions 4 are measured by the inspector, and the characteristic information based on the electrical characteristic results of each circuit is inspected together with the positional information of the respective chip formation regions 4. After storing in the information recording apparatus of the semiconductor wafer 1, the positional information of each chip formation region 4 is positioned on the back surface 1Y of the semiconductor wafer 1 from the position coordinates on the circuit formation surface 1X of the semiconductor wafer 1. Although the example which converted into the coordinate was demonstrated, the positional information of each chip formation area | region 4 is not the positional coordinate in the circuit formation surface 1X of the semiconductor wafer 1 from the back surface 1Y of the semiconductor wafer 1. The position coordinates may be converted and stored in the information recording apparatus of the inspector.

As mentioned above, although the invention made by this inventor was demonstrated concretely based on the said Example, this invention is not limited to the said Example and can be variously changed in the range which does not deviate from the summary.

For example, the present invention can be applied to an electronic device for mounting a semiconductor chip (bare chip) in a state exposed to a mounting substrate.

Claims (26)

delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete In the method of manufacturing a semiconductor device, A semiconductor wafer comprising a main surface and a back surface opposite the main surface, the semiconductor wafer comprising a plurality of chip formation regions defined by dicing lines, each of the plurality of chip formation regions integrated circuits on the main surface. And an electrode pad-, Forming a plurality of bump electrodes on the main surface of the semiconductor wafer, the plurality of bump electrodes being electrically connected to the electrode pads respectively and protruding from the main surface of the wafer; After the forming step of the plurality of bump electrodes, forming a plurality of semiconductor chips by dicing the semiconductor wafer along the dicing lines, thereby forming the plurality of semiconductor chips each having a corresponding bump electrode; , Forming an identification mark on the back surface of the semiconductor wafer, the identification mark corresponding to the plurality of chip formation regions; and Providing the plurality of semiconductor chips each having the corresponding bump electrode and the corresponding identification mark by performing the step of forming the identification mark before the forming process of the plurality of bump electrodes. How to include. The method of claim 21, And prior to the forming of the plurality of bump electrodes, grinding the back surface of the semiconductor wafer to thin the plurality of wafers. The method of claim 22, And the identification mark is formed on the back surface of the semiconductor wafer ground by laser light. The method of claim 22, And forming a resin layer on the back surface of the ground semiconductor wafer before the forming process of the plurality of bump electrodes and after the thinning process of the semiconductor wafer. The identification mark is formed on the resin layer, After the dividing of the semiconductor wafer, each of the plurality of semiconductor chips includes a portion of the resin layer having the corresponding identification mark on the back surface. The method of claim 21, The electrode pads of each of the plurality of chip formation regions of the semiconductor wafer are arranged at a predetermined first pitch, The process of providing the semiconductor wafer further includes forming a plurality of rearranged electrode pads on the major surface of the semiconductor wafer, wherein the plurality of rearranged electrode pads are electrically connected with the corresponding electrode pads. and, Performing the forming process of the plurality of rearranged electrode pads such that the plurality of rearranged electrode pads are disposed at a predetermined second pitch wider than the predetermined first pitch of the electrode pad. The method of claim 25, Wherein the plurality of bump electrodes are each formed on the plurality of rearranged electrode pads.

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