CN106653955B - A kind of identification chip and preparation method thereof - Google Patents
A kind of identification chip and preparation method thereof Download PDFInfo
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- CN106653955B CN106653955B CN201510733318.5A CN201510733318A CN106653955B CN 106653955 B CN106653955 B CN 106653955B CN 201510733318 A CN201510733318 A CN 201510733318A CN 106653955 B CN106653955 B CN 106653955B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
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- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The present invention provides a kind of identification chip and preparation method thereof, the production method of the identification chip, the following steps are included: 1) provide an epitaxial structure, in forming barrier layer on the epitaxial structure, and N bore region and P bore region are formed in the barrier etch or corrosion；2) N electrode diffusion layer is made, the electrical property for N bore region is drawn；3) growth of passivation layer, performs etching the passivation layer or corrodes and form the first reserved area and the second reserved area, first reserved area and correspond to the P bore region；Wherein, first reserved area and the second reserved area include preset identification information.A kind of identification chip successively includes from bottom to top: growth substrates, light emitting epitaxial layer, transparency conducting layer, mirror layer, barrier layer, N electrode diffusion layer, passivation layer, electrode.The present invention, which provides a kind of identification chip and preparation method thereof, can be used for solving the problems, such as that different chips or chip electrode are difficult in the prior art.
Description
Technical field
The present invention relates to a kind of identification chip, especially a kind of identification chip and its manufacturing method.
Background technique
It is automatic used in the production of light emitting diode (Light Emitting Diode, referred to as LED), testing process
Change machine specifically includes die bonder (Die Bonder), bonding machines (Wire Bonder) and chip tester (Chip Prober)
(Pattern Recognition) function is identified etc. figure is required to, to differentiate the correct position of chip and board is guided to act.
Structure on LED chip is with metal electrode easy interpretation the most obvious, therefore when executing image identification one to gold
The figure for belonging to electrode is foundation.Chip surface is roughened (Surface Roughen) and pattern substrate (Patterned Sapphire
) etc. Substrate the use for improving chip brightness new technology, which often results in the variation of CCD image gray scale, causes metal electrode to be not easy
It distinguishes.And the typical sizes of LED chip, between 0.22mm~0.35mm, the electrode structure of LED chip is smaller, and it is further
It quickly distinguishes N-type and the difficulty of P-type electrode is bigger, it is therefore desirable to which a better scheme identifies LED chip, distinguishes chip P, N
Electrode, and it is suitable for various chips.
Although the producer of chip has nothing in common with each other, chip size specification is essentially the same, generally requires detection chip
Every electricity ginseng, beche-de-mer without spike observe internal circuit to distinguish brand, and identification is got up more troublesome.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of identification chip and its production sides
Method, for solving the problems, such as that different chips or chip electrode are difficult in the prior art.
In order to achieve the above objects and other related objects, the present invention provides a kind of identification chip production method, including following
Step:
1) epitaxial structure is provided, in forming barrier layer on the epitaxial structure, and in the barrier etch or corrosion
Form N bore region and P bore region；
2) N electrode diffusion layer is made, the electrical property for N bore region is drawn；
3) growth of passivation layer performs etching to the passivation layer or corrodes the first reserved area of formation and the second trough
Domain, first reserved area correspond to the P bore region；
Wherein, first reserved area and the second reserved area include preset identification information.
Preferably, first reserved area and the second reserved area depth are 2000-15000 μm.
Preferably, first reserved area and the second reserved area include letter, number, figure and symbol therein one
The identification information of kind or a variety of compositions.
Preferably, further include the following steps after step 3): forming N-type electrode and p-type electricity on the passivation layer
Pole, first reserved area are set to the P electrode region, and second reserved area is set to the N electrode region, use
In difference electrode.
Preferably, the depth of first reserved area is until transparency conducting layer or mirror layer, described second is reserved
The depth in region is until the N electrode diffusion layer.
Preferably, step 3) is comprising steps of 3-1) photoresist is coated in the passivation layer surface；3-2) to the photoresist
It is patterned processing；3-3) passivation layer is performed etching according to patterned photoresist or is corroded and forms the first trough
Domain and the second reserved area.
Preferably, the production method of the epitaxial structure is the following steps are included: 1-1) growth substrates are provided, in the lining
Light emitting epitaxial layer is formed on bottom；1-2) in forming transparency conducting layer on the light emitting epitaxial layer, Cutting Road region is then etched
With N bore region；1-3) in making mirror layer on the transparency conducting layer.
Preferably, step 1-2) in, the depth of the N bore region is the N-type layer until the light emitting epitaxial layer.
The present invention also provides a kind of identification chips, successively include from bottom to top: growth substrates；Light emitting epitaxial layer is formed
In the upper surface of substrate；Transparency conducting layer is formed in the light emitting epitaxial layer upper surface；Mirror layer is formed in described
Bright conductive layer upper surface；Barrier layer, is formed in the epitaxial structure upper surface, and the barrier layer has N bore region and is located at the hole P
Region；N electrode diffusion layer, is formed in the obstruction layer upper surface, and the N electrode diffusion layer has N bore region；Passivation layer, shape
Barrier layer upper surface described in Cheng Yu, the passivation layer have the first reserved area and the second reserved area, first trough
Domain corresponds to the P electrode region；Electrode layer is formed in the passivation layer upper surface.Wherein, first reserved area, second
Reserved area includes preset identification information.
Preferably, first reserved area and the second reserved area depth are 2000-15000 μm.
Preferably, first reserved area and the second reserved area include letter, number, figure and symbol therein one
The identification information of kind or a variety of compositions.
Preferably, the electrode layer includes P-type electrode and N-type electrode, is formed in the passivation layer upper surface, and described first
Reserved area is set to P electrode region, and second reserved area is set to N electrode region, for distinguishing electrode.Described first
The depth of reserved area is until transparency conducting layer or mirror layer, the depth of second reserved area are until N electricity
Pole diffusion layer.
As described above, a kind of identification chip and preparation method thereof of the invention, has the advantages that
(1) it is formed not in such a way that burn into etches or removes in the barrier layer of identification chip, diffusion layer or passivation layer
Same reserved area, specific identification information can be carried in chip, to realize identification function.
(2) by setting product information or company's information (for example, LOG of company) for the information of reserved area, in this way
It can not only allow the user different type of identification chip and manufacturer etc. easily, but also product brand identification can be increased
Degree.
(3) by the way that reserved area to be set to the specific position in Different electrodes region, to realize to chip Different electrodes
Mark, can with it is more intuitive it is more effective distinguish chip P electrode and N electrode, make it be suitable for various chips, facilitate chip
Figure identification is carried out in production, testing process, significantly improves chip resolution and production efficiency, reduces rejection rate and is produced into
This.
(4) by setting anti-counterfeiting information (such as product coding) for the information of reserved area, since the anti-counterfeiting information is held
It is loaded in the inside of chip, so that fake producer is difficult to copy easily, the antiforge function of chip may be implemented.
(5) N electrode diffusion layer is made, the electrical property for N bore region is drawn, and increases electric current in the diffusion of luminescent layer.
Detailed description of the invention
The identification chip structure that Fig. 1-13 is shown as presenting in the production method of identification chip of the present invention according to each step is shown
It is intended to.
Figure 14 is shown as each layer distribution schematic diagram of identification chip of the invention.
Component label instructions
| 101 | Growth substrates |
| 102 | Light emitting epitaxial layer |
| 103 | Transparency conducting layer |
| 104 | Mirror layer |
| 105 | Barrier layer |
| 106 | N electrode diffusion layer |
| 107 | Passivation layer |
| 108 | Electrode |
| 2011-2013 | Cutting Road region |
| 2021-2023 | N bore region |
| 2031-2032 | P bore region |
| 301-305 | Photoresist layer |
| 401 | First reserved area |
| 402 | Second reserved area |
| 501-502 | Electrode zone |
| S1~S7 | Step |
Specific embodiment
Illustrate embodiments of the present invention below by way of preset specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Fig. 1 is please referred to 14.It should be noted that diagram provided in the present embodiment only illustrates this hair in a schematic way
Bright basic conception, only shown in schema then with related component in the present invention rather than component count when according to actual implementation,
Shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its component
Being laid out kenel may also be increasingly complex.
Embodiment one
As shown in figures 1-13, the present invention provides a kind of production method of LED identification chip, and production method includes at least following
Step:
As shown in Figure 1, step S1 is first carried out, a growth substrates 101 are provided, and in the upper surface shape of growth substrates 101
At a light emitting epitaxial layer 102.In the present embodiment, growth substrates 101 can be sapphire (Al2O3), light emitting epitaxial layer 102 includes
N-GaN light emitting epitaxial layer.Then step S2 is executed.
As depicted in figs. 1 and 2, in step s 2, transparency conducting layer 103 is formed in 102 upper surface of light emitting epitaxial layer.It is first
First, as shown in Figure 1, forming a transparency conducting layer 103 using vapor deposition or sputtering technology on 102 surface of light emitting epitaxial layer.Then, exist
Electrically conducting transparent forms a photoresist layer 301 on 103 layer by layer, in defining the first Cutting Road region on photoresist layer 301 respectively
2011 and the first N bore region 2021, and remove by way of development 2011 He of the first Cutting Road region in photoresist layer 301
First N bore region 2021.In the present embodiment, number >=2 of N bore region, and at least a N bore region is located at P electrode region.
Then, 2 μm~5 μm in the remaining photoresist layer 301 to photoresist layer 301 of excessive corrosion are carved using ICP dry method
The first Cutting Road region 2011 and the first N bore region 2021 are lost until exposing light emitting epitaxial layer 102, and continue 1 μm of etching downwards
~2 μm.Finally, as shown in figure 3, removal photoresist layer 301 obtains transparency conducting layer 103.Transparency conducting layer in the present embodiment
103 can be ITO layer.Then step S3 is executed.
As shown in Figure 4 and Figure 5, in step s3, mirror layer 104 is formed in 103 upper surface of transparency conducting layer.It is specific next
It says, firstly, spin coating, coating form a photoresist layer 302, as shown in figure 4, in defining mirror layer area on photoresist layer 302
Domain, mirror layer region are formed by the region in addition to the second Cutting Road region 2012 and the 2nd N bore region 2022.Then, lead to
The mode for crossing development removes the photoresist in mirror layer region, exposed portion transparency conducting layer 103.Then, using being deposited or splash
It penetrates technique and forms mirror layer 104, and by the second Cutting Road region 2012 and the 2nd N bore region by way of metal-stripping
2022 metal-stripping removal.Finally, as shown in figure 5, obtaining mirror layer 104, wherein the second Cutting Road region 2012 and the
Two N bore regions 2022 distinguish exposed portion transparency conducting layer 103 and part light emitting epitaxial layer 102.Reflecting mirror in the present embodiment
Layer 104 is the mirror layer of P diffusion layer.Then step S4 is executed.
As shown in Figure 6 and Figure 7, in step s 4, a barrier layer 105 is formed in 104 upper surface of mirror layer.It is specific next
It says, deposits barrier layer 105 in 104 upper surface of mirror layer first, a photoresist layer 303 is then applied, as shown in fig. 6, in light
The 3rd N bore region 2023 and the first P bore region 2031 are defined on photoresist layer 303.Then, third is removed by way of development
The photoresist of N bore region 2023 and the first P bore region 2031, exposed portion barrier layer 105.Then, by corroding or etching
Mode removes the 3rd N bore region 2023 and the first P bore region 2031 in barrier layer, wherein the distribution of the 3rd N bore region exposed division
Light epitaxial layer 102, the mirror layer 104 of 2031 exposed portion P diffusion layer of the first P bore region.Finally, as shown in fig. 7, removal light
Photoresist 303 obtains barrier layer 105.In the present embodiment, barrier layer 105 can be SiO2Barrier layer.Then step S3 is executed.
As shown in Figure 8 and Figure 9, in step s 5, N electrode diffusion layer 106 is formed in 105 upper surface of barrier layer.It is specific next
It says, firstly, spin coating covers to form a photoresist layer 304, as shown in figure 8, in defining third Cutting Road region on photoresist layer
2013 and the 2nd P bore region 2032.Then, N diffusion layer 106 is formed using vapor deposition or sputtering technology, and passes through metal-stripping
Mode removes the metal-stripping of third Cutting Road region 2013 and the 2nd P bore region 2032.Finally, as shown in figure 9, obtaining N
Electrode diffusion layer 106.Wherein, 2013 exposed portion barrier layer 105 of third Cutting Road region, 2032 exposed division of the 2nd P bore region
Divide the mirror layer 104 and partial barrier 105 of P diffusion layer.N electrode diffusion layer in the present embodiment is used for the electrical property of n-quadrant
It draws, increases electric current in the diffusion of luminescent layer.Then step S3 is executed.
As shown in Figure 10 and Figure 11, in step s 6, a passivation layer 107 is formed in 106 upper surface of N electrode diffusion layer.Tool
For body, first in depositing a passivation layer 107, then spin coating, covering one photoresist layer 305 of formation on N electrode diffusion layer 106, such as
Shown in Figure 10, in defining the first reserved area 401 and the second reserved area 402 on photoresist layer, in the present embodiment, it is located at P
First reserved area of electrode zone 501 is the shape of alphabetical " P ", and the second reserved area positioned at N electrode region 502 is letter
The shape of " N ".Then, the photoresist of reserved area 401 and 403 is removed by way of development.Then, by corroding or etching
Mode remove the reserved area 401 and 402 of passivation layer 107.Finally, as shown in figure 11, removing photoresist layer 305, obtain blunt
Change layer 107, wherein the first reserved area 401 positioned at P electrode region 501 exposes mirror layer 104, is located at N electrode region
502 the second reserved area 402 exposes the pole N diffusion layer 106.The material of passivation layer 107 in the present embodiment can for silica,
Silicon nitride or silicon oxynitride.Then step S7 is executed.
As shown in Figure 12 and Figure 13, in the step s 7, electrode 108, the first reserved area are formed in 107 upper surface of passivation layer
401 are set to P electrode region 501, and the second reserved area 402 is set to N electrode region 501, for distinguishing electrode.It is specific next
It says, firstly, spin coating, covering form a photoresist layer 306, as shown in figure 3, in defining P-type electrode region on photoresist layer 306
501 and N-type electrode region 502.Then, the photoresist of electrode zone, evaporation metal are removed by way of development.The present embodiment
In, metal fills the first reserved area 401 and connect to form P-type electrode with p scattered reflection mirror layer 104；Metal filling second is reserved
Region 402 connect to form N-type electrode with the pole N diffusion layer 106, wherein the pole N diffusion layer passes through the N of N bore region and light emitting epitaxial layer
The connection of type layer.Finally, removing the metal other than electrode zone 501 and 502 by way of metal-stripping, metal electrode is obtained
108。
Electrode material can be Au, CrAu etc..It is noted that since the depth of reserved area in chip has 2000-
15000 μm, therefore in subsequent evaporation metal electrode, it can also show that reserved area, reserved area are enough on metal electrode
Difference in height guarantees to form visual pattern.By the way that reserved area to be set to the specific position in Different electrodes region, so as to
Realize the purpose of difference chip electrode.As shown in figure 14, in 502 Reference character of N-type electrode region " N ", in P-type electrode region
501 Reference characters " P " can make it to be suitable for various chips with the more intuitive more effective P electrode and N electrode for distinguishing chip,
Facilitate chip production, carry out figure identification in testing process, significantly improve chip resolution and production efficiency, reduce rejection rate and
Production cost.
It is noted that the first reserved area and the second reserved area include that letter, number, figure or symbol are therein
The identification information of one or more compositions is used for tagging chip, not to be illustrated as limiting.Moreover, the position of reserved area setting
Its position in each layer of chip can be determined according to actual needs, for example, when identification information is mainly used for the identification of chip
When, then the setting of reserved area do not need it is corresponding with electrode, as long as design convenient for identification position.Passing through will
The information of reserved area be set as product information or company's information (for example, LOG of company) and design chip barrier layer, expand
One or more layers dissipated in layer and passivation layer forms different reserved areas, not only can increase product brand resolution,
It allows the manufacturer of user's identification chip easily, and the antiforge function of chip may be implemented.In addition, the present invention can not only be
One or more layers in the barrier layer of identification chip, diffusion layer and passivation layer forms different reserved areas, can also be according to core
The difference of piece, chip it is any one or more layers (for example, one layer or more in substrate, light emitting epitaxial layer and transparency conducting layer
Layer) reserved area comprising identification information is formed, specific identification information is carried in chip.
Embodiment two
The present invention also provides a kind of identification chips, and as shown in figure 14, identification chip 1 includes: growth substrates 101, shine outer
Prolong layer 102, transparency conducting layer 103, mirror layer 104, barrier layer 105, N electrode diffusion layer 106, passivation layer 107, electrode 108.
It for ease of understanding, please be referring again to Fig. 1 to Figure 14, as shown, identification chip includes:
Growth substrates 101, in the present embodiment, growth substrates 101 can be sapphire (Al2O3), silicon (Si) or silicon carbide
One of (SiC).
Light emitting epitaxial layer 102 is formed in 101 upper surface of growth substrates.In the present embodiment, light emitting epitaxial layer 102 includes N-
GaN light emitting epitaxial layer.The the first Cutting Road region 2011 and the first N bore region 2021 that light emitting epitaxial layer 102 has, at least 1
One N bore region 2021 is located in P electrode region.
Transparency conducting layer 103, is formed in 102 upper surface of light emitting epitaxial layer, and in the present embodiment, transparency conducting layer 103 can be with
For ITO layer.Transparency conducting layer 103 has the first Cutting Road region 2011 and the first N bore region 2021.
Mirror layer 104 is formed in 103 upper surface of transparency conducting layer, and mirror layer 104 has mirror layer region, instead
Mirror layer region is penetrated to be formed by the region in addition to the second Cutting Road region 2012 and the 2nd N bore region 2022.Second Cutting Road area
The area 2011 in the first Cutting Road of area ratio region in domain 2012 is big.In the present embodiment, barrier layer 105 can be SiO2Stop
Layer.Mirror layer 104 in the present embodiment can be reflecting mirror P diffusion layer.First N bore region 2021 is located in the 2nd N porose area
In domain 2022.
Barrier layer 105, is formed in 104 upper surface of mirror layer, and barrier layer 105 has the 3rd N bore region 2023 and the first P
Bore region 2031.3rd N bore region 2023 is located in the first N bore region 2021.In the present embodiment, barrier layer 105 can be
SiO2Barrier layer.In the present embodiment, N bore region is two circular grooves for being located at P electrode region and N electrode region, deep
Degree for until transparency conducting layer or mirror layer,.
N electrode diffusion layer 106 is formed in 105 upper surface of barrier layer, and N electrode diffusion layer 106 has and the 2nd P bore region
2032.In the present embodiment, P bore region is the rectangular recess positioned at P electrode region.First P bore region 2031 is located at the 2nd hole P
In region 2032.
Passivation layer 107, is formed in 106 upper surface of N electrode diffusion layer, the passivation layer have the first reserved area 401 and
Second reserved area 402, the corresponding P bore region of the first reserved area 401, the first reserved area 401 are located at the first P bore region 2031
It is interior.Second reserved area 403 is located in N-type electrode region 502, and shape is the shape of alphabetical " N ".Passivation layer in the present embodiment
107 can be SiO2Passivation layer.
Metal electrode 108 is respectively formed P-type electrode and N-type electrode in 501 He of electrode zone of 107 upper surface of passivation layer
502, the first reserved area 401 and the second reserved area 402 are set to corresponding with P-type electrode 501 and N-type electrode region 502
Specific position.
It is noted that the first reserved area and the second reserved area and for distinguish realize chip identification function or
When antiforge function, not to be illustrated as limiting, the position of reserved area setting can determine according to actual needs, can be located at
One or more layers in each layer of chip.
In conclusion (1) present invention in the barrier layer of identification chip, diffusion layer or passivation layer by burn into etch or
The mode of removing forms different reserved areas, specific identification information can be carried in chip, to realize the knowledge of chip
Other function.(2) by setting product information or company's information (for example, LOG of company) for the information of reserved area, so not
It can only allow the user different type of identification chip and manufacturer easily, and product brand resolution can be increased.(3)
It, can be with to realize to the marks of chip Different electrodes by the way that reserved area to be set to the specific position in Different electrodes region
The more intuitive more effective P electrode and N electrode for distinguishing chip, makes it to be suitable for various chips, facilitates chip production, detection stream
Figure identification is carried out in journey significantly improves chip resolution and production to differentiate the correct position of chip and board is guided to act
Efficiency reduces rejection rate and production cost.(4) by setting anti-counterfeiting information (such as coding) for the information of reserved area, by
It is carried on the inside of chip in the anti-counterfeiting information, so that fake producer is difficult to copy easily, the antiforge function of chip may be implemented.
(5) N electrode diffusion layer is made, the electrical property for N bore region is drawn, and increases electric current in the diffusion of luminescent layer.
So the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (8)
1. a kind of production method of identification chip, which is characterized in that the production method the following steps are included:
1) epitaxial structure is provided, in forming barrier layer on the epitaxial structure, and forms N bore region in the barrier etch
With P bore region；
2) N electrode diffusion layer is made, the electrical property for N bore region is drawn；
3) growth of passivation layer performs etching the passivation layer to form the first reserved area and the second reserved area, described first
Reserved area corresponds to the P bore region；
Wherein, first reserved area and the second reserved area include preset identification information.
2. a kind of production method of identification chip according to claim 1, it is characterised in that: first reserved area and
Second reserved area depth is 2000-15000 μm.
3. a kind of production method of identification chip according to claim 1, it is characterised in that: first reserved area and
Second reserved area includes letter, number and figure is one such or the identification information of a variety of compositions.
4. a kind of production method of identification chip according to claim 1, it is characterised in that: after step 3), also wrap
It includes the following steps: forming electrode on the passivation layer, first reserved area is set to P electrode region, and described second is pre-
Region is stayed to be set to N electrode region, for distinguishing electrode.
5. a kind of production method of identification chip according to claim 1, it is characterised in that: first reserved area
Depth is until transparency conducting layer or mirror layer, the depth of second reserved area are until the N electrode diffusion layer.
6. a kind of production method of identification chip according to claim 1, it is characterised in that: step 3) comprising steps of
3-1) photoresist is coated in the passivation layer surface；
Processing 3-2) is patterned to the photoresist；
3-3) passivation layer is performed etching to form the first reserved area and the second reserved area according to patterned photoresist.
7. a kind of production method of identification chip according to any one of claims 1 to 6, which is characterized in that the epitaxy junction
The production method of structure the following steps are included:
One growth substrates 1-1) are provided, form light emitting epitaxial layer over the substrate；
1-2) in forming transparency conducting layer on the light emitting epitaxial layer, Cutting Road region and N bore region, at least one are then etched
N bore region is located at P electrode region；
1-3) in making mirror layer on the transparency conducting layer.
8. a kind of production method of identification chip according to claim 7, it is characterised in that: step 1-2) in, the hole N
The depth in region is the N-type layer until the light emitting epitaxial layer.
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| CN1270416A (en) * | 1999-04-08 | 2000-10-18 | 株式会社日立制作所 | Manufacture of semiconductor device |
| CN102279195A (en) * | 2011-04-18 | 2011-12-14 | 首雷光电科技(厦门)有限公司 | LED chip appearance visual inspection method |
| CN103390604A (en) * | 2012-05-10 | 2013-11-13 | 瑞萨电子株式会社 | Semiconductor device manufacturing method and semiconductor device |
| CN205194732U (en) * | 2015-11-02 | 2016-04-27 | 上海博恩世通光电股份有限公司 | Recognition chip |
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| JP5007529B2 (en) * | 2006-06-22 | 2012-08-22 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
| KR20120032305A (en) * | 2010-09-28 | 2012-04-05 | 삼성엘이디 주식회사 | Semiconductor light emitting diode chip, method of fabricating the chip and method for quality control of the chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1270416A (en) * | 1999-04-08 | 2000-10-18 | 株式会社日立制作所 | Manufacture of semiconductor device |
| CN102279195A (en) * | 2011-04-18 | 2011-12-14 | 首雷光电科技(厦门)有限公司 | LED chip appearance visual inspection method |
| CN103390604A (en) * | 2012-05-10 | 2013-11-13 | 瑞萨电子株式会社 | Semiconductor device manufacturing method and semiconductor device |
| CN205194732U (en) * | 2015-11-02 | 2016-04-27 | 上海博恩世通光电股份有限公司 | Recognition chip |
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