CN105097481A - Packaging method of semiconductor device - Google Patents
Packaging method of semiconductor device Download PDFInfo
- Publication number
- CN105097481A CN105097481A CN201410166682.3A CN201410166682A CN105097481A CN 105097481 A CN105097481 A CN 105097481A CN 201410166682 A CN201410166682 A CN 201410166682A CN 105097481 A CN105097481 A CN 105097481A
- Authority
- CN
- China
- Prior art keywords
- wafer
- weld pad
- present
- soldered ball
- film
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Abstract
The invention provides a packaging method of a semiconductor device. The packaging method comprises that a wafer is provided, and a bonding pad is formed at the front side of the wafer; the front side of the wafer is covered with a protective film; the back of the wafer is ground; the protective film is removed; and a solder ball is provided and arranged on the bonding pad. The packaging method of the invention can improve the uniformity of a printing layer at the back side of the wafer, and reduce the production cost.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly relate to a kind of method for packing of semiconductor device.
Background technology
Wafer stage chip encapsulation (WaferLevelChipScalePackaging, be called for short WLCSP), be different from traditional chip package mode (first to cut and seal survey again, and after encapsulation, at least increase the volume of former chip 20%), this kind of state-of-the-art technology first on full wafer wafer, carries out packaging and testing, then IC particle one by one is just cut into, the volume therefore after the encapsulation i.e. life size of the equivalent naked crystalline substance of IC.The packaged type of WLCSP, not only reduces the size of package module on the one hand significantly, and meets the high density demand of current all kinds of device for body space; On the other hand in the performance of usefulness, more improve speed and the stability of transfer of data.
Figure 1A-1F shows wafer in prior art to carry out WLCSP and encapsulates the step comprised: first, as shown in Figure 1A, wafer 100 is provided, described wafer 100 surface has been formed with under-bump metallization (UBM) structure 101, soldered ball 102 is provided, soldered ball 102 correspondence is arranged on UBM layer 101.Then, as shown in Figure 1B, perform reflow soldering process step, melting soldered ball 102 is electrically connected with UBM structure to make it.Then, as shown in Figure 1 C, ultraviolet (UV) film 103 is pasted, with protection device in wafer frontside.Then, as shown in figure ip, wafer back part grinding is carried out, by the size of grinding wafer to technological requirement.Then, as referring to figure 1e, adopt UV-irradiation to remove the viscosity between ultraviolet film and wafer, remove ultraviolet film.Then, coating and the solidification of wafer back part epoxy resin layer 104 is carried out as shown in fig. 1f.
For WLCSP product, due to the tolerance of size of solder ball often have ± 15 μm, and the tolerance of the back up layer of terminal client demand be only ± 5 μm, the tolerances of the soldered ball uniformity of back up layer, thus have impact on the qualification rate of product greatly.Simultaneously due to the existence of crystal column surface soldered ball, and the height of ball is up to 300 μm, so the device of UV film to wafer frontside that cost must be adopted higher when carrying out wafer back part grinding is protected, this also brings very large challenge to cost.The generation of these problems all because wafer has completed the processing procedure in front, thus causes uncontrollability and the cost increase of backside process.
Therefore, in order to solve the problems of the technologies described above, be necessary to propose a kind of new method for packing.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
In order to solve problems of the prior art, the present invention proposes a kind of method for packing of semiconductor device, comprising the following steps: to provide wafer, described wafer frontside is formed with weld pad; At described wafer frontside covered with protective film; Carry out wafer back part grinding technics; Remove described diaphragm; Soldered ball is provided, described soldered ball is positioned on described weld pad.
Further, before being positioned on described weld pad by described soldered ball, be also included in described wafer rear cover ring epoxy layer, and the step be cured.
Further, after being positioned on described weld pad by described soldered ball, also comprise the step performing reflow soldering process.
Further, described diaphragm is selected from ultraviolet film or blue film.
Further, described weld pad is under-bump metallization structure.
To sum up, according to method for packing of the present invention, the uniformity of wafer rear printed layers can be improved, also can reduce production cost simultaneously.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A-Fig. 1 F is that in prior art, wafer carries out the schematic diagram that WLCSP encapsulates the step corresponding construction comprised;
The schematic diagram of the structure that the step that the method that Fig. 2 A-Fig. 2 F is exemplary embodiment of the present is implemented successively obtains respectively;
Fig. 3 is the flow chart of step implemented successively of method according to an exemplary embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to explain the manufacturing process of the present invention of the present invention's proposition.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
[exemplary embodiment]
Below in conjunction with accompanying drawing, the present invention is described in more detail, wherein denotes the preferred embodiments of the present invention, should be appreciated that those skilled in the art can modify the present invention described here, and still realize advantageous effects of the present invention.
First, as shown in Figure 2 A, provide wafer 200, described wafer frontside is formed with weld pad 201, at described wafer 200 front covered with protective film 202.
Described wafer 200 is made up of Semiconductor substrate and device, and the material of Semiconductor substrate is monocrystalline silicon, also can be other substrates such as isolate supports or stress silicon.Described device passes through the interconnected integrated circuit formed of alloy by several metal-oxide semiconductor fieldeffect transistors (MOSFETs) and other devices such as electric capacity, resistance, also can be semiconductor device common in other integrated circuit fields, such as bipolar device or power device etc.
Described weld pad 201 is electric conducting material, use PVD, CVD, sputtering, metallide, electrodeless plating technique or other suitable metal deposition process on wafer, form weld pad 201, as an example, weld pad can be under-bump metallization (UBM) structure, can be one or more layers Ti, TiW, NiV, Cr, CrCu, Al, Cu, Sn, Ni, Au, Ag or other suitable electric conducting material.As an example, under-bump metallization (UBM) structure can form by the multiple layer metal of adhesion layer, barrier layer and seed or wetting layer is stacking.UBM structure contributes to the diffusion prevented between soldered ball and the integrated circuit of multi-chip semiconductor device, provides low-resistance electrical connection simultaneously.
At described wafer frontside covered with protective film 202, described diaphragm is used for providing protection to wafer frontside circuit in wafer back part process of lapping.Described diaphragm is selected from ultraviolet (UV) film or blue film, the present embodiment, preferred blue film.Because the cost of UV film is relatively high, and adopt at this blue film that bondline thickness is thinner, wafer back part grinding technics requirement in successive process can be met.Blue film paste employing prior art, do not repeat at this.
Then, as shown in Figure 2 B, wafer back part grinding technics is carried out.
According to package dimension requirement, thinned wafer thickness is to chip given size, and in the present embodiment, adopt the thinning described wafer thickness of mechanical lapping, due to same as the prior art, therefore not to repeat here.
Then, as shown in Figure 2 C, wafer frontside diaphragm is removed.
UV film, under UV-irradiation, loses viscosity and is easy to peel off.And the stripping of blue film needs to use membrane removal machine to coordinate roller and striping adhesive tape to be peeled off by blue film.Above-mentioned steps adopts prior art, does not repeat at this.
Then, as shown in Figure 2 D, in wafer rear cover ring epoxy layer 203, and be cured.
Adopt typography, liquid-state epoxy resin is evenly coated on whole wafer rear, is cured step afterwards, utilize Ultraviolet radiation or heat treated with the above-mentioned epoxy resin (epoxy) that hardens.
Then, as shown in Figure 2 E, provide soldered ball 204, soldered ball 204 is positioned on weld pad 201.
To choose the soldered ball 204 matched with weld pad, correspondence is positioned on weld pad 201, and this process is called plants ball, and the method for planting ball or can be planted ball device and plants ball for implant ball, and preferably plant ball device and plant ball, above process is prior art, and therefore not to repeat here.It is worth mentioning that, the present invention only carries out generality explaination for soldered ball, so soldered ball mentioned is here not limited to strict spherical scolding tin, it can also be scolding tin or the metal coupling of other shape.
Then, as shown in Figure 2 F, reflow soldering process step is performed.
Perform reflow soldering process step, melting soldered ball 204 is electrically connected with weld pad 201 to make it.As an example, the temperature range of Reflow Soldering is 200 DEG C ~ 260 DEG C.
Rearmounted planting ball technique according to the embodiment of the present invention, epoxy resin layer printing tolerance by the impact of UBM structure, and the tolerance of UBM structure only ± 1um, thus the impact avoiding ball high, effectively can improve the uniformity of epoxy resin layer.In addition, prior art carries out the mode of wafer back part grinding after adopting and first planting ball, so the UV film that bondline thickness must be adopted thicker is to protect the front of wafer.And the embodiment of the present invention is rearmounted planting ball, the blue film that bondline thickness can be adopted thinner when carrying out wafer back part grinding, thus reduce the use cost of film.
With reference to Fig. 3, the flow chart of the step that the method according to an exemplary embodiment of the present invention that illustrated therein is is implemented successively, for schematically illustrating the flow process of whole manufacturing process.
In step 301, provide wafer, described wafer frontside is formed with weld pad, at wafer frontside covered with protective film;
In step 302, wafer back part grinding technics is carried out;
In step 303, wafer frontside diaphragm is removed;
In step 304, in wafer rear cover ring epoxy layer, and be cured;
In step 305, provide soldered ball, soldered ball is positioned on weld pad;
Within step 306, reflow soldering process step is performed.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (5)
1. a method for packing for semiconductor device, comprising:
There is provided wafer, described wafer frontside is formed with weld pad;
At described wafer frontside covered with protective film;
Carry out wafer back part grinding technics;
Remove described diaphragm;
Soldered ball is provided, described soldered ball is positioned on described weld pad.
2. the method for claim 1, is characterized in that, before being positioned on described weld pad by described soldered ball, be also included in described wafer rear cover ring epoxy layer, and the step be cured.
3. the method for claim 1, is characterized in that, also comprises the step performing reflow soldering process after being positioned on described weld pad by described soldered ball.
4. the method for claim 1, is characterized in that, described diaphragm is selected from ultraviolet film or blue film.
5. the method for claim 1, is characterized in that, described weld pad is under-bump metallization structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410166682.3A CN105097481A (en) | 2014-04-24 | 2014-04-24 | Packaging method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410166682.3A CN105097481A (en) | 2014-04-24 | 2014-04-24 | Packaging method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105097481A true CN105097481A (en) | 2015-11-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410166682.3A Pending CN105097481A (en) | 2014-04-24 | 2014-04-24 | Packaging method of semiconductor device |
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| CN (1) | CN105097481A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110021548A (en) * | 2019-04-03 | 2019-07-16 | 江苏纳沛斯半导体有限公司 | A kind of technique reducing chip cutting edge chipping |
| CN111755342A (en) * | 2020-06-18 | 2020-10-09 | 宁波芯健半导体有限公司 | Method for packaging wafer-level chip |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59119747A (en) * | 1982-12-25 | 1984-07-11 | Fujitsu Ltd | Manufacture of semiconductor device |
| US6060373A (en) * | 1998-07-10 | 2000-05-09 | Citizen Watch Co., Ltd. | Method for manufacturing a flip chip semiconductor device |
| CN1270416A (en) * | 1999-04-08 | 2000-10-18 | 株式会社日立制作所 | Manufacture of semiconductor device |
| JP2011159694A (en) * | 2010-01-29 | 2011-08-18 | Hitachi Chem Co Ltd | Method of manufacturing semiconductor device, semiconductor device obtained thereby, and dicing film integrated type chip protective film used therefor |
| CN102194761A (en) * | 2010-03-17 | 2011-09-21 | 台湾积体电路制造股份有限公司 | Manufacturing method of residue-free wafer |
-
2014
- 2014-04-24 CN CN201410166682.3A patent/CN105097481A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59119747A (en) * | 1982-12-25 | 1984-07-11 | Fujitsu Ltd | Manufacture of semiconductor device |
| US6060373A (en) * | 1998-07-10 | 2000-05-09 | Citizen Watch Co., Ltd. | Method for manufacturing a flip chip semiconductor device |
| CN1270416A (en) * | 1999-04-08 | 2000-10-18 | 株式会社日立制作所 | Manufacture of semiconductor device |
| JP2011159694A (en) * | 2010-01-29 | 2011-08-18 | Hitachi Chem Co Ltd | Method of manufacturing semiconductor device, semiconductor device obtained thereby, and dicing film integrated type chip protective film used therefor |
| CN102194761A (en) * | 2010-03-17 | 2011-09-21 | 台湾积体电路制造股份有限公司 | Manufacturing method of residue-free wafer |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110021548A (en) * | 2019-04-03 | 2019-07-16 | 江苏纳沛斯半导体有限公司 | A kind of technique reducing chip cutting edge chipping |
| CN110021548B (en) * | 2019-04-03 | 2020-09-11 | 江苏纳沛斯半导体有限公司 | Process for reducing edge breakage of chip cutting edge |
| CN111755342A (en) * | 2020-06-18 | 2020-10-09 | 宁波芯健半导体有限公司 | Method for packaging wafer-level chip |
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Application publication date: 20151125 |
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