CN101807511B - method for horizontal chip-level package of laser marking wafer - Google Patents
method for horizontal chip-level package of laser marking wafer Download PDFInfo
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- CN101807511B CN101807511B CN 200910004152 CN200910004152A CN101807511B CN 101807511 B CN101807511 B CN 101807511B CN 200910004152 CN200910004152 CN 200910004152 CN 200910004152 A CN200910004152 A CN 200910004152A CN 101807511 B CN101807511 B CN 101807511B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Abstract
The invention discloses a wafer horizontal chip-level package and a method for identifying package by laser. The method comprises the following steps: forming a plurality of semiconductors on the front surface of a wafer, metallizing a device contact on the front surface of the wafer, grinding the back of the wafer, etching the back of the wafer, identifying the back of the wafer by laser, performing oxide etch on the back of the wafer, depositing a metal layer on the back of the wafer, and cutting the wafer into a plurality of wafer horizontal chip-level packages. Each wafer horizontal chip-level package comprises an identifier formed on the back of the wafer horizontal chip-level package. The identifier comprises a plurality of grooves formed on the back of silicon and nicks correspondingly formed on the metal layer which covers the back.
Description
Technical field
The present invention relates on the surface of semiconductor packages, be provided with the method for identification marking, special, the present invention relates to the method for wafer horizontal chip-level encapsulation and this encapsulation of laser-marking.
Background technology
Product information (for example product type, pin one position and distinguishing mark) generally is to provide through the method for on the flat surface of wafer-level package (CSP), doing sign.CSP for using the chip level encapsulation technology to make typically uses printing ink or laser these signs to be indicated in the back side of chip.
Publication No. is that 2004/0188860 United States Patent (USP) discloses a kind of example that uses printing ink sign product information.Wafer-level package comprises a printing ink sign of printing and being solidificated in the CSP back side.Though owing to this method can not cause any infringement to be called as " nondestructive " to the back side,, this printing ink identifies lasting and possibly in CSP processing procedure subsequently, be damaged, and is when being printed on the smooth surface when printing ink identifies especially.
Laser marking method can provide durable sign, and identification marking can be formed directly on the silicon layer at the back side, and perhaps indirect being formed on is arranged on the level on the silicon layer at the back side.The patent No. is the example that discloses direct sign in 6248973,6261919,6374834,6596965 the United States Patent (USP).The patent No. is the example that discloses indirect sign in 5610104,6023094,6683637 the United States Patent (USP).
Known laser-marking technology can not well be applicable to the wafer-level CSP with metal layer on back (backmetal), power MOSFET for example, the especially inapplicable common drain MOSFET that is used for battery protecting apparatus.The direct sign at this type of MOSFET back side has been cut off back metal, and the transverse current that flows through back metal is had adverse effect, and has increased its resistance.
The indirect sign of on coating that is applied to the MOSFET back side or film, carrying out can not have a negative impact to the electrical property of chip.Yet, because the different mechanical performances of various compositions in the sandwich (silicon/metal/organic film) at the back side have caused the little bits that in the wafer cutting process, produce.In addition, application of coatings or film have increased the cost of wafer-level CSP manufacturing process.Additive method needs special equipment, perhaps handles for ease and the thicker wafer of needs, and is not suitable for LED reverse mounting type.
In view of the limitation of prior art, therefore, need a kind of laser-marking to have the method for the wafer-level CSP of back metal technically.
Summary of the invention
Laser-marking of the present invention has the method for the wafer-level CSP of back metal, through continuous, a unspoiled metal layer on back are provided, has overcome the shortcoming of prior art.After laser-marking is carried out at the back side of exposed silicon wafer, again wafer is carried out back face metalization, just guaranteed the continuity of metal layer on back.
According to an aspect of the present invention, wafer-level CSP comprises the laser-marking that is formed on its back side, and this laser-marking is to utilize groove that is formed on the silicon wafer back side and the corresponding indentation (indentation) that is formed on the metal level that covers the back side to form.
According to another aspect of the present invention, the method for the laser-marking wafer-level CSP front surface that is included in wafer forms the several semiconductor device, after the back side of the back side of laser-marking wafer after the back of the back side of the front surface metallization device contacts of wafer, grinding wafers, silicon etched wafer, the silicon etch steps, silicon etch steps rear oxidation etched wafer, oxide etch step, cuts into the step of wafer horizontal chip-level encapsulation at the chip back surface depositing metal layers with wafer.
For the following detailed description of the present invention of better understanding, for a better understanding of the present invention for the contribution of prior art, listed the key character of this invention roughly.Certainly, also will be at the following additional technical feature that is described to this invention, this additional technical feature has constituted the theme of Rights attached thereto requirements.
Like this, before introducing at least one embodiment of the present invention in detail, should be appreciated that this invention is not limited to the details and the compound mode of these functional form elements in following description or the accompanying drawing in application.This invention can have other execution mode, and can accomplished in various ways and completion.And should be appreciated that technical term used herein and expression way, and summary all are in order to describe the present invention, not to be understood that it is limitation of the present invention.
Therefore, those of ordinary skill in the art will understand, this open institute based on thought can be used as the basis of the method and system of other realization the object of the invention.Therefore, claims can be regarded as and comprise that those equivalent structures of not violating the spirit and scope of the present invention are within its scope.
Description of drawings
After the detailed description of reading below in conjunction with accompanying drawing, for the person of ordinary skill of the art, the object of the invention and characteristic will be conspicuous.
Fig. 1 is through the sketch map of the chip back surface behind the grinding operation according to the present invention.
Fig. 2 is through the sketch map of chip back surface behind the silicon etching operation according to the present invention.
Fig. 3 is through the sketch map of the chip back surface after the laser-marking operation according to the present invention.
Fig. 4 is the sketch map of the chip back surface of process back metal deposition according to the present invention.
Fig. 5 is a flow chart of steps of a method in accordance with the invention.
Fig. 6 shows the partial plan of laser-induced thermal etching chip back surface according to the present invention.
Embodiment
Describe the present invention in detail below in conjunction with accompanying drawing, it makes those skilled in the art can realize this invention as embodiments of the invention.Special, following accompanying drawing and explanation do not limit the scope of the present invention.And some element of the present invention can be realized by the known device of some or all of use.In order to make the present invention more clear, only describe those necessary devices here, and will be omitted for the detailed description of those known device.In addition, the present invention includes for the device of here showing now or later equivalent.
As shown in Figure 5, laser-marking wafer horizontal chip-level method for packing 500 comprises step 510, and some semiconductor device are formed on the front surface (Fig. 1) of wafer 100 in this step.Metallization is formed on the device contacts of wafer front in step 520.In the step 530, the back side of wafer is by mechanical lapping.As the result of grinding operation, as shown in Figure 1, the silicon layer 110 of damage is formed on chip back surface.
Next the silicon layer 110 that in the silicon etching operation, damages is removed with this in the back side of etched wafer 100 in step 540.Therefore as shown in Figure 2 a very smooth back side is provided.After the silicon etching operation, the back side 120 of wafer 100 is by laser-marking in step 550.As shown in Figure 3, the result of laser-marking has caused overleaf forming on 120 some grooves 130.In step 560, carry out oxide etching and operate the Si oxide on the back side 120 of removing wafer 100, in step 570, depositing metal layers 140 (Fig. 4) on chip back surface 120.In optional step 580, optional solder ball is formed on the metallized device contacts.In step 590, wafer 100 is cut into independently wafer-level package.
As shown in Figure 4, after deposition step 570, the groove 130 that is formed on wafer 100 back sides 120 makes generation indentation 150 on the metal layer on back 140.Metal layer on back 140 is continuous, and the electric current of consistency of thickness to guarantee to flow through subsequently wherein.Visual contrast on metal in the indentation 150 and the metal level 140 between the metal of remainder provides identification capability, and the wafer horizontal chip utmost point of crossing with identification marking encapsulates.Be illustrated in figure 6 as the sign 600 that forms according to method 500.For example, laser-marking can comprise some information, corporate logo for example, product type, battery size, pin positions.
According to the present invention, the laser-marking 600 that the wafer horizontal chip-level encapsulation comprises is to utilize groove 130 that is formed on the silicon wafer back side 120 and the corresponding indentation 150 that is formed on the metal level 140 that covers the back side to form.
The typical thickness that is used for the wafer of power MOSFET manufacturing is 200 μ m, and preferably less than 300 μ m.Whole back metal thickness ranges is 0.5-10 μ m, and preferably about 2.5 μ m.The composition of metal layer on back comprises the titanium/nickel/silver/nickel of sandwich construction, titanium/nickel/silver, titanium/gold, titanium/nickel/gold, titanium/aluminium, perhaps titanium/aluminium/nickel/gold.Through the thin wafer with thicker relatively metal layer on back is provided, the resistance of MOSFET wafer horizontal chip-level encapsulation can reduce.Although specification has provided typical thickness and preferred thickness, those skilled in the art know that the method for wafer horizontal chip-level encapsulation and this encapsulation of laser-marking can realize on the wafer of any thickness.
The inventor finds that silicon etch steps 540 must be operated before laser-marking step 550.Otherwise the danger that the metal level at the back side that the serious particle pollution at the device back side will cause following peels off.In test, silicon etch steps 540 is in laser-marking step 550 back rather than before it, operate, even the optical frequency ultrasonic cleaning technology can not effectively solve the problem of particle pollution.When silicon etch steps 540 was operated behind laser-induced thermal etching step 550 rather than oxide etching, just not at the needs cleaning step, and particle pollution also was minimum.
The wafer horizontal chip-level encapsulation provides the wafer-level package with continuous metal layer on back with its laser marking method.Back face metalization behind the laser-marking on the exposed silicon layer has overleaf been guaranteed the continuity of metal level at the back.
Obviously, under the situation of scope of the present invention, above execution mode can be made a lot of modifications.And each purpose of specific embodiment all comprises the theme of patentability, and does not spend other purposes of considering same embodiment.Further, the various aspects of different embodiment can combine.Therefore, scope of the present invention should be by following claim and its legal Peer decision.
Claims (4)
1. the method for a wafer horizontal chip-level encapsulation of a laser-marking is characterized in that, may further comprise the steps:
(a) front surface at wafer forms the several semiconductor device;
(b) in wafer front metallization device contacts;
(c) back side of grinding wafers;
(d) back side of silicon etched wafer;
(e) afterwards, the back side of laser-marking wafer in step (d);
(f) afterwards, the back side of oxide etch wafer in step (e);
(g) afterwards, at metal level of backside deposition of wafer in step (f);
(h) wafer is cut into some wafer horizontal chip-level encapsulation.
2. the method for claim 1 is characterized in that, described wafer horizontal chip-level encapsulation comprises a power metal oxide semiconductor field-effect transistor.
3. the method for claim 1 is characterized in that, described wafer horizontal chip-level encapsulation comprises that leaks a power metal oxide semiconductor field-effect transistor altogether.
4. the method for claim 1 is characterized in that, this method also comprises: in step (g) afterwards, on metallized device contacts, form the step of solder ball.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910004152 CN101807511B (en) | 2009-02-13 | 2009-02-13 | method for horizontal chip-level package of laser marking wafer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910004152 CN101807511B (en) | 2009-02-13 | 2009-02-13 | method for horizontal chip-level package of laser marking wafer |
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| CN101807511A CN101807511A (en) | 2010-08-18 |
| CN101807511B true CN101807511B (en) | 2012-03-28 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1270416A (en) * | 1999-04-08 | 2000-10-18 | 株式会社日立制作所 | Manufacture of semiconductor device |
| US6448632B1 (en) * | 2000-08-28 | 2002-09-10 | National Semiconductor Corporation | Metal coated markings on integrated circuit devices |
| CN1707790A (en) * | 2004-05-27 | 2005-12-14 | 半导体元件工业有限责任公司 | Semiconductor device formed having a metal layer for conducting the device current and for high contrast marking and method thereof |
| CN101197336A (en) * | 2006-12-07 | 2008-06-11 | 育霈科技股份有限公司 | Structure and process for wl-csp with metal cover |
-
2009
- 2009-02-13 CN CN 200910004152 patent/CN101807511B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1270416A (en) * | 1999-04-08 | 2000-10-18 | 株式会社日立制作所 | Manufacture of semiconductor device |
| US6448632B1 (en) * | 2000-08-28 | 2002-09-10 | National Semiconductor Corporation | Metal coated markings on integrated circuit devices |
| CN1707790A (en) * | 2004-05-27 | 2005-12-14 | 半导体元件工业有限责任公司 | Semiconductor device formed having a metal layer for conducting the device current and for high contrast marking and method thereof |
| CN101197336A (en) * | 2006-12-07 | 2008-06-11 | 育霈科技股份有限公司 | Structure and process for wl-csp with metal cover |
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| Publication number | Publication date |
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| CN101807511A (en) | 2010-08-18 |
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