TW495803B - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
- Publication number
- TW495803B TW495803B TW089106633A TW89106633A TW495803B TW 495803 B TW495803 B TW 495803B TW 089106633 A TW089106633 A TW 089106633A TW 89106633 A TW89106633 A TW 89106633A TW 495803 B TW495803 B TW 495803B
- Authority
- TW
- Taiwan
- Prior art keywords
- region
- film
- gate electrode
- forming
- diffusion layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
-
- H10D64/0112—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19805899 | 1999-07-12 | ||
| JP2000049869A JP3963629B2 (ja) | 1999-07-12 | 2000-02-25 | 半導体装置及びその製造方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW495803B true TW495803B (en) | 2002-07-21 |
Family
ID=26510749
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW089106633A TW495803B (en) | 1999-07-12 | 2000-04-10 | Semiconductor device and method of manufacturing the same |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6251721B1 (enExample) |
| JP (1) | JP3963629B2 (enExample) |
| KR (1) | KR100658475B1 (enExample) |
| TW (1) | TW495803B (enExample) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2809183B2 (ja) * | 1996-03-27 | 1998-10-08 | 日本電気株式会社 | 半導体記憶装置の製造方法 |
| JP3472738B2 (ja) * | 1999-12-24 | 2003-12-02 | Necエレクトロニクス株式会社 | 回路製造方法、半導体装置 |
| KR100377833B1 (ko) * | 2001-06-19 | 2003-03-29 | 삼성전자주식회사 | 보더리스 콘택 구조를 갖는 반도체 장치 및 그 제조방법 |
| JP2003031684A (ja) * | 2001-07-11 | 2003-01-31 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
| KR100844936B1 (ko) * | 2002-07-19 | 2008-07-09 | 주식회사 하이닉스반도체 | 반도체소자 및 그 제조 방법 |
| US6686247B1 (en) * | 2002-08-22 | 2004-02-03 | Intel Corporation | Self-aligned contacts to gates |
| KR100618908B1 (ko) | 2005-08-12 | 2006-09-05 | 삼성전자주식회사 | 게이트 저항을 개선한 반도체 소자 및 제조 방법 |
| US8728949B2 (en) * | 2010-08-09 | 2014-05-20 | United Microelectronics Corp. | Method for fabricating a semiconductor device |
| JP2015070192A (ja) * | 2013-09-30 | 2015-04-13 | サンケン電気株式会社 | 半導体装置の製造方法、半導体装置 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5930618A (en) * | 1997-08-04 | 1999-07-27 | United Microelectronics Corp. | Method of Making High-K Dielectrics for embedded DRAMS |
| JPH1154724A (ja) * | 1997-08-06 | 1999-02-26 | Sony Corp | 半導体装置の製造方法 |
| US5966600A (en) * | 1997-11-21 | 1999-10-12 | United Semiconductor Corp. | DRAM process with a multilayer stack structure |
| US6159839A (en) * | 1999-02-11 | 2000-12-12 | Vanguard International Semiconductor Corporation | Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections |
| US6117723A (en) * | 1999-06-10 | 2000-09-12 | Taiwan Semiconductor Manufacturing Company | Salicide integration process for embedded DRAM devices |
-
2000
- 2000-02-25 JP JP2000049869A patent/JP3963629B2/ja not_active Expired - Lifetime
- 2000-04-07 US US09/545,598 patent/US6251721B1/en not_active Expired - Lifetime
- 2000-04-10 TW TW089106633A patent/TW495803B/zh not_active IP Right Cessation
- 2000-04-24 KR KR1020000021614A patent/KR100658475B1/ko not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2001085643A (ja) | 2001-03-30 |
| JP3963629B2 (ja) | 2007-08-22 |
| KR100658475B1 (ko) | 2006-12-18 |
| US6251721B1 (en) | 2001-06-26 |
| KR20010014812A (ko) | 2001-02-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GD4A | Issue of patent certificate for granted invention patent | ||
| MK4A | Expiration of patent term of an invention patent |