TW494565B - Reduction of topography between support regions and array regions of memory devices - Google Patents
Reduction of topography between support regions and array regions of memory devices Download PDFInfo
- Publication number
- TW494565B TW494565B TW090114976A TW90114976A TW494565B TW 494565 B TW494565 B TW 494565B TW 090114976 A TW090114976 A TW 090114976A TW 90114976 A TW90114976 A TW 90114976A TW 494565 B TW494565 B TW 494565B
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor device
- support
- region
- array
- height
- Prior art date
Links
- 230000009467 reduction Effects 0.000 title description 2
- 238000012876 topography Methods 0.000 title description 2
- 239000004065 semiconductor Substances 0.000 claims abstract description 47
- 230000015654 memory Effects 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims description 70
- 239000002184 metal Substances 0.000 claims description 70
- 239000003990 capacitor Substances 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 17
- 238000005516 engineering process Methods 0.000 claims description 8
- 230000008859 change Effects 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 5
- 230000007704 transition Effects 0.000 claims description 5
- 230000007423 decrease Effects 0.000 claims description 4
- 230000003247 decreasing effect Effects 0.000 claims description 3
- 238000007667 floating Methods 0.000 claims description 3
- 239000003989 dielectric material Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 230000000694 effects Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910052778 Plutonium Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 208000023414 familial retinal arterial macroaneurysm Diseases 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- OYEHPCDNVJXUIW-UHFFFAOYSA-N plutonium atom Chemical compound [Pu] OYEHPCDNVJXUIW-UHFFFAOYSA-N 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 235000012976 tarts Nutrition 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Landscapes
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US59711400A | 2000-06-20 | 2000-06-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW494565B true TW494565B (en) | 2002-07-11 |
Family
ID=24390138
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW090114976A TW494565B (en) | 2000-06-20 | 2001-06-20 | Reduction of topography between support regions and array regions of memory devices |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP1292986A2 (fr) |
| TW (1) | TW494565B (fr) |
| WO (1) | WO2001099160A2 (fr) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050070861A (ko) * | 2003-12-31 | 2005-07-07 | 동부아남반도체 주식회사 | 반도체 소자의 더미층 및 그 제조방법 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR930011462B1 (ko) * | 1990-11-23 | 1993-12-08 | 현대전자산업 주식회사 | 다층배선의 단차를 완화시키는 방법 |
| US5262353A (en) * | 1992-02-03 | 1993-11-16 | Motorola, Inc. | Process for forming a structure which electrically shields conductors |
| JP2682455B2 (ja) * | 1994-07-07 | 1997-11-26 | 日本電気株式会社 | 半導体記憶装置およびその製造方法 |
| JPH1098166A (ja) * | 1996-09-20 | 1998-04-14 | Nippon Steel Corp | 半導体記憶装置及びその製造方法 |
| JP3110328B2 (ja) * | 1996-11-19 | 2000-11-20 | 日本電気アイシーマイコンシステム株式会社 | 半導体記憶装置 |
| KR100268424B1 (ko) * | 1998-08-07 | 2000-10-16 | 윤종용 | 반도체 장치의 배선 형성 방법 |
| DE19926106C1 (de) * | 1999-06-08 | 2001-02-01 | Siemens Ag | Halbleiterspeicherbauelement mit Speicherzellen, Logikbereichen und Füllstrukturen |
-
2001
- 2001-06-20 WO PCT/US2001/019684 patent/WO2001099160A2/fr not_active Application Discontinuation
- 2001-06-20 EP EP01952175A patent/EP1292986A2/fr not_active Withdrawn
- 2001-06-20 TW TW090114976A patent/TW494565B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| WO2001099160A3 (fr) | 2002-10-17 |
| EP1292986A2 (fr) | 2003-03-19 |
| WO2001099160A2 (fr) | 2001-12-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GD4A | Issue of patent certificate for granted invention patent | ||
| MM4A | Annulment or lapse of patent due to non-payment of fees |