TW492161B - Method to increase the capacity in a memory-trench and memory-capacitor with increased capacity - Google Patents

Method to increase the capacity in a memory-trench and memory-capacitor with increased capacity Download PDF

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Publication number
TW492161B
TW492161B TW090104539A TW90104539A TW492161B TW 492161 B TW492161 B TW 492161B TW 090104539 A TW090104539 A TW 090104539A TW 90104539 A TW90104539 A TW 90104539A TW 492161 B TW492161 B TW 492161B
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Taiwan
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layer
silicon
trench
deposited
memory
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TW090104539A
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Alexander Dr Ruf
Wilhelm Kegel
Wolfram Karcher
Martin Dr Schrems
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Infineon Technologies Ag
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    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
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Description

492161 A7 _ B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（1 ) 本發明涉及一種記憶體溝渠中提高電容所用之方法及具 有較大電容之溝渠式電容器。 本發明可用在記憶體電路（例如，DRAM)及其它半導體 電路中。 在溝渠式dram記憶體模組中，電容器儲存電荷而成 爲記憶元件，其是以盆形式成在深處中。這樣不只使記憶 胞面積變小，同時使α微粒擊中記憶胞之槪率變小。此種 盆形之電容器形成在溝渠中且亦稱爲溝渠式電容器。溝渠 式記憶胞之記憶體具有溝渠，其在指定之期間中必須儲存 一種固定量之電荷。 國際競爭力之保持及提高是需要的；達成一種指定之電 子功能所需之成本將持續地下降以提高生產力。最近幾年 中提高生產力所需之保證是CMOS技術或DRAM技術。 溝渠式DRAM技術之突出之特點主要是溝渠式電容器本身 較小面積需求以及可以最高之封裝密度配置在積體電路中。 在結構持續地變小時，溝渠之直徑及其表面亦變小，使 傳統技術中只能儲存較少之電荷。 由先前技術US 5 8 76 788中已知一種製成DRAM記憶 胞之介電質用之方法。使用介電常數較大之Si3N4作爲介 電質以提高記憶體容量。使用此種介電質主要會在較小之 橫向尺寸中造成一些問題。爲了在DRAM記憶胞中直徑變 小時防止電荷之損耗，則須使溝渠被蝕刻得較深，或降低 氮化矽層之厚度。但較深之溝渠之蝕刻所顯現之缺點是較 長之處理時間及較大之製造成本。氮化矽膜之層厚度之下 (請先閱讀背面之注咅？事項再填. 裝'丨 頁： · •線· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 492161 A7 __ B7 五、發明說明（2 ) 降會使隧道效應所造成之損耗增大。 本發明之目的是提供：一種記憶體溝渠中提高電容所用 之方法及一種具有較大電容之溝渠式電容器，其可防止先 前技藝中之缺點且在較高之封裝密度時仍可儲存足夠之電 荷，這樣可確保記憶胞之功能。 此目的由申請專利範圍第1項之記憶體溝渠中提高電容 所用之方法及第15項之具有較大電容之溝渠式電容器來 達成。 本發明之方法及本發明之溝渠式電容器之有利之其它形 式描述在申請專利範圍各附項中。 在本發明之方法中，在記憶體溝渠中沈積第一氧化矽層 ，其上藉由沈積方法而沈積一種矽層，其提供此記憶體溝 渠一種足夠之側壁。在此矽層上沈積一種具有可氧化之金 屬之層。此矽層及可氧化之金屬層須氧化或一種具有金屬 氧化物及氧化矽之層。 在本發明之溝渠式電容器中，溝渠之內壁是以第一氧化 矽層覆蓋。第二氧化矽層是以一種含有金屬氧化物之層覆 蓋。此種含有金屬氧化物之層是以第二氧化矽層覆蓋。溝 渠之其餘部份是以矽塡入。 可使用化學氣相沈積或原子層沈積法作爲沈積方法° 在本發明之方法中，若在此種具有金屬氧化物及氧化石夕 之層上沈積第二氧化矽層，則這樣是有利的。 若此層可氧化之金屬層具有Ti，TiN，W，WN，Ta， TaN，WSi，TiSi或TaSi，則這樣是有利的。 -4- 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） 請 先 閱 讀. 背 面 之 注 意 事 項 再 經濟部智慧財產局員工消費合作社印製
492161 A7 B7 五、發明說明（3 ) 此種氧化在含氧之大氣中進行時是有利的。這樣可使各 別之金屬達成一種強化之氧化作用。 此外，溝渠中以矽塡入時是有利的。 就本發明之方法而言，若記憶體溝渠之寬度小於i4Gnm 時是有利的。 在本發明之方法中，當第一氧化矽層之厚度接近〇.3nm 時是特別有利的。 在本發明之方法中，當第二氧化矽層之厚度接近〇.3nm 時同樣是特別有利的。 當第一和第二氧化矽層藉由化學氣相沈積法而沈積時是 有利的。 在本發明之方法中，當矽層之厚度接近〇.5nm時是特別 有利的。 當所使用之矽特別適合用來覆蓋該側壁時，則特別有利。 在本發明之方法中，可氧化之金屬層之厚度接近l〇nm 時是有利的。 若此種具有可氧化之金屬之層藉由化學氣相沈積法沈積 而成時，則這樣在本發明之方法中是有利的。 經濟部智慧財產局員工消費合作社印製 本發明以下將依據圖式來詳述。圖式簡單說明： 第1圖在進行塗層之前此溝渠式電容器之橫切面。 第2圖在氧化矽層，矽層及金屬層進行塗層之後此溝渠 式電容器之橫切面。 第3圖在矽層和金屬層氧化之後此溝渠式電容器之橫切 面。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 492161 A7 B7 五、發明說明（4 ) 第4圖具有另一個氧化矽層之溝渠式電容器之橫切面。 第5圖具有矽塡料之溝渠式電容器（之橫切面。 第6圖在蝕刻之後該溝渠式電容器之橫切面。 第7圖在本發明之方法中使用鎢時各步驟之流程圖。 第8圖在本發明之方法中使用鈦時各步驟之流程圖。 第1圖中以橫切面顯示：一種埋入式η區l(n板）是由 基板2所圍繞。溝渠3存在於基板2及此埋入式η區中。 第2圖是記憶體溝渠3之橫切面。基板2之表面以及記 憶體溝渠3之內壁是以第一氧化矽層4塗佈。 氧化矽4在溝渠3之壁面上所具有之層厚度較基板2之 上側者還小。基板2之上側上之層厚度對溝渠3之側壁之 比例可以是2 :1。基板2之上側上之氧化矽沈積厚度大約 是0.3nm。氧化矽4可有利地沈積在爐（其中存在該已預製 之溝渠式電容器）中。 第一氧化矽層4在下一步驟中以矽層5覆蓋。在矽層5 中水平區域之層厚度較垂直區域中者還大。矽層5在爐中 最好在550°C時藉由LPCVD(L〇w Pressure CVD)沈積法而 形成。 爲了沈積矽層5，則亦可使用所謂原子層沈積（ALD)法 以取代CVD沈積法，其是用來形成極薄（較佳是只有數個 原子層厚度）之矽層所用之沈積方法。在ALD沈積法中， 其與CVD沈積方法不同的是：表面之化學親和性是用於 各別之分子或基（radical)。這些分子或基由氣相中沈積在 待塗層之表面上，直至全部之自由之原子價飽和爲止。此 -6- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 請 先 閱 讀. 背 面 之 注 意 事 項 再 經濟部智慧財產局員工消費合作社印製
492161 經濟部智慧財產局員工消費合作社印製 A7 _B7____五、發明說明（5 ) 種沈積因此會自我設限而結束。 在矽層5之表面上沈積一種層6(其具有可氧化之金屬） 。此層6之金屬可選擇性地含有Ti，TiN，W，WN，Ta， TaN，WSi，TiSi或TaSi。此層6在水平區及垂直區中覆 蓋該矽層5。金屬層6之厚度在水平區亦可大於垂直區中 者。在水平區中此層6之厚度大約是1 Onm。此金屬層6 較佳是以 CVP(Chemical vapor deposition)沈積而成。 此矽層5作爲金屬層6用之連結（link)層。這樣可以（或 促進）隨後之金屬沈積且可確保此金屬可充份地黏合至側 壁〇由於此矽層5，則另外可使介電質層之電容藉由此溝 渠式電容器中之金屬層6之氧化作用而提高。 例如，可使用鈦或鎢於可氧化之金屬層6中。 在沈積5及鈦層或鎢層6氧化之後形成第3圖所示之溝 渠式電容器之層構造。由此二個層，即，矽層5及鈦層或 鎢層6，而形成氧化鈦/氧化政鈦層或氧化鎢/氮化砂鎢層7 。氧化鈦或氧化矽鈦或此二者是否形成於層7中是與此製 程之進行次序有關。但製程中形成氧化鈦是較佳的，這是 因爲其介電常數較氧化矽鈦者還大。可藉由適當之製程順 序來防止氧化矽之形成。 同樣情況亦適用於氧化鎢或氧化矽鎢之形成。此處氧化 鎢是較佳的，因爲氧化鎢之介電常數較氧化砂鎢者還大。 使溝渠式電容器之記憶電容提高因此是可能的。在矽層5 和鈦層或鎢層6之氧化過程中，這樣所形成之層7是藉由 另外加入之氧而在水平區中形成，其層厚度大約是15nm。在 -7- 請 先‘ 閱 讀- 背 意 事 項 再
I»裝 頁I 訂 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 492161 A7 B7 五、發明說明（6 ) 垂直區中此7之厚度由10nm至20nm。因此，目的是使溝 渠3之垂直區中之層7儘可能厚。 氧化鈦/氧化矽鈦層之表面或氧化鎢/氧化矽鎢層7之表 面如第4圖所示是由第二氧化矽層或氮化矽層8所覆蓋， 第二氧化矽層或氮化矽層8在垂直區域中較在水平區域中 者還薄。第二氧化矽層8之水平之層厚度是0.3nm。 如第5圖所示，然後在下一步驟中使矽9塡入記憶體溝 渠3中。 最後，在下一步驟中又去除整個層結構，以便產生如第 6圖所示之結構。這可藉由乾燥化學蝕刻法及隨後以濕式 淨化法來完成。此種材料去除過程是在該埋入板區之上部 邊緣下方停止。 第7圖是此製程之流程圖。在該溝渠3已蝕刻該埋入板 之製程已完成之後，進行此溝渠之濕式淨化過程。然後沈 積一^種厚度是0.3nm(如第2圖所不）之氧化砂4。所使用 之氧化矽4亦稱爲爐氧化矽。在下一步驟中沈積爐矽5， 其須良好地覆蓋此溝渠3之側壁。然後藉由化學蒸氣沈積 法來沈積鎢6(層厚度l〇nm)。在下一步驟中，使矽層5及 鎢層6被氧化而形成氧化鎢7。最後，在爐中沈積第二氧 化矽層或氮化矽層8。 第8圖中顯示：使用鈦以提高記憶體溝渠中之電容所用 之方法之流程。如前所述，首先進行溝渠3之蝕刻及進行 埋入板之過程。然後對此溝渠進行濕式淨化過程且在下一 步驟中沈積一種爐氧化矽〇在下一步驟中藉由低壓化學蒸 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填$頁) · --線· 492161 Α7 Β7 五、發明說明（7 ) 氣沈積法在55(TC時在爐中沈積該爐矽。然後藉由化學蒸 氣沈積法沈積鈦6(層厚度10nm)。在下一步驟中使矽層5 及鈦層6氧化成氧化鈦層7。最後，此層7上沈積第二爐 氧化矽層或氮化矽層8。 ‘ 該埋入板過程用來使溝渠式電容器可與DRAM記憶體 模組所需之電晶體隔離。 矽層5可促進核化（nucleation)且可促進所期望之金屬層 (鈦或鎢）之黏合性，且可與隨後所沈積之金屬層6相連接 而被氧化。 上述之層厚度只是一種標準値而已。在溝渠寬度進一步 縮小時，各別之層厚度可相對應地調整。 符號之說明 1 埋入式η區 2 基板 3 溝渠 4 第一氧化矽層 5 矽層 6 含有可氧化之金屬之層 經濟部智慧財產局員工消費合作社印製 7 金屬氧化物層 8 第二氧化矽層或氮化矽層 9 矽塡料 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）

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  1. 492161 _?i!j六、申請專利範圍 第90104539號「記憶體溝渠中提高電容所用之方法及具有較 大電容之溝渠式電容器」專利案 （91年3月修正） 六申請專利範圍 1. 一種記憶體溝渠中提高電容所用之方法，其特徵爲： 記憶體溝渠（3)中沈積第一氧化矽層（4)， 在第一氧化矽層（4)上藉由一種沈積方法（其適合充份地 覆蓋此記憶體溝渠之壁面）沈積一種矽層（5)， 在矽層（5)上沈積一種層（6)，其具有可氧化之金屬， 矽層（5)及層（6)(其具有可氧化之金屬）氧化成一種層， 其具有金屬氧化物及氧化矽（7)。 2. 如申請專利範圍第1項之方法，其中使用化學蒸氣沈積 法或原子層沈積法作爲沈積方法。 3. 如申請專利範圍第2項之方法，其中在此層（6)(其具有可 氧化之金屬）及氧化矽層（7)上沈積第二氧化矽層或氮化矽 層（8) 〇 4. 如申請專利範圍第1，2或3項之方法，其中此層（6)(其 具有可氧化之金屬）具有Ti，TiN，W，WN，Ta，TaN，WSi， TiSi 或 TaSi 。 5. 如申請專利範圍第1項之方法，其中氧化作用是在含有 氧之大氣中進行。 6. 如申請專利範圍第1項之方法，其中記憶體溝渠（3)中塡 入矽（9)。 7·如申請專利範圍第1或6項之方法，其中該記憶體溝渠（3) 之寬度小於140nm。 492161 六、申請專利範圍 8·如申請專利範圍第1項之方法，其中第一氧化砍層（4)之 厚度是0.3nm。 9·如申請專利範圍第3項之方法，其中第二氧化矽層（8)之 厚度是0.3nm。 10. 如申請專利範圍第1或3項之方法，其中第一和第二氧 化砂層（4,8)藉由化學蒸氣沈積法沈積而成。 11. 如申請專利範圍第1項之方法，其中此矽層（5)之厚度是 0.5nm 〇 1Z如申請專利範圍第1或11項之方法，其中此矽層（5)所用 之矽具有特殊之能力以覆蓋此溝渠（3)之側壁。 η如申請專利範圍第1或3項之方法，其中此層（6)(其具有 可氧化之金屬）之厚度是10nm。 14. 如申請專利範圍第1或3項之方法，其中此層（6)(其具有 可氧化之金屬）是藉由化學蒸氣沈積法沈積而成。 15. 如申請專利範圍第13項之方法，其中此層（6)(其具有可 氧化之金屬）是藉由化學蒸氣沈積法沈積而成。 16. —種具有較大電容之溝渠式電容器，其特徵爲： 此記憶體溝渠（3)之內壁是以第一氧化矽層（4)覆蓋’ 第一氧化矽層（4)是以一種層（其具有金屬氧化物（7))覆 蓋， 具有氧化鈦（7)之此層是以第二氧化矽層（8)覆蓋’ 此記憶體溝渠（3)之其餘部份是以矽（9)塡入。 17. 如申請專利範圍第16項之具有較大電容之溝渠式電容 器，其中該金屬氧化物含有Ti ’ TiN，W，WN，Ta ’ TaN ’ WSi，TiSi 或 TaSi。 -2 - _____
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US20030073283A1 (en) 2003-04-17
US6699747B2 (en) 2004-03-02
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US20010030352A1 (en) 2001-10-18
DE10010821A1 (de) 2001-09-13

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