TW471143B - Integrated circuit chip package - Google Patents
Integrated circuit chip package Download PDFInfo
- Publication number
- TW471143B TW471143B TW090100177A TW90100177A TW471143B TW 471143 B TW471143 B TW 471143B TW 090100177 A TW090100177 A TW 090100177A TW 90100177 A TW90100177 A TW 90100177A TW 471143 B TW471143 B TW 471143B
- Authority
- TW
- Taiwan
- Prior art keywords
- scope
- patent application
- item
- top surface
- cover
- Prior art date
Links
- 235000012431 wafers Nutrition 0.000 claims description 35
- 239000000853 adhesive Substances 0.000 claims description 22
- 230000001070 adhesive effect Effects 0.000 claims description 22
- 125000006850 spacer group Chemical group 0.000 claims description 19
- 238000003466 welding Methods 0.000 claims description 9
- 229910000679 solder Inorganic materials 0.000 claims description 8
- 230000002079 cooperative effect Effects 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 239000004033 plastic Substances 0.000 claims description 4
- 229920003023 plastic Polymers 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 239000002990 reinforced plastic Substances 0.000 claims description 3
- 239000004593 Epoxy Substances 0.000 claims description 2
- 239000004952 Polyamide Substances 0.000 claims description 2
- 239000000919 ceramic Substances 0.000 claims description 2
- 125000003700 epoxy group Chemical group 0.000 claims description 2
- 239000011152 fibreglass Substances 0.000 claims description 2
- 229920002647 polyamide Polymers 0.000 claims description 2
- 229920000647 polyepoxide Polymers 0.000 claims description 2
- 229920001296 polysiloxane Polymers 0.000 claims description 2
- 239000012780 transparent material Substances 0.000 claims description 2
- 230000000875 corresponding effect Effects 0.000 claims 2
- -1 Aerylies Polymers 0.000 claims 1
- 239000002689 soil Substances 0.000 claims 1
- 238000003384 imaging method Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000010276 construction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229920006397 acrylic thermoplastic Polymers 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- AYOOGWWGECJQPI-NSHDSACASA-N n-[(1s)-1-(5-fluoropyrimidin-2-yl)ethyl]-3-(3-propan-2-yloxy-1h-pyrazol-5-yl)imidazo[4,5-b]pyridin-5-amine Chemical compound N1C(OC(C)C)=CC(N2C3=NC(N[C@@H](C)C=4N=CC(F)=CN=4)=CC=C3N=C2)=N1 AYOOGWWGECJQPI-NSHDSACASA-N 0.000 description 1
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 1
- 239000011226 reinforced ceramic Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- ISXSCDLOGDJUNJ-UHFFFAOYSA-N tert-butyl prop-2-enoate Chemical compound CC(C)(C)OC(=O)C=C ISXSCDLOGDJUNJ-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electromagnetism (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Description
471143 A7 B7
^濟'^-£T_· -nr UK 五、發明説明() 本發明係與積體電路晶片之構裝有關,特別是指一種 小尺寸積體電路晶片之構裝結構。 請參閱第一圖,為一種習用之積體電路晶片之構裝 (10),該構裝(10)大體上包含有一承載體(π)、一晶片(12) 5 及一遮蓋(13),其中該承載體(11)具有一開口向上之容室 (14),該容室(14)之底部佈設有預定數目及態樣之銲墊 (16),該晶片(12)則黏著固接於該容室(14)底部中央位置 上,並藉由銲線(17)與各該銲墊(16)電性連接,而該遮蓋 (13),係用以封抵住該承載體(11)之開口端,使該晶片(12) 10 可與外界隔離,以保護該晶片(12)不受外力破壞或雜物污 染,且當該晶片(12)係為影像用晶片時,該遮蓋(13)則為透 明物質所製成。其次,請參閱第二圖,為另一種習用之構 裝(20),其結構大體上與前一習用構裝(10)相仿,申請人在 此容不贅述。 15 上述構裝(10),因該容室(14)底部必須同時容裝晶片 (12)以及承載體(11)之銲墊(16),且晶片(12)與該容室(14) 之壁面之間,必須提供足夠之空間供打線器活動,以致該 容室(M)底部之面積,將遠大於晶片本身之面積,而大幅 增加整個構裝之體積,如此一來,對於現行電子產品"輕、 20 薄、短、小"之體積訴求而言,此等構裝方式並非十分適用。 其次,上述構裝(10)之承載體(11),一般係採用強化塑 膠材質、陶瓷等材質之印刷電路板製造,必須進一步加工 容納晶片之凹陷容室,整體製程顯得較為複雜。 緣此,本發明之主要目的在於提供一種積體電路晶片 -3- 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 裝-- (讀先閱讀背面之注意事項再填寫本頁)
'1T 471143 A7 B7 經濟部中央標準局員工消費合作社印f 五、發明説明() 之構裝,可大幅縮小其整體構裝體積者。 本發明之又一目的在於提供一種積體電路晶片之構 裝,其結構簡單,加工組裝容易者。 為達成上述之目的,本發明所提供之一種積體電路晶 5 片之構裝,包含有:一承載板,具有一頂面及一底面,且 該頂面佈設有多數之銲墊;至少一晶片,係固設於該承載 板頂面,該晶片具有多數之銲墊;多數之銲線,係分別電 性連接該承載體之銲墊與該晶片之銲墊;一黏著物,係佈 設於該承載板頂面周緣;一遮蓋;一間隔裝置,係銜接該 10 承載板與該遮蓋,用以使該遮蓋可間隔一預定距離地罩設 於該承載板頂面上方者。 為使 審查委員能詳細暸解本發明之實際構造及特 點,茲列舉以下實施例並配合圖示說明如后,其中·· 第一圖係一種習用積體電路晶片之構裝; 15 第二圖係另一種習用積體電路晶片之構裝; 第三圖係本發明第一較佳實施例之立體組合圖; 第四圖係第三圖沿剖線4-4方向之剖視圖; 第五圖係本發明第一較佳實施例之頂視圖; 第六圖係本發明第二較佳實施例之剖視圖; 20 第七圖係本發明第三較佳實施例之剖視圖; 第八圖係本創作第四較佳實施例之剖視圖; 第九圖係本創作第五較佳實施例之剖視圖; 第十圖係本創作第六較佳實施例之剖視圖; 第十一圖係本創作第七較佳實施例之剖視圖。 25 請先參閱第三至第五圖,係本發明第一較佳實施例所 4- 本紙張尺度適用中國國家標準(CNS ) A4規格(210X29?公釐) ---------衣------訂------t (請先閱讀背面之注意事項再填寫本頁) 143 4 A7 B7 7、發明说明( 10 15 經濟部中决標率局員工消費合作社印製 20 25 提供之積體電路晶片構裝(30),主要包含有一承載板(31)、 /晶片(32)、多數之銲線(33)、一黏著物(34)、一遮蓋(35)、 /間隔裝置(36)及一連接裝置(3Ό ’其中: 該承載板(31) ’係可為塑膠、玻璃纖維、強化塑膠、 陶瓷.··等材質所製成之電路板(Printed Circuit Board, pCB),其具有一頂面(31a)及一底面(3ib),且該頂面(31a) 调緣佈設有多數之銲墊(31c)。 該晶片(32),係固定於承載板(31)頂面(31 a)中央位置, $該晶片(32)之表面具有多數之銲墊(32b)。 各該銲線(33),係由黃金或鋁等金屬材質製成,係利 用打線器(圖中未示)先以其一端與該晶片(32)之銲墊(32b) 連接,其另一端再與該承載板(31)之銲墊(31c)連接。 該黏著物(34) ’係可為梦樹脂(Silicones)、環氧樹脂 (Epoxies)、丙烯酸樹脂(Acrylics)、聚醯亞胺(p〇lyamides)、 低熔點之玻璃或雙面膠帶等材質所構成,該黏著物(34)係 佈設於該承載板(31)頂面(3la)’並覆蓋保護著各該銲線(33) 與該承載板(31)銲墊(31c)之銜接處。 該遮蓋(35) ’具有一由不透明之塑膠、金屬或透明之 玻璃、塑膠等材質所製成之板件,其具有一頂面(35a)以及 一底面(35b)。 而該間隔裝置(36) ’其主要功能係銜接該承載板(31) 與該遮蓋(35),用以使該遮蓋(35)可間隔一預定距離地罩設 於該承載板(31)頂面(3 la)上方;本實施例中,該間隔裝置 (36)包含有四定位柱(36a) ’各該定位柱(36a)之一端係一體 銜接於該遮盍(35)底面(35b)四個角落,而各該定位柱(3Q) ---------装------訂------t (請先閱讀背面之注意事項再填寫本頁} 本紙張尺度適用中國國家標準(cns ) A4規格(210X297公釐) 471143 Μ Β7 五、發明説明() 之另一端則抵接於該承載板(31)頂面(3la),並使該遮蓋(35) 之底面(35b)周緣可與該黏著物(34)固接,藉此,可隔離該 晶片(32)與外界,以保護該晶片(32)不受外力破壞或雜物污 染。 5 而該連接裝置(37),其主要功能係用以電性連接該承 載板上之銲墊(31c)至該承載板外部;本實施例中,該連接 裝置(37)係為開設於該承載板(31)周緣,用以連通該承載板 (31)頂面(3 la)銲蟄(3lc)至該承載板(31)底面(31b)之多數貫 孔(37a)(through hole),藉此,該構裝(30)可藉由銲錫電性 1〇 連接於一外界電路板(圖中未示)上。 藉由上述之組合,該積體電路晶片構裝(30),該承載 板(31)頂面(3 la)周緣,係為一開放之空間,可供打線器自 由活動’因此該承載板(31)之面積,可儘其可能地縮小至 與該晶片(32)之面積幾近相同’故可大幅地縮小該構裝(3〇) 15之整體體積,以達到晶片尺寸般構裝(chip size package)之 目的;其次,該承載板(31)可利用現行之電路板製造,不 須再額外加工,故整體結構較習用技術更為簡單、組裝更 為容易。 經漓部中央標準局員τ,消費合作社印製 ---------η衣— (請先閱讀背面之注意事項再填寫本頁 訂 凊參閱弟7T圖’係本發明弟二較佳實施例所提供之積 20體電路晶片構裝(40),其結構大體上與前一實施例相仿, 惟其差異在於: 該間隔裝置之定位柱(42)之一端’係嵌置於該承載板 (44)頂面凹設之定位孔(44a)中’俾使該遮蓋(46)可穩固地罩 設於該承載板(44)上。 25 請參閱第七圖,係本發明第三較佳實施例所提供之積 -6· 本纸張尺度適ϋ國國Ϊ:標準(CNS ) Λ4規格(ϋχ 297公釐)~~~~~~----——~~ 經濟部中央標準局貝工消費合作社印聚 471143 A7 _________ B7 一Τ-_Γ .」. 一 ' ~' ' ' ' - …· 越 一~ — 五、發明説明() 體電路晶片構裝(50),其結構大體上與前一實施例相仿, 惟其差異在於: 該承載板(52)設有貫穿其頂、底面之定位孔(52a) ’而 該間隔裝置之定位柱(54)之一端,係穿過該定位孔(52a)並 5 突露於該承載板(52)底面,以作為該構裝(50)裝設於外界電 路板上時之定位點者。 請參閱第八圖,係本發明第四較佳實施例所提供之積 體電路晶片構裝(60) ’主要包含有一承載板(61)、一影像用 晶片(62)、多數之銲線(63)、一黏著物(64)、一遮蓋(65)、 間隔裝置(66)及一連接裝置(67),本實施例與上述各實施 例之差異在於: 該遮蓋(65) ’具有一頂面(65a)、一底面(65b)以及貫穿 其頂底面(65a)(65b)之穿孔(65d),該穿孔(65d)中封設有若 干鏡片(65e),藉此光線可透過該鏡片(65e)照射於該晶片 15 (62)上。 其次,該間隔裝置(66),係為一框體(66a),其頂端(66b) 係抵接於該遮蓋(65)底面(65b),而詨框體(66a)之底端 (65c),係與該黏著物(64)銜接固定。 而該連接裝置(67),本實施例中,係包含有電性連通 20該承載板(61)頂面銲墊至該承載板(61)底面之多數貫孔 (67a)(through hole),以及佈植於該承載板(61)底面,與各 该貫孔(67a)電性連接之多數個銲球(67b)(s〇lder ba⑴者。 請參閱第九圖,係本發明第五較佳實施例所提供之積 體電路晶片構裝(70),主要包含有一承载板(71)、一影像用 25晶片(72)、多數之銲線(73)、一黏著物(74)、一遮蓋(75)、 -7- "^氏張尺度適) Μ規格(~~~ ---- ---------^------訂------'\ (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 471143 A7 B7 五、發明说明() 一間隔裝置(76)以及一連接裝置(77),本實施例與上述各實 施例之差異在於: 該遮蓋(75),具有一貫穿其頂、底面(75a)(75b)之螺孔 (75c)及一鏡頭(75d);該鏡頭(75d),具有一筒體(75f)及封 5設於孩筒體(75f)中之鏡片(75g),且該筒體(75f)係鎖合於該 螺孔(75c)中者。在此需說明的是’該鏡頭(75d)利用螺紋鎖 合方式與該螺孔(75c)銜接,可方便調整該鏡頭(75d)至該晶 片(72)之距離(焦距),惟其亦可採用他種固定方式者。 其次’該間隔裝置(76),本實施例中係為一框體(76a), 10其頂端C76b)係與該遮蓋(75)底面(75b)銜接,其底端(76c) 則抵接於該承載板(71)頂面,且該框體(76a)鄰近該承載板 (71)位置具有一凹陷部(76d),可以容置該黏著物(74)者。 再者’該連接裝置(77),於本實施例中,包含有多數 之金屬接腳(77a)(lead),各該接腳(77a)之一端(77b)係與該 15 承載板(71)頂面銲墊電性連接,另一端(77c)則位於該承載 板(71)外部並彎折成預定形狀者。 請參閱第十圖,係本發明第六較隹實施例所提供之積 體電路晶片構裝(80),主要包含有一承載板(81)、一影像用 晶片(82)、多數之銲線(83)、一黏著物(84)、一遮蓋(85) — 20 間隔裝置(86)以及一連接裝置(87),本實施例與上述各實施 例之差異在於: 該連接裝置(87),於本實施例中,包含有多數之金屬 接腳(87a)(lead),各該接腳(87a)之一端(87b)係固設於該承 載板(81)之頂面上,位於該晶片(82)之周緣,且各該接腳 -8- 本紙張尺度適用中國國家標準(CNS ) A4规格(2!〇χ297公釐) ----------衣------^11------^ (請先閱讀背面之注意事項再填寫本百 〇 471143 A7 B7 經濟部中央標率局負工消費合作社印製 五、發明説明() (87a)之該端(87b)上具有一銲墊(圖中未示),並藉由該銲墊 與該銲線(83)連接,而該接腳(87a)之另一端(87c)則位於該 承載板(81)外部並彎折成預定形狀者。 其次,該間隔裝置(86),其底端(86a)係壓接於該接腳 5 —端(87b)上,且該底端(86a)具有一凹陷部(86b),用以容納 該黏著物(84)。 請參閱第十一圖,係本發明第七較佳實施例所提供之 積體電路晶片構裝(90),主要包含有一承載板(91)、一影像 用晶片(92)、多數之銲線(93)、一黏著物(94)、一遮蓋(95)、 10 一間隔裝置(96)以及一連接裝置(97),本實施例與上述各實 施例之差異在於: 該承載板(91)之頂面尚佈設有若干電子元件(91a),各 該元件(91a)並佈線(圖中未示)與該承載體(91)頂面之銲塾 (圖中未示)電性連接,如此一來,該構裝(90)可成為一具特 15 定功能之模組使用。 综上所陳,本發明積體電路晶片之構裝,確實具有體 積小及結構簡單組裝容易之優點,故本發明之實用性與進 步性當毋庸置疑,今為保障申請人之權益,遂依法提出專 利申請’祈請 審查委貝詳加審查’並早日賜准本案專 20 利,則為申請人是幸。 (請先閱讀背面之注意事項再填寫本頁 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) 471143 A7 B7 五、發明説明() 厂圖示之簡單說明J 第一圖係一種習用積體電路晶片之構裝; 第二圖係另一種習用積體電路晶片之構裝; 第三圖係本發明第一較佳實施例之立體組合圖; 5 第四圖係第三圖沿剖線4-4方向之剖視圖; 第五圖係本發明第一較佳實施例之頂視圖; 第六圖係本發明第二較佳實施例之剖視圖; 第七圖係本發明第三較佳實施例之剖視圖; 第八圖係本創作第四較佳實施例之剖視圖; 10 第九圖係本創作第五較佳實施例之剖視圖; 第十圖係本創作第六較佳實施例之剖視圖; 第十一圖係本創作第七較佳實施例之剖視圖。 ----------衣-- (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 「圖號說明」 『第一實施例』 15 構裝(30) ’ 承載板(31) 頂面(3 la) 底面(3 lb) 銲墊(31c) 晶片(32) 銲墊(32b) 銲線(33) 黏著物(34) 遮蓋(35) 頂面(35a) 底面(35b) 間隔裝置(36) 20 貫孔(37a) 『第二實施例』 四定位柱(36a) 連接裝置(37) 構裝(40) 定位柱(42) 承載板(44) 定位孔(44a) 『第三實施例』 遮蓋(46) -10- 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) 471143 A7 B7 經濟部中决標率局員Η消費合作社印製 發明説明() 構裝(50) 承載板(52) 定位孔(52a) 定位柱(54) 『第四實施例』 構裝(60) 承載板(61) 晶片(62) 5 銲線(63) 黏著物(64) 遮蓋(65) 頂面(65a) 底面(65b) 穿孔(65d) 鏡片(65e) 間隔裝置(66) 框體(66a) 頂端(66b) 底端(65c) 連接裝置(67) 貫孔(67a) 銲球(67b) 10 『第五實施例』 構裝(70) 承載板(71) 晶片(72) 銲線(73) 黏著物(74) 遮蓋(75) 頂面(75a) 底面(75b) 螺孔(75c) 鏡頭(75d) 筒體(75f) 鏡片(75g) 15 間隔裝置(76) 框體(76a) 頂端(76b) 底端(76c) 凹陷部(76d) 連接裝置(77) 接腳(77a) 接腳一端(77b) .接腳另一端(77c) 構裝(70) 承載板(71) 晶片(72) 『第六實施例』 20 構裝(80) 承載板(81) 晶片(82) 銲線(83) 黏著物(84) 遮蓋(85) 間隔裝置(86) 底端(86a) 凹陷部(86b) 連接裝置(87) 接腳(87a) 接聊一端(87b) 接腳另一端(87c) 25 『第七實施例』 -11- (請先閱讀背面之注意事項再填寫本頁
、1T 本紙張尺度適用中國國家標準(CNS ) Α4規格(2Ι0Χ297公釐) 471143 A7 B7 五、發明説明() 構裝(90) 承載板(91) 晶片(92) 銲線(93) 黏著物(94) 遮蓋(95) 間隔裝置(96) 連接裝置(97) 電子元件(91a) (請先閲讀背面之注意事項再填寫本頁') 經濟部中央標準局員工消費合作社印製 2 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐)
Claims (1)
- 471143 A8 B8 C8 D8 申請專利範圍 15 20 經濟部智慧財產局P'工消費合作社印製 25 1_一種積體電路晶片之構裝,包含有: 承載板,具有一頂面及一底面,且該頂面佈設有多 數之銲墊; " 至少—晶片,係固設於該承載板頂面,該晶片且多 數之銲墊; 6/、有^ 多數之銲線’係分別電性連接該承載體之銲墊與該晶 片之銲墊; 土 〃 p 一黏著物’係佈設於該承載板頂面周緣; 一遮蓋; 卜一間隔裝置,係銜接該承載板與該遮蓋,用以使該遮 蓋可間隔一預定距離地罩設於該承載板頂面上方者。 2. 依據申請專利範圍第1項所述之構裝,其中該黏著 物佈設於該承載板頂面周緣時,係覆蓋保護著各該銲線與 該承載板頂面銲墊之連接處者。 3. 依據申請專利範圍第1項所述之構裝,其中該遮蓋 更與戎黏著物銜接固定者。 士 4.依據申請專利範圍第1項所述之構裝,其中該間隔 裝置,包含有至少一定位柱,係夾置固接於該承載板與該 遮盖之間者。 5.依據申請專利範圍第4項所述之構裝,其中該承載 板頂面凹設有至少一定位孔,且該定位柱之一端係嵌置固 定於該定位孔中。 6·依據申請專利範圍第4項所述之構裝,其中該承載 板設有至少—貫穿該承載板頂、底面之定位孔,且該定位 柱之一端係穿過該定位孔,並突露出該承載板底面者。 7.依據申請專利範圍第丨項所述之構裝,其中該間隔 裝置’包含有一框體,係夾置固接於該承載板與該遮蓋之 ;----- -- - I I —Jn m c讀先閱讀背面之注意f項存填寫本f ) 、-口 本紙張尺度適$中國國蒙; 叩 務 靈 公 7 9 471143 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 間。 8. 依據申請專利範圍第7項所述之構裝,其中該框體, 其鄰近該承載板位置具有一凹部,可供該黏著物容置者。 9. 依據申請專利範圍第1項所述之構裝,其中該遮蓋 5 係為透明材質所製成者。 10. 依據申請專利範圍第1項所述之構裝,其中該遮蓋 具有一通孔,該通孔係對應該晶片,且該通孔中至少封設 固定有一鏡片者。 11. 依據申請專利範圍第1項所述之構裝,其中該遮蓋 10 具有: 一螺孔,係貫穿該遮蓋之頂底面,並對應該晶片; 一鏡頭,具有一筒體以及至少一封設於該筒體中之鏡 片,且該筒體係鎖合於該螺孔中者。 12. 依據申請專利範圍第1項所述之構裝,其中該承載 15 板,係為一選自塑膠、強化塑膠、玻璃纖維或陶瓷等材料 之一所製成者。 13. 依據申請專利範圍第1項所述之構裝,其中該黏著 物,係選自砂樹脂(Silicones)、環氧樹脂(Epoxies)、丙婦酸 樹脂(Aerylies)、聚醯亞胺(Polyamides)、玻璃等材質之一所 20 製成者。 14. 依據申請專利範圍第1項所述之構裝,其中該黏著 物,係為一雙面膠帶者。 15. 依據申請專利範圍第1項所述之構裝,其中該承載 板頂面更佈設有若干電子元件,係與位於該承載板頂面之 25 銲墊電性連接者。 16. 依據申請專利範圍第1項所述之構裝,更包含有一 連接裝置,係用以電性連接該承載板上之銲墊至該承載板 ----------^------17------線 (請先閱讀背面之注意事項再填寫本頁) -14- 本紙張尺度適用中國國家標準(CNS) A4規格( 210X297公釐) 471143 A8 B8 C8 D8 六、申請專利範圍 外部者。 17.依據申請專利範圍第16項所述之構裝,其中該連 接裝置,係為開設於該承載板周緣,用以連通該承載板頂 面鮮塾至該承載板底面之多數貫孔者。 5 18.依據申請專利範圍第16項所述之構裝,其中該連 接裝置,包含有多數貫孔及銲球,其中各該貫孔,係電性 連接該承載板頂面銲蟄至該承載板之底面,而各該銲球, 係佈植於該承載板之底面,並分別與各該貫孔電性連接 者。 10 19.依據申請專利範圍第16項所述之構裝,其中該連 接裝置,係為多數之金屬接腳,各該接腳之一端係與位於 該承載板頂面之銲墊電性連接,另一端則位於該承載板外 部並彎折成預定形狀者。 ----------^------訂------il (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員.工消費合作社印製 ________-1S- 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW090100177A TW471143B (en) | 2001-01-04 | 2001-01-04 | Integrated circuit chip package |
US10/033,932 US6798053B2 (en) | 2001-01-04 | 2002-01-03 | IC chip package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW090100177A TW471143B (en) | 2001-01-04 | 2001-01-04 | Integrated circuit chip package |
Publications (1)
Publication Number | Publication Date |
---|---|
TW471143B true TW471143B (en) | 2002-01-01 |
Family
ID=21676937
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW090100177A TW471143B (en) | 2001-01-04 | 2001-01-04 | Integrated circuit chip package |
Country Status (2)
Country | Link |
---|---|
US (1) | US6798053B2 (zh) |
TW (1) | TW471143B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI503944B (zh) * | 2013-04-18 | 2015-10-11 | 矽品精密工業股份有限公司 | 屏蔽罩、半導體封裝件及其製法暨具有該屏蔽罩之封裝結構 |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004312666A (ja) * | 2003-03-25 | 2004-11-04 | Fuji Photo Film Co Ltd | 固体撮像装置及び固体撮像装置の製造方法 |
KR100545133B1 (ko) * | 2003-04-28 | 2006-01-24 | 주식회사 스마텍 | 팩키지 구조 및 팩키지 구조를 이용한 센서 모듈 |
TWI228811B (en) * | 2004-05-28 | 2005-03-01 | Taiwan Electronic Packaging Co | Package for integrated circuit chip |
TWI254997B (en) * | 2004-09-10 | 2006-05-11 | Aiptek Int Inc | Process of manufacturing flip-chips and the apparatus thereof |
TWM271321U (en) * | 2004-09-10 | 2005-07-21 | Aiptek Int Inc | Flip-chip packaging device |
JP2006278726A (ja) * | 2005-03-29 | 2006-10-12 | Sharp Corp | 半導体装置モジュール及び半導体装置モジュールの製造方法 |
US20060219862A1 (en) * | 2005-03-31 | 2006-10-05 | Kai-Kuang Ho | Compact camera module with reduced thickness |
US7084391B1 (en) * | 2005-04-05 | 2006-08-01 | Wen Ching Chen | Image sensing module |
CN1885909A (zh) * | 2005-06-24 | 2006-12-27 | 鸿富锦精密工业(深圳)有限公司 | 数码相机模块 |
US20070120213A1 (en) * | 2005-11-28 | 2007-05-31 | Hiew Siew S | Wire under dam package and method for packaging image-sensor |
JP4466552B2 (ja) * | 2005-12-09 | 2010-05-26 | ソニー株式会社 | 固体撮像装置の製造方法 |
DE102006011753B4 (de) * | 2006-03-13 | 2021-01-28 | Infineon Technologies Ag | Halbleitersensorbauteil, Verfahren zur Herstellung eines Nutzens und Verfahren zur Herstellung von Halbleitersensorbauteilen |
CN100483725C (zh) * | 2006-07-28 | 2009-04-29 | 鸿富锦精密工业(深圳)有限公司 | 影像感测器封装及其应用的数码相机模组 |
CN101132478A (zh) * | 2006-08-23 | 2008-02-27 | 鸿富锦精密工业(深圳)有限公司 | 影像感测器封装及其应用的数码相机模组 |
US20080099866A1 (en) * | 2006-10-25 | 2008-05-01 | Impac Technology Co., Ltd. | Image sensing module and method for packaging the same |
CN101562175B (zh) * | 2008-04-18 | 2011-11-09 | 鸿富锦精密工业(深圳)有限公司 | 影像感测器封装结构及其应用的成像装置 |
DE102009001930B4 (de) * | 2009-03-27 | 2018-01-04 | Robert Bosch Gmbh | Sensorbaustein |
DE102011080971A1 (de) * | 2011-08-16 | 2013-02-21 | Robert Bosch Gmbh | Sensor, Sensoreinheit und Verfahren zur Herstellung einer Sensoreinheit |
KR101792442B1 (ko) * | 2016-12-12 | 2017-10-31 | 삼성전기주식회사 | 전자 모듈과 그 제조 방법 |
CN113035788A (zh) * | 2019-12-25 | 2021-06-25 | 台湾积体电路制造股份有限公司 | 封装结构及其制作方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0831490B2 (ja) * | 1991-03-21 | 1996-03-27 | 株式会社住友金属セラミックス | ガラス封止型セラミックパッケージ |
US5773879A (en) * | 1992-02-13 | 1998-06-30 | Mitsubishi Denki Kabushiki Kaisha | Cu/Mo/Cu clad mounting for high frequency devices |
US5804870A (en) * | 1992-06-26 | 1998-09-08 | Staktek Corporation | Hermetically sealed integrated circuit lead-on package configuration |
US5650592A (en) * | 1993-04-05 | 1997-07-22 | Olin Corporation | Graphite composites for electronic packaging |
US5877546A (en) * | 1996-01-02 | 1999-03-02 | Lg Semicon Co., Ltd. | Semiconductor package with transparent window and fabrication method thereof |
KR100186329B1 (ko) * | 1996-06-14 | 1999-03-20 | 문정환 | 고체 촬상 소자용 반도체 패키지 |
US5893726A (en) * | 1997-12-15 | 1999-04-13 | Micron Technology, Inc. | Semiconductor package with pre-fabricated cover and method of fabrication |
US6204454B1 (en) * | 1997-12-27 | 2001-03-20 | Tdk Corporation | Wiring board and process for the production thereof |
US6313521B1 (en) * | 1998-11-04 | 2001-11-06 | Nec Corporation | Semiconductor device and method of manufacturing the same |
JP3395164B2 (ja) * | 1998-11-05 | 2003-04-07 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 半導体装置 |
JP2000349178A (ja) * | 1999-06-08 | 2000-12-15 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US6531784B1 (en) * | 2000-06-02 | 2003-03-11 | Amkor Technology, Inc. | Semiconductor package with spacer strips |
US6317326B1 (en) * | 2000-09-14 | 2001-11-13 | Sun Microsystems, Inc. | Integrated circuit device package and heat dissipation device |
-
2001
- 2001-01-04 TW TW090100177A patent/TW471143B/zh active
-
2002
- 2002-01-03 US US10/033,932 patent/US6798053B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI503944B (zh) * | 2013-04-18 | 2015-10-11 | 矽品精密工業股份有限公司 | 屏蔽罩、半導體封裝件及其製法暨具有該屏蔽罩之封裝結構 |
Also Published As
Publication number | Publication date |
---|---|
US20020140072A1 (en) | 2002-10-03 |
US6798053B2 (en) | 2004-09-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW471143B (en) | Integrated circuit chip package | |
US6627983B2 (en) | Stacked package structure of image sensor | |
US6559539B2 (en) | Stacked package structure of image sensor | |
EP1221716A2 (en) | IC chip package | |
US20080309805A1 (en) | Image sensor package | |
US8248514B1 (en) | Camera module having image sensing module with passive components | |
US20070152345A1 (en) | Stacked chip packaging structure | |
US6876544B2 (en) | Image sensor module and method for manufacturing the same | |
US6967400B2 (en) | IC chip package | |
US20070034772A1 (en) | Image sensor chip package | |
JP2005086100A (ja) | 固体撮像装置 | |
US6740973B1 (en) | Stacked structure for an image sensor | |
US20070138585A1 (en) | Image sensor package | |
EP1434276B1 (en) | Image sensor adapted for reduced component chip scale packaging | |
US20040179249A1 (en) | Simplified image sensor module | |
KR200235805Y1 (ko) | 집적 회로 칩 패키지 | |
US20040150062A1 (en) | Simplified image sensor module | |
JP2004186362A (ja) | 回路装置 | |
JPH04162657A (ja) | 半導体装置用リードフレーム | |
KR100414224B1 (ko) | 스택 패키지 구조의 영상 센서 | |
JPS61214565A (ja) | 半導体光センサ装置 | |
JPS61281559A (ja) | 光検出装置 | |
KR100428950B1 (ko) | 스택 구조의 영상 센서 및 그의 제조방법 | |
US7064404B1 (en) | Image sensor structure | |
US20070159543A1 (en) | Simplified image sensor module package |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent |