TW445601B - Die-embedded ball grid array packaging structure with leadframe - Google Patents
Die-embedded ball grid array packaging structure with leadframe Download PDFInfo
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- TW445601B TW445601B TW089100694A TW89100694A TW445601B TW 445601 B TW445601 B TW 445601B TW 089100694 A TW089100694 A TW 089100694A TW 89100694 A TW89100694 A TW 89100694A TW 445601 B TW445601 B TW 445601B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
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Description
Λ 45 6 Ο ' 五、發明說明(ι) ' 發明領域: 本發明係有關於一種半導體裝置,特別有關於一種晶 片我入式球格陣列(Ball Grid array, BGA)封裝構造,用 以封裝銲墊位於中央之半導體晶片。 先前技術: 隨著更輕更複雜電子裝置需求的曰趨強烈,半導體晶 片的速度及複雜性相對越來越兩’而越複雜之半導體晶片 其所需之電性連接也越多。於是,半導想晶片封裝業界發 展出球格陣列封裝構造丨〇 〇。請參照第一圊,球格陣列封 裝構造100係將晶片112固設於一絕緣基板114之上表面, 該基板114之下表面係用以安裝至一電路板上。晶片丨12設 有複數個位在其周邊之銲勢(未示於圖中),用以電性連 接至晶片112之内部電路。該基板114之上表面設有複數個 銲墊116及導電線路,該複數個銲墊116及導電線路係藉由 連接線(bonding wires)118電性連接至該晶片112之晶片 銲墊。該基板114之下表面設有複數個錫球(s〇ider ba 1 1 s ) 1 1 9 ’使該封膠體可與外界電性溝通,並且由於錫 球可呈高密度陣列排列,所以可用以封襄需要大量電性連 接之晶片。該複數個録墊116及導電線路係藉由穿設於該 基板114中的導電通孔(vias)與該複數個錫球119電性連 接。一封躁體117以及該基板114共同密封該晶片η〗、該 複數條連接線18以及該複數個鲜塾及導電線路116 ,使其 與外界隔絕,而形成一球格陣列封聢構造丨0 〇 ^ 然而,第一圖所示之球格陣列封裝構造1 〇 〇只適用於封
• 44560 ^ 45 6 0 1___ 五、發明說明(2) 裝銲墊位在周邊之晶片(peripheral-pad design chip), 因為若該晶片1 1 2之銲墊係位於其中央,則連接線11 8會變 得太長,而導致導電效能(electrical performance)降 低,以及伴隨電阻及訊號干擾增加之問題。 因而,業界發展出另一種封裝構造以克服前述問題。 請參照第二圖,一種改良封裝構造20 0在基板2 2 5設一槽縫 以供複數條連接線226通過,藉此該連接線226可以電性連 接該基板225至一銲墊位於中央之晶片224,但不會有前述 因連接線太長而導致導電效能降低,以及伴隨電阻及訊號 干擾增加之問題。然而,在該基板225之下表面必須設一 下封膠體2 2 8來密封該複數條連接線2 2 6使其與外界隔絕, 並且該下封膠體228在封膠製程(molding process)中很難 避免封膠溢料(f 1 a s h )之現象產生,所以必須以去溢料 (de-f lash)製程來清除封膠溢料或以複雜且昂貴之封膠方 法來防止溢膠,以免影響設於該基板225下表面之複數個 錫球220之銲料連接可靠性(s〇ider joint reliability)。 發明概要: 本發明之主要目的係提供一種晶片嵌入式球格陣列 (Ball Grid array, BGA)封裝構造,其包含一導線架用以 將一銲塾位於中央之晶片電性連接至一基板,藉此該基板 不需要具有槽縫供其電性連接,因此其製造不需要去溢料 製程》 根據本發明之晶片嵌入式球格陣列封裝構造,其主要
第5頁 445601 五'發明說明(3) 包含一基板、一導線架、一半導體晶片以及一封膠體包覆 該導線架以及半導體晶片使其與外界隔絕。該基板之正面 6史有一凹部用以容置該半導體晶片。該基板之正面設有複 數個基板銲墊(contact pads),該基板之背面設有複數個 錫球,用以與外界電性溝通,該每一個錫球係分別電性連 接至相對應的基板銲墊。該半導體晶片具有複數個晶片銲 墊位於該晶片之上表面中央,用以電性連接至該晶片之内 部電路。該導線架包含複數條導線且具有内腳部分(inner lead portion)以及外腳部分(outer lead portion),該 複數條導線之内腳部分以一絕緣層固設於該晶片之上表 面。該每一條導線之内腳部分係以連接線(bonding w i res)連接至相對應的晶片銲墊,該複數條導線之外腳部 分係電性連接至相對應的基板銲墊。可以理解的是,根據 本發明之晶片嵌入式球格陣列封裝構造可包含一個以上之 半導體晶片而形成一多晶片球格陣列(BG A )封裝構造。 根據本發明之晶片嵌入式球格陣列封裝構造,其基板 不需要具有槽縫也可用以封裝銲塾位於中央之晶片。由於 該半導體晶片係設於該基板正面之凹部,且該晶片係經由 在基板正面之導線架電性連接至該基板,所以該封膠體只 需包復該基板之正面,因此不需要去溢料(de-flash)製 程。此外,因為該晶片銲墊係經由該導線架之導線電性連 接至該基板’所以可避免因連接線(bonding wires)太長 而導致導電效能(electrical performance)降低,以及伴 隨電阻增加的散熱問題。
第6頁 445601 五、發明說明(4) 圖示說明: 為了讓本發明之上述和其他目的、特徵、和優點能更 明顯特徵,下文特舉本發明較佳實施例,並配合所附圖 示,作詳細說明如下。 第1囷:習知球格陣列封裝構造之剖面圖; 第2圖:另一習知球格陣列封裝構造之剖面圖; 第3圖:本發明之第一較佳實施例之剖面示圖; 第4圖:根據本發明之第一較佳實施例尚未進行注膠 封裝前之示意圖;及 第5圖:本發明之第二較佳實施例之剖面示圖; 第6囷:根據本發明之第二較佳實施例尚未進行注膠 封裝前之示意圖。 圖號說明: 100 習 用 球 格 陣 列封 裝構造 112 晶 片 114 基 板 116 銲 整* 117 封 膠 體 118 連 接 線 119 錫 球 200 封 裝 構 造 224 晶 片 225 基 板 226 連 接 線 228 下 封 膠體 310 基 板 312 凹 部 314 晶 片 承 座 316 基 板 銲 墊 318 錫 球 330 導 線 架 332 導 線 3 3 2a 内 腳 部 分 3 3 2b 外 腳 部 分 334 絕 緣 層 336 連 接 線 338 τ^τ 溫 銲 錫 350 半 導 體 晶 片
第7頁 :^ 4456 五、發明說明(5) 3 5 2 晶片銲墊 354 銀膠 3 7 0 封膠體 發明說明: 請參照第三圈以及第四圖,其係根據本發明之第一較 佳實施例’其主要包含一基板310、兩導線架330、兩半導 體晶片350以及一封膠體370包覆該導線架330以及半導體 晶片350使其與外界隔絕。該基板310之正面設有一凹部 312用以容置該半導體晶片350。該基板310之凹部312較佳 設有一晶片承座314以增加該基板310之剛性(rigidity)。 該基板310之正面設有複數個基板銲墊316(contact pads),該基板31 〇之背面設有複數個錫球3 1 8,用以與外 界電性溝通’該每一個錫球3 18係分別電性連接至相對應 的基板銲墊316。該半導體晶片350具有複數個晶片銲墊 352位於該晶片350之上表面中央,用以電性連接至該晶片 之内部電路。該半導體晶片3 5 0之下表面係以黏著劑(如 銀膠3 54)固設於該晶片承座314 »該導線架330包含複數 條導線332且具有内腳部分(inner lead portion)332a以 及外聊部分(outer lead portion)332b,該複數條導線 332之内腳部分332a以一絕緣層334固設於該晶片350之上 表面。該每一條導線332之内腳部分332a係以連接線336連 接至相對應的晶片銲墊35 2,該複數條導線332之外腳部分 332b係以高溫銲錫338連接至相對應的基板銲墊352 ^可以 理解的是,該複數條導線之外腳部分亦可先以不導電膠例 如環氧樹脂(epoxy)固設於該基板之正面,再以連接線
第8頁 4456 ο ) 五、發明說明(6) (bonding wires)連接至相對應的基板鲜塾。 請再參照第三圖,該基板31 〇係以不導電材質[例如 FR-4玻璃環氧樹脂(glass-epoxy)或聚醢亞胺 (polyimide)]製成。該晶片承座314以及導線架3 3 0較佳係 由銅、鐵、鎳或其合金製成。此外該複數條導線3 32可以 鍍上一層高導電物質例如銀、銅、金或鈀。該絕緣層334 係為三層構造,其包含一聚醯亞胺(polyimide)基層夾在 兩熱可塑(thermoplastic)膠層間,其可事先藉由一熱壓 機(heater press)加熱加壓後,再黏貼至該複數條導線 332之内腳部分332a以及該晶片350之上表面。該複數條連 接線3 36可以一打線機將其分別連接至每一條導線33 2之内 腳部分332a以及相對應的晶片銲墊352 〇該高溫銲錫338 — 般係為高船銲錫材料(high lead solder material),較 佳為5%錫及95%鉛。錫球318係以共晶銲錫材料(eutectic solder material)形成,較佳為63%錯及37¾錯。該封勝體 3 7 0之材質係為絕緣材料,較佳之塑料(mol ding compound)為 Hitachi Chemical Company 提供之 CEL-9200XU 塑料。 請再參照第四圖’其係本發明第一較佳實施例尚未進 行注膠封裝前之示意圖’其中該兩半導體晶350係為彼此 直列。此外’用以接合該複數條導線之内腳部分至該晶片 之上表面的絕緣層3 3 4係被沿著該複數條導線3 3 2之内腳部 分332a切割成梳子狀。因為該絕緣層334之熱膨脹係數 (thermal expansion c oe f f i c i en t)與該複數條導線 3 3 2 及
第9頁 '44560] 五、發明說明(7) 晶片3 5 0差異極大,所以該絕緣層3 34之接合面積越大則越 易因長期溫度差異造成的熱脹冷縮而脫落。因此,將該絕 緣層3 34沿著該複數條導線3 3 2之内腳部分33 2a切割成梳子 狀可以減少其接合面積,因而可降低其分離之機率。 請參照第五圖以及第六圖,其係為根據本發明之第二 較佳實施例,其主要包含一基板3 1 0、兩導線架3 3 0、兩半 導體晶片3 5 0以及一封膠體3 7 0,其中該每一半導體晶片 350係為並列。該基板310之正面設有兩凹部312用以容置 該半導體晶片3 5 0。根據本發明之第二較佳實施例,除了 該每一半導體晶片350以及該每一導線架330係為並列之 外,其餘之結構以及連接關係大致類同於第一較佳實施 例。 根據本發明之晶片嵌入式球格陣列封裝構造,其基板 不需要具有槽縫也可用以封裝銲墊位於中央之晶片。由於 該半導體晶片係設於該基板正面之凹部,且該晶片係經由 在基板正面之導線架電性連接至該基板,所以該封膠體只 需包覆該基板之正面,因此該基板之背面不會有溢料情形 產生,所以不需要去溢料(de-flash)製程來確保設於基板 背面之複數個錫球的鲜料連接可靠性(solder joint rel i abi 1 i ty) »此外,因為該晶片銲墊係經由該導線架之 導線電性連接至該基板,所以可避免因連接線太長而導致 導電效能降低,以及伴隨電阻增加的散熱問題。(因為如 果沒有導線架且基板不開槽縫,則銲墊位於中央之晶片必 須直接以連接線電性連接至基板,則其連接線會變得太長
,.4456。445 6 01 五、發明說明(8) 而導致導電效能降低,以及伴隨電阻增加的散熱問題)。 雖然本發明已以前述較佳實施例揭示,然其並非用以 限定本發明,任何熟習此技藝者,在不脫離本發明之精神 和範圍内,當可作各種之更動與修改。例如根據本發明之 晶片嵌入式球格陣列封裝構造,其雖然以包含兩個半導體 晶片之多晶片球格陣列封裝構造為較佳實施例,然而可以 理解的是根據本發明之晶片嵌入式球格陣列封裝構造其也 可只包含單一個半導體晶片或是兩個以上之半導體晶片。 因此本發明之保護範圍當視後附之申請專利範圍所界定者 為準。
Claims (1)
- 445601 t、申請專利範圍 1 、一種具有導線架之晶片嵌入式球格陣列封裝構造,其 係包含: 至少一半導體晶片,具有一上表面以及一下表面,該 晶片具有複數個晶片銲墊位於該晶片之上表面中央用以電 性連接至該晶片之内部電路; —基板,具有正面以及背面,該基板之正面至少設有 一凹部用以容置該至少一半導體晶片,該基板之正面設有 複數個基板銲墊,該基板之背面設有複數個錫球用以與外 界電性溝通,該每一個錫球係分別電性連接至相對應的基 板銲墊; 一導線架,包含複數條導線具有内腳部分以及外腳部 分,該複數條導線之内腳部分係以一絕緣層固設於該晶片 之上表面,該複數條導線之外腳部分係以不導電膠固設於 該基板之正面,該每一條導線之内腳部分電性連接至相對 應的晶片銲墊,該每一條導線之外腳部分電性連接至相對 應的基板銲墊;及 一封膠體包覆該至少一半導體晶片以及導線架使其與 外界隔絕"445601 六、申請專利範圍 造,其中該基板之凹部係設有一晶片承座,該每一半導體 晶片係固設於該晶片承座。 4 、依申請專利範圍第1項之晶片嵌入式球格陣列封裝構 造,其包含至少兩半導體晶片以及兩導線架,其中該每一 半導體晶片係為彼此直列。 5 、依申請專利範圍第1項之晶片嵌入式球格陣列封裝構 造,其包含至少兩半導體晶片以及兩導線架,其中該基板 係設有相對應數目之凹部用以容置該半導艎晶片,且該每 一半導體晶片係為並列。第13頁
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US8237249B2 (en) | 2009-03-27 | 2012-08-07 | Chipmos Technologies Inc. | Stacked multichip package |
TWI705543B (zh) * | 2015-10-23 | 2020-09-21 | 日商新光電氣工業股份有限公司 | 引線架及其製造方法 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US8237249B2 (en) | 2009-03-27 | 2012-08-07 | Chipmos Technologies Inc. | Stacked multichip package |
TWI705543B (zh) * | 2015-10-23 | 2020-09-21 | 日商新光電氣工業股份有限公司 | 引線架及其製造方法 |
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