TW426983B - Method and apparatus for high-performance integrated circuit interconnect fabrication - Google Patents

Method and apparatus for high-performance integrated circuit interconnect fabrication Download PDF

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Publication number
TW426983B
TW426983B TW087115586A TW87115586A TW426983B TW 426983 B TW426983 B TW 426983B TW 087115586 A TW087115586 A TW 087115586A TW 87115586 A TW87115586 A TW 87115586A TW 426983 B TW426983 B TW 426983B
Authority
TW
Taiwan
Prior art keywords
layer
patent application
item
scope
copper
Prior art date
Application number
TW087115586A
Other languages
English (en)
Chinese (zh)
Inventor
Mehrdad M Moslehi
Original Assignee
Cvc Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cvc Inc filed Critical Cvc Inc
Application granted granted Critical
Publication of TW426983B publication Critical patent/TW426983B/zh

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684Smoothing; Planarisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32131Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
TW087115586A 1997-09-18 1998-10-31 Method and apparatus for high-performance integrated circuit interconnect fabrication TW426983B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US93342097A 1997-09-18 1997-09-18

Publications (1)

Publication Number Publication Date
TW426983B true TW426983B (en) 2001-03-21

Family

ID=25463916

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087115586A TW426983B (en) 1997-09-18 1998-10-31 Method and apparatus for high-performance integrated circuit interconnect fabrication

Country Status (5)

Country Link
EP (1) EP1018149A1 (ja)
JP (1) JP2001516970A (ja)
KR (1) KR20010024096A (ja)
TW (1) TW426983B (ja)
WO (1) WO1999014800A1 (ja)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6221612B1 (en) 1997-08-01 2001-04-24 Aurora Biosciences Corporation Photon reducing agents for use in fluorescence assays
KR100338112B1 (ko) * 1999-12-22 2002-05-24 박종섭 반도체 소자의 구리 금속 배선 형성 방법
KR20040007862A (ko) * 2002-07-11 2004-01-28 주식회사 하이닉스반도체 반도체 소자의 구리 배선 형성 방법
US7232766B2 (en) * 2003-03-14 2007-06-19 Lam Research Corporation System and method for surface reduction, passivation, corrosion prevention and activation of copper surface
US6821899B2 (en) * 2003-03-14 2004-11-23 Lam Research Corporation System, method and apparatus for improved local dual-damascene planarization
KR100764054B1 (ko) * 2006-08-22 2007-10-08 삼성전자주식회사 금속배선 및 그 형성 방법
CA2667640C (en) 2006-12-01 2016-10-04 D-Wave Systems, Inc. Superconducting shielding for use with an intergrated circuit for quantum computing
WO2013180780A2 (en) * 2012-03-08 2013-12-05 D-Wave Systems Inc. Systems and methods for fabrication of superconducting integrated circuits
CN110462857B (zh) 2017-02-01 2024-02-27 D-波系统公司 用于制造超导集成电路的系统和方法
US20200152851A1 (en) 2018-11-13 2020-05-14 D-Wave Systems Inc. Systems and methods for fabricating superconducting integrated circuits

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5292393A (en) * 1986-12-19 1994-03-08 Applied Materials, Inc. Multichamber integrated process system
US5478780A (en) * 1990-03-30 1995-12-26 Siemens Aktiengesellschaft Method and apparatus for producing conductive layers or structures for VLSI circuits
US5284804A (en) * 1991-12-31 1994-02-08 Texas Instruments Incorporated Global planarization process
US5354712A (en) * 1992-11-12 1994-10-11 Northern Telecom Limited Method for forming interconnect structures for integrated circuits

Also Published As

Publication number Publication date
JP2001516970A (ja) 2001-10-02
WO1999014800A1 (en) 1999-03-25
KR20010024096A (ko) 2001-03-26
EP1018149A1 (en) 2000-07-12

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