TW425620B - Method for forming a spin-on-glass layer - Google Patents

Method for forming a spin-on-glass layer Download PDF

Info

Publication number
TW425620B
TW425620B TW088112087A TW88112087A TW425620B TW 425620 B TW425620 B TW 425620B TW 088112087 A TW088112087 A TW 088112087A TW 88112087 A TW88112087 A TW 88112087A TW 425620 B TW425620 B TW 425620B
Authority
TW
Taiwan
Prior art keywords
layer
sog
isolation
item
patent application
Prior art date
Application number
TW088112087A
Other languages
Chinese (zh)
Inventor
Seung-Jin Lee
Original Assignee
Hyundai Electronics Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Ind filed Critical Hyundai Electronics Ind
Application granted granted Critical
Publication of TW425620B publication Critical patent/TW425620B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/312—Organic layers, e.g. photoresist
    • H01L21/3121—Layers comprising organo-silicon compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Application Of Or Painting With Fluid Materials (AREA)
  • Coating Apparatus (AREA)

Abstract

There is provided a method for forming a SOG layer, which can enhance flatness. In the method, the SOG layer is spin-coated on a wafer and the SOG solvent is spread in a closed receptacle containing the wafer to make a saturated vapor pressure in the receptacl. Thus, the SOG layer can be more flattened and be obtained with larger thickness than that of the prior art to enhance the productivity. The present invention can also maximally suppress the production of edge beads generated by spin coating and inhibit the bowing generated during etching of the SOG layer for forming a contact hole, with enhancing the flatness.

Description

A7 4 2弓620 ________B7_______ ^、發明說明（/ ) 本發明之領域 本發明俺闋於一種製造半導體器件之領域：更特別的 ，其係鬭於形成自旋玻璃層之方法•其可增強做為雇舆 層間隔離層的自旋玻璃層（以下簡稱30G層）之平坦性並 且增強其生産力。 習知技藝說明 一般而言，SOG層僳輔由自旋式塗覆（Spin coating) 所形成•在自旋式塗覆之前•先將矽氣烷或矽酸麴溶解 或分散於溶剤中而形成G溶液·接著透遇噴嘴的散佈， 將該形成的SO G溶液以自旋式塗覆在晶蹰上而形成S0G 層。其後，此塗佈層經過烘烤或硬化進行縮合反醮· 第1圖葆一剖面匪，顯示一種依據習知技蘸製作S0G 層的開放型接受器。在此閿放型接受器Μ中設有一晶 圃支撐桿20。並顯示有一晶鼷3 0置放在與此支播桿連着 的支撐板之上。在此以厢放型接受器進行作自旋式塗霣 的例子中，其塗覆作楽傜在常壓下進行9 現今及將來的趨勢•僳為多層金屬結構中方向比随替 半導髂裝置之高積體傾向而變离。雖然可使用S0G溶液 本身的流動來達成埋層之小孔和平坦性，然而卽使在以 自旋式塗费此SO G層之後，並未完全逹到其平坦性。 更進一步地，以一次自旋式塗覆所形成的S0G層的 厚度你局限在某籲值之内，因為該塗佈的S0 6溶液在自 旋式塗覆作業進行基間會失去流動性。例如，當SO G層 為自矽氧烷或其衍生物的溶液時，若要以一次自旋式塗 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公釐） • II I----------J -----訂 *-------- t請先閱讀背面之注意事項再填寫本頁) ---^^ ' 經濟部智慧財產局員工消費合作杜印製 經濟部智慧財產局員工消費合作社印製 4 256 2 0 A7 _____B7 五、發明說明（> ) 覆來形成厚度大於2 0 0 G A的s 0 6層是頻1為困難的4因此· 在習知技蕤中，在一具有金靨架嫌圓樣40之晶國30上· 形成第一層s 0 G層5 1之後（如附鬭2 a所示 >，再於第一J1 SOG雇51之上形成第二雇SOG層52(如附第2b晒所示 >。意 即，依所痛要的SOG層厚度來決定自旋式塗覆的次數 。例如，當所痛要的SOG層厚度大於2D00A,自旋式塗 覆的次數就應該多增加一次或者一次以上。 如前述銳明，為了要形成所痛要的306層厚度，躭驩 該多進行幾次自旋式塗覆•因此，存在於習知技®中的 問題，傺為此重覆相同的程序而降低了生産力* 尚有S—櫥問题，即當在後鑛作業中形成接*孔時， 在此接諝孔側邊曹因蝕刻羧留物霣而産生弓狀物（bowi-ng)。此問题乃肇因於在金羼架線上之S06層部位比其它 部位來的摩，而此較厚部位則源自於平坦性不足· 仍有另一铕問題，即傳統自旋式塗覆會迪成珠嫌（edge bead) , 因而 增加了 晶圔於 後鑛作 業期閜 ϋ 部位破 -·:善' 、.入 損的機會》 本發明之概要A7 4 2 Bow 620 ________B7_______ ^ Field of the invention (/) Field of the invention The present invention lies in the field of manufacturing semiconductor devices: more specifically, it belongs to the method of forming a spin glass layer. It can be reinforced as The flatness of the spin glass layer (hereinafter referred to as the 30G layer) of the interlayer isolation layer is used to enhance its productivity. Description of known techniques Generally speaking, the SOG layer is formed by spin coating. • Prior to spin coating. • Dissolve or disperse silane or silicate in solution. The G solution was then sprayed through the nozzle, and the formed SO G solution was spin-coated on the crystal grate to form a SOG layer. Thereafter, this coating layer is baked or hardened for condensation. Figure 1 shows a cross-section bandage, showing an open-type receiver for dipping the SOG layer according to conventional techniques. A crystal support rod 20 is provided in the placement type receiver M. It is shown that a crystal cymbal 30 is placed on the supporting plate connected to this seeding rod. In this example, a box-type receiver is used for spin coating. Its coating is applied under normal pressure. 9 Current and future trends. The high volume of the device tends to detach. Although the flow of the SOG solution itself can be used to achieve the pores and flatness of the buried layer, the flatness of the SOG layer was not fully achieved after the SOG layer was spin-coated. Furthermore, the thickness of the SOG layer formed by one spin coating is limited to a certain value, because the coated SO 6 solution loses fluidity during the spin coating operation. For example, when the SO G layer is a solution of self-siloxane or its derivative, if the paper is to be spin-coated once, the Chinese national standard (CNS > A4 specification (210 X 297 mm) applies) II I- --------- J ----- Order * -------- tPlease read the notes on the back before filling out this page) --- ^^ '' Staff of Intellectual Property Bureau, Ministry of Economic Affairs Consumption Cooperation Du printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the Consumer Cooperatives 4 256 2 0 A7 _____B7 V. Description of the invention (>) Overlays to form s 0 with a thickness greater than 2 0 0 GA 6 layers are frequency 1 is difficult 4 Therefore, in the conventional technique, a first layer s 0 G layer 5 1 is formed on a crystal country 30 with a gold-shaped frame 40 that looks like a circle (as shown in Appendix 2 a > A second SOG layer 52 is formed on top of a J1 SOG layer 51 (as shown in Appendix 2b). This means that the number of spin coatings is determined according to the thickness of the SOG layer. For example, when The thickness of the critical SOG layer is greater than 2D00A, and the number of spin coatings should be increased one or more times. As mentioned above, in order to form the desired thickness of 306 layers, Huan Huan should perform several spins. Coating • Therefore, the problem existing in Know-how®, which reduces the productivity by repeating the same procedure. * There is still an S-cabinet problem, that is, when the connection hole is formed in the post-mine operation, the connection is performed here. On the side of the perforation hole, the bow is generated by etching the carboxyl residue 霣. This problem is caused by the friction of the S06 layer portion on the golden ridge line than other parts, and the thicker part is Due to insufficient flatness, there is still another problem, that is, the traditional spin coating will become edge bead, which increases the crystal 圔 in the post-mine operation period. .. Chance of Loss "Summary of the invention

因此，本發明的目的，换在提供一種用來形成sofl雇 的方法，其能增加平坦性P 又且，本發明的另一目的，係在提供一種用來龄〔成一 增強平坦性的SO G層的方法，其能極度壓制由自旋式 / ( 塗覆所造成的珠鐮之生成，並且在使S0G層形成接觸孔 的钱刻期間抑制弓狀物發生》 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I.------->---:------ f锖先聞讀背面之注碩再填寫本頁) 訂： ’線· A7 . 4,·2ί 上. Β7 五、發明說明（ 依據本發明的一具龌實施例，其提供了 一種形成自旋 玻璃（S06)層的方法，此SOG層會使半導體裝置平坦化， 此方法包括將自旋式塗料塗覆在晶圓之上以形成S0G層 的步嫌（第一步，>;及在一内含晶鬮的封閉式容器中散 佈SOG溶劑，並以旋轉方式使在此封閉式接受器中形成 飽和蒸氣應，而該SOG層表面變為平坦（第二籲步驟）》 依據本發明的方法，此SO G層供以自旋塗佈晶圔之上， 並且該S0G溶劑偽在一内含晶圓的封閉式接受器中散佈， 以使得在該接受器内形成飽和蒸氣壓；因此·能增加S〇G 層的厚度並且增強S0G層的平坦性。 附画之簡略説明 本發明之前述及其它目的以及特色，曹随如下的較佳 具觼丨|例之説明並结合附圈而變為淸楚，其中： 第葆一種接受器的剖面圖，其你依據習知技毎以 m isafs 〇 an ； 圖，肖顯示依據習知技睡並塗佈兩 次雇； 圖3圖係一受器的剖面圓，其依據本發明之一具鱷 實施例以形成S0G層； 第4圖你剖面圈顯示依據本發明之具釀實施例而塗佈 的s優 第傜顯示整個SGG層的厚度之分佈，其依據本發明 之具施例之方法使用酵性溶薄做為S0G的溶劑； 第傺顯示整掴S0G層的厚度之分佈，其依據本發明 -5- 本紙張尺度通用中國國家標準（CNS)A4規格（210 X 297公釐） -----!!·裝.1 I {請先閲讀背面之注专？W-項再填寫本頁) 訂 --線. 經濟部智慧財產扃員工消費合作杜印製 4 2 56 2 0 A7 _____B7_ 五、發明說明（4 ) 之方法使用醚性溶劑撖為SO G的溶劑。 較佳具釀實施例之詳细銳明 (請先閱讀背面之注項再填寫本頁) 本發明将透過後述之具龌資施例參照附圈，詳細説明· 第3麵你一種依據本發明之具醸實施例其用來形成S06 層之接受器的剖面國。第3画中，在内接受器10A中投有 一晶圔支撐样U0»晶園置於舆支播桿Π0連接的支捸板上 。在内接受器10 A上放置一内封Μ 1〇 B以構成一内含晶國 之封閉空間β在内接受器10 Α外面放置一外接受器20Αβ 並且在内接受器20Α外面置上一外封蓋20Ββ如此，外接 受器和外封蓋各自緊緊封住其相對應的内接受器和内封 蓋》 如圖所示，晶圓120被牢牢地固定在輿支播桿110連接 的支撐板上，且S0G溶液透過嘖嘴將此S0G溶液以自_塗 覆方式散佈在晶圃上（未顯示U而S0G溶劑則透遇i職敗 佈在内接受器中並且因而在此由内接受器10 A和内封鏟 10B所封住的封閉空間中構成飽和蒸氣辑β V此時,.在封 聞空間已蒸氣飽和的溶》1之敗佈作業可爸S06游ϋ覆/ 之同時、之前、或者之後進行。： 經濟部智慧財產局員工消費合作社印製 在本發明中，此S0G層可在晶麵之上形成第一麕隔離 層之後，再在此第一層隔離層之上形成第二層隔離層· 亦可在此S0G層上形成第三層隔離層*其中此第一 )|^隔 離層與第三層隔雄層可為傳統式隔離蘑例如氣化#靥、 四氟化三砂層、或者氰氣化矽層等β 此種30 6最好為具有侧鐽含（^823«+1基（此處^僳一自 本紙張尺度適用中國國家標準（CNS)A4規格<210 x 297公釐） 4rT ^ η Α7 Λ 9 : B7___ --, ，五、發明說明（Γ ) 然數）之有機矽酮類。而so 6溶商I最好為«性物質。在本 發明的具餹簧施例中，採用丙二酵二甲醚做為溶爾。不 遇，在本發明中，另可使用醇性物質做為溶劑，雖然其 在效能上不如》性物質· 藉箸S0G溶劑在内接受器1〇 A和内封蓋ΙίϊΒ所封住的封閉 空間内所構成的飽和蒸氣壓，因S0G會再溶回於溶劑使S06 塗層不致失去流動性之故，連鑛地在晶國上進行S0G溶液 之自旋塗覆作業是可行的》 接替，最好此SO G層應在300^0到500 ·(：的溫度下做硬化 處理》 圖顯示如前面方法所述在晶囫上形成S 06靥140 β 丨明之方法，此S0G層140可經一次自旋塗覆就形 技蕤法所塗佈者更大的厚度d並且其平坦性亦增 潁示整値SO G靥的厚度之分佈，其依據本發明之 醇性溶劑的溶劑。附圖5b亦顯示整値S0G 下表依據量測結果其使用酵性溶劑做 為S0G的溶劑以及依據测結果其使用醚性溶 阐做為S06的溶劑之S0G牖及均勻性做了比較β其 ΐ所使用的酵性溶劑為異丙酵，所使用的醚性溶劑為丙 二酵二甲醚，且其SO G材料為AG-2 U(聚甲基矽氧烷類物 g,由美國 Allide Signal Co.所提供}。 本紙張尺度適用中國國家標準（CNS>A4規格（210 x 297公釐） (請先間讀背面之注意事項再填寫本頁) C'-^^Γ 經濟部智慧財產局員工消費合作社印製Therefore, the object of the present invention is to provide a method for forming a sofl employment, which can increase the flatness P. Moreover, another object of the present invention is to provide an SO G for enhancing flatness. Layer method, which can extremely suppress the generation of bead sickle caused by spin / (coating, and suppress the occurrence of bows during the time of making the SOG layer to form a contact hole.) This paper size applies Chinese national standards ( CNS) A4 specification (210 X 297 mm) I .------- > ---: ------ f 锖 read the note on the back before filling in this page) Order: 'Line · A7. 4, · 2ί. B7 V. Description of the Invention (According to a specific embodiment of the present invention, it provides a method for forming a spin glass (S06) layer. This SOG layer will flatten the semiconductor device. This method includes the step of applying a spin coating on a wafer to form a SOG layer (the first step, >), and dispersing the SOG solvent in a closed container containing crystal osmium, and rotating the solution. The saturated vapor should be formed in this closed receptacle, and the surface of the SOG layer becomes flat (second step). In the method of the invention, the SO G layer is provided on a spin-coated wafer, and the SOG solvent is spread in a closed receiver containing a wafer, so that a saturated vapor pressure is formed in the receiver; Therefore, the thickness of the SOG layer can be increased and the flatness of the SOG layer can be enhanced. The attached picture briefly describes the foregoing and other objects and features of the present invention. And it becomes 淸 chu, where: The first section of the receiver is a cross-section of which you use misafs 〇an according to the conventional technique; Figure, Xiao shows that you sleep and apply two jobs according to the conventional technique; Figure 3 A cross section of a receiver is formed according to one embodiment of the present invention to form a SOG layer; FIG. 4 shows a cross section of a cross section of the present invention showing a coating of the entire SGG layer. The thickness distribution, according to the method of the present invention, uses a fermented solvent as the solvent for SOG; the first one shows the distribution of the thickness of the entire SOG layer, which is based on the present invention. -5- The paper size is common in China. Standard (CNS) A4 specification (210 X 297 mm) ----- !! · Packing. 1 I (Please read the note on the back? W-item and then fill out this page) Order-line. Intellectual property of the Ministry of Economic Affairs and employee cooperation cooperation printed 4 2 56 2 0 A7 _____B7_ 5. Description of the invention (4 ) Method uses an ethereal solvent 撖 is a solvent of SO G. It is preferred to have detailed details of the brewing example (please read the note on the back before filling out this page) The present invention will be referred to through the following examples with detailed information Attached circle, detailed explanation. • On the third side, you have a cross-section of a receiver according to an embodiment of the present invention that is used to form a S06 layer. In the third picture, a crystal support type U0 is cast into the inner receiver 10A. »Jingyuan is placed on the support plate connected to the support rod Π0. An inner seal M 10B is placed on the inner receiver 10 A to form a closed space containing a crystal kingdom. Β An outer receiver 20A β is placed outside the inner receiver 10 A and an outer cover is placed outside the inner receiver 20A. As for the cover 20Bβ, the outer receiver and the outer cover tightly seal the corresponding inner receiver and inner cover respectively. As shown in the figure, the wafer 120 is firmly fixed on the connecting rod 110. Support plate, and the SOG solution is spread on the crystal garden by self-coating through the nozzle (not shown U and the SOG solvent is encountered in the internal receiver, and therefore here) The saturated space β V is formed in the enclosed space enclosed by the receiver 10 A and the inner sealing shovel 10B. At this time, the failure of the saturated space in the sealed space》 1 can be done at the same time as S06. , Before, or after .: Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs in the present invention, this SOG layer can form a first chirped isolation layer on the crystal plane, and then over this first isolating layer. Form a second isolation layer · A third isolation layer can also be formed on this SOG layer * wherein this A) | ^ The isolation layer and the third male isolation layer can be traditional isolation mushrooms such as gasification # 靥, tetrafluoride trisand layer, or cyanide gas silicon layer. (^ 823 «+1 base (here ^ 僳 1) The paper size applies the Chinese National Standard (CNS) A4 specification < 210 x 297 mm) 4rT ^ η Α7 Λ 9: B7___-,, 5. Description of the invention (Γ) Natural number) of organic silicones. The so 6 solvent quotient I is preferably «sex substance. In the reeded embodiment of the present invention, malonate dimethyl ether is used as the solvent. However, in the present invention, another alcoholic substance can be used as a solvent, although its performance is not as good as that of a substance. • By using SOG solvent, the enclosed space enclosed by the inner receiver 10A and the inner cover Ι ϊ Β The saturated vapor pressure formed is because the S0G will be re-dissolved back to the solvent so that the S06 coating will not lose its fluidity. It is feasible to perform spin coating of the S0G solution on the crystalline country even at the mine site. The SO G layer should be hardened at a temperature of 300 ^ 0 to 500. The figure shows the method of forming S 06 靥 140 β on the crystal as described in the previous method. The SOG layer 140 can be processed once. The spin coating has a larger thickness d and a flatness which is increased by the coating method, showing the distribution of the thickness of the whole SO G, which is the solvent of the alcoholic solvent according to the present invention. Fig. 5b also Shows the whole SOG. The following table compares the SOG 结果 and homogeneity of the solvent based on the measurement results using a fermentive solvent as SOG and the ether based solvent based on the measurement results. Isozyme is the fermentative solvent, and dimethyl ether malonate is used as the ethereal solvent. And its SO G material is AG-2 U (polymethylsilane type g, provided by American Allide Signal Co.). This paper size is applicable to Chinese national standards (CNS > A4 size (210 x 297 mm)) (Please read the notes on the back before filling out this page) C '-^^ Γ Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs

4 256 2 0 A7 B7 五、發明說明u ) 酵性溶劑 醚性溶剤 S06塗層之平均厚度 3 3 1 0 . 5 2 A 3 3 4 1 . 3 5 Α 最小學度 3 1 48 . 4 5A 3 2 7 2 . 7 1 Α 最大厚度 34 1 7 . 54A 3 4 1 0 . 2 2 A 最大-最小 26S . 09 A 1 3 7 . 50 A 厚度均勻度 η 2% (諳先閱讀背面之注意事項再填寫本頁) •e. 上表中，厚度均勻度之數值的播得傜使用下列數學式ί ;其中均勻度愈小，平坦性愈佳* U ν 厚度均勻度（χ) = [(最大厚度-最小厚度u(2x厚度平均 值）]X 100 上面兩桓結果皆顯示其SOS層可經一次自旋塗輕形成 • . 比習知技薛者更大的厚度。此埤桌7亦顔示使用睛性溶爾 的S0 (5層的厚度大於使用_性溶劑的S&G層的厚度，並且 塗層厚度的均勻度前者亦較後者為佳》 雖然本發明僅針對某些固定的較佳具鱷實施例做説明 ，實尚可有其它的修改與變化可為之成就卻不傕離本發 明如下之申餹専利項目的精神與範豳。 -8- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) -線- Γ— 經濟部智慧財產局員工消費合作社印製 Γ Γ 經濟部智慧財產局員工消費合作社印製 符號之說明 ίο… 10Λ .. 10Β . 20Α . 20Β . 20 .. 30 .. 40 .. 51 .. 52 ., 110 . 120. 140 . Α7 4 256 2 0 Β7 __ ..開放式接受器 ..内接受器 ..内封蓋 ..外接受器 ..外封蓋 ..支撐稈 ,.晶圆 ..金釀架線画樣 ..第1S0G雇 ..第2S0G層 ..支撐稈 ..晶圓 …S0G層 -------------裝--------訂---------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）4 256 2 0 A7 B7 V. Description of the invention u) The average thickness of the S06 coating with a fermenting solvent, etheric solvent 3 3 1 0. 5 2 A 3 3 4 1. 3 5 Α minimum academic degree 3 1 48. 4 5A 3 2 7 2. 7 1 Α maximum thickness 34 1 7. 54A 3 4 1 0. 2 2 A maximum-minimum 26S. 09 A 1 3 7. 50 A thickness uniformity η 2% (谙 read the precautions on the back first (Fill in this page) • e. In the above table, the value of the thickness uniformity is broadcast using the following mathematical formula; where the smaller the uniformity, the better the flatness * U ν Thickness uniformity (χ) = [(Maximum thickness -Minimum thickness u (2x thickness average value)] X 100 The above two results show that the SOS layer can be lightly formed by a single spin coating. • Greater thickness than those skilled in the art. This table 7 is also shown The thickness of the S0 using the eye-soluble solvent is greater than the thickness of the S & G layer using the solvent, and the uniformity of the coating thickness is better than the latter. "Although the present invention is only for certain fixed better The embodiment is described as an example, but there are other modifications and changes that can be made without departing from the spirit and scope of the following claims of the present invention. -8 -This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -line-Γ-printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ίο… 10Λ .. 10Β. 20Α. 20Β. 20 .. 30 .. 40 .. 51 .. 52., 110. 120. 140. Α7 4 256 2 0 Β7 __ .. Open receiver .. Internal receiver .. Inner cover .. Outer receiver .. Outer cover .. Support stalk. Wafer .. Gold wine line drawing: 1S0G hire .. 2S0G layer .. Support stalk .. Wafer ... S0G Layer ------------- install -------- order --------- line (please read the precautions on the back before filling this page) Applicable to China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

經濟部智慧財產局員工消費合作社印製 425620 锰 C8 D8六、申請專利範圍 1. 一種用來形成自旋玻璃（S0G)層之方法，其僳用於使 半導體器件平坦化，此方法包括的步®有： 將自旋式塗覆S0G溶液塗覆在一晶緬上，以使形成 S0G塗層（第一梅步驟）；並且 敗佈S0G溶劑在一内含晶圈的封閉式接受器中，並利 用自旋方式使在此接受罌内溝成一飽和蒸氣壓，而使 得S0G層的表面轉成平坦（第二餹步醣）》 2. 如申讅專利範園第1項之方法，其中所有第一泡步 朦和第二值步骤係皆在封閉式接受器中進行0 3. 如申誚専利範園第1項之方法，其中SO G溶劑的敝 佈作業葆在SO G雇的塗佈作業之同時、之前、或者之 後進行。 4. 如申誚専利範鼷第1項之方法，其中S0G溶爾為_性 溶劑或酵性溶用》 5. 如申餹専利範國第2項之方法，其中S0G溶薄為邂 性溶瘌或酵性溶繭β 6. 如申請專利範園第1項之方法，其中SO G溶劑為丙 二酵二甲醚· 7. 如申鵠《利範圔第2項之方法，其中SO G溶劑為丙 二醇二甲醚。 8. 如申讅專利範圍第1項之方法，其中在SO G層平坦 化之後，此方法進一步包括在300*0到50D°C硬化孩S0G 層之步驟。 9. 如申請専利範画第2項之方法，其中在S0G層平坦化 -1 0- --------.--「笨-- (請先閲讀背面之注項再填寫本頁) 打 本紙張尺度通用中國國家檁準（CNS ) A4规格（210X297公釐） f 經濟部智慧財產局員工消費合作社印製 Α8 Β8 C8 D8 425620 六、申請專利範圍 之後，此方法進一步包括在300 °C到500 °C硬化該SOG 層之步驟〇 10. 如申請專利範圍第1項之方法，其中S0G像由具有 侧鏈含Cxhx+i-i此處，X傺一自然數）之有機矽 酮物所構成。 11. 如申請專利範圄第2項之方法，其中S0G僳由具有槲 雜含CxH2x + i基（此處，X侮一自然數）之有機矽 嗣物所構成。 12 .如申請專利範圃第1項之方法，其中此方法進一步 包括步驟：在做為第二層隔離層之S0G層形成前，先在 晶圓上形成第一層隔離層；並且 視情況地在S06靥上形成第三層隔離雇，其中此SOG 層傜形成在第一層隔離層之上做為第二層隔離層β 13.如申請專利範圍第2項之方法，其中此方法進一步 包括步驟：在做為笫二層隔離層之S0G層形成前，先在 晶圓上形成第一層隔離層；並且 視情況地在S0G層上形成第三層隔離層；其中此SOG 層形成在第一層隔離層之上做為第二層隔離層《 • 14.如申請專利範圍第12項之方法，其中第一層隔離曆 以及第三層隔離層你分別為氧化矽層。 15. 如申請專利範圍第13項之方法，其中第一層隔離層 以及第三層隔離層偽分別為氣化矽層。 16. 如申請專利範圍第12項之方法，其中第一層隔雜層 以及第三層隔離層偽分別為氮氣化砂層。 -1 1 - ---------裝— (請先閱讀背面之注意事項再填寫本頁) '1Τ 線 本紙張尺度逍用中國國家梂準（CNS > Α4规格（210Χ297公釐） A8425620 驾 六、申請專利範圍 7 1X 中 層 離. 隔 曆 1 第 。 中層 其矽 ► 化 法氧 方氮 之為 項別 13分 第係 圔層 範離 利隔 專層 請三 第 及 % ---------;--1--------I I 訂· —-- <請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 2 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 425620 Manganese C8 D8 6. Scope of Patent Application 1. A method for forming a spin-glass (S0G) layer, which is used to flatten semiconductor devices, the method includes the steps ®Yes: Apply a spin-coated SOG solution on a crystal to form an SOG coating (the first plum step); and dissolve the SOG solvent in a closed receiver containing a crystal ring, And the spin method is used to make the receiving pit inside the trench to a saturated vapor pressure, so that the surface of the SOG layer becomes flat (second step sugar). 2. The method of item 1 of Shenyang Patent Fanyuan, where all The first foaming step and the second value step are both performed in a closed receiver. 3. The method of item 1 of Shenliliyuan Garden, in which the SO G solvent is applied and the coating is applied in SO G. Work at the same time, before, or after. 4. For example, the method of item 1 in the application, where SOG solvent is used as a solvent or fermentative solution. 5. For method of item 2 in the application, where the solution is SOG solution Or fermented cocoon β 6. If the method of applying for patent No. 1 in the patent application, the SO G solvent is malonase dimethyl ether. Propylene glycol dimethyl ether. 8. The method of claim 1, wherein after the SO G layer is flattened, the method further includes the step of hardening the SOG layer at 300 * 0 to 50D ° C. 9. If you apply for the method of the second item of the Fanli painting, which is to flatten the S0G layer -1 0 ---------.-- "Stupid-- (Please read the note on the back before filling this page ) The size of the paper used is in accordance with China National Standards (CNS) A4 (210X297 mm) f Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A8 Β8 C8 D8 425620 6. After applying for a patent, this method is further included at 300 ° Step of hardening the SOG layer from C to 500 ° C. 10. As the method of the scope of patent application No. 1, wherein the SOG image is made of an organic silicone material having a side chain containing Cxhx + ii (here, X 傺 a natural number). Composition. 11. The method according to item 2 of the patent application, wherein SOG is composed of an organosilicon with a CxH2x + i group (here, X is a natural number) containing mistletoe. 12. As a patent application The method of Fanpu Item 1, wherein the method further includes the steps of: forming a first isolation layer on the wafer before forming the SOG layer as the second isolation layer; and optionally forming it on S06 靥The third layer of isolation is employed, where this SOG layer is formed on top of the first layer of isolation as a second layer Isolation layer β 13. The method according to item 2 of the scope of patent application, wherein the method further includes the step of: forming a first isolation layer on the wafer before forming the SOG layer as the second isolation layer; and A third isolation layer is formed on the S0G layer; the SOG layer is formed on the first isolation layer as the second isolation layer. “14. The method according to item 12 of the patent application, where the first The layer isolation calendar and the third isolation layer are respectively silicon oxide layers. 15. For the method of the 13th scope of the patent application, the first isolation layer and the third isolation layer are pseudo-gasified silicon layers. 16. For example, the method of claim 12 of the patent scope, in which the first layer of impurity barrier layer and the third layer of isolation layer are pseudo-nitrogenated sand layers respectively. -1 1---------- 装 — (Please read the back first Please note this page before filling in this page) '1T line paper size standard Chinese national standard (CNS > A4 size (210 × 297 mm) A8425620 driving six, patent application scope 7 1X middle layer. Interval 1st. Middle layer its Silicon ► 13 points of chemical oxygen and nitrogen Please refer to the third layer and the second layer of the Fan Lili special layer. ---------;-1 -------- II Order --- < Please read the notes on the back first (Fill in this page again.) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 2 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm).
TW088112087A 1998-10-29 1999-07-16 Method for forming a spin-on-glass layer TW425620B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019980045677A KR100314806B1 (en) 1998-10-29 1998-10-29 Method for forming spin on glass layer

Publications (1)

Publication Number Publication Date
TW425620B true TW425620B (en) 2001-03-11

Family

ID=19556021

Family Applications (1)

Application Number Title Priority Date Filing Date
TW088112087A TW425620B (en) 1998-10-29 1999-07-16 Method for forming a spin-on-glass layer

Country Status (4)

Country Link
US (1) US6313044B1 (en)
JP (1) JP3554686B2 (en)
KR (1) KR100314806B1 (en)
TW (1) TW425620B (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4334168B2 (en) * 2001-09-25 2009-09-30 東京応化工業株式会社 Film formation method
US20030224105A1 (en) * 2002-05-30 2003-12-04 Symyx Technologies, Inc. Apparatus and methods for forming films on substrates
US20040071888A1 (en) * 2002-05-30 2004-04-15 Symyx Technologies, Inc. Apparatus and method of research for creating and testing thin films
US20040102022A1 (en) * 2002-11-22 2004-05-27 Tongbi Jiang Methods of fabricating integrated circuitry
US7435692B2 (en) * 2005-10-19 2008-10-14 Tokyo Electron Limited Gas jet reduction of iso-dense field thickness bias for gapfill process
JP4542977B2 (en) * 2005-10-27 2010-09-15 東京エレクトロン株式会社 Coating film forming method and apparatus

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63158853A (en) 1987-12-11 1988-07-01 Chiyou Lsi Gijutsu Kenkyu Kumiai Method of forming multilayer interconnection
JPH03287163A (en) 1990-04-02 1991-12-17 Hitachi Ltd Pattern forming method, mask forming method by using same, and this mask
JP2748612B2 (en) 1989-11-14 1998-05-13 富士通株式会社 Method for manufacturing semiconductor device
JPH03261145A (en) 1990-03-12 1991-11-21 Fujitsu Ltd Method of flattening surface of semiconductor device
JPH04174342A (en) 1990-08-01 1992-06-22 Sharp Corp Method for evaluating performance of liquid for forming sog file and its performance evaluation mechanism as well as manufacture of semiconductor device utilizing its performance evaluation method
US5527872A (en) 1990-09-14 1996-06-18 At&T Global Information Solutions Company Electronic device with a spin-on glass dielectric layer
JPH04131853A (en) 1990-09-21 1992-05-06 Dainippon Printing Co Ltd Method for correcting phase shift photomask
JPH04153651A (en) 1990-10-18 1992-05-27 Dainippon Printing Co Ltd Photomask having phase shift layer
US5314724A (en) * 1991-01-08 1994-05-24 Fujitsu Limited Process for forming silicon oxide film
JP2665404B2 (en) 1991-02-18 1997-10-22 シャープ株式会社 Method for manufacturing semiconductor device
US5759923A (en) 1991-02-25 1998-06-02 Symetrix Corporation Method and apparatus for fabricating silicon dioxide and silicon glass layers in integrated circuits
EP0560617A3 (en) 1992-03-13 1993-11-24 Kawasaki Steel Co Method of manufacturing insulating film on semiconductor device and apparatus for carrying out the same
JP3155631B2 (en) 1992-10-16 2001-04-16 日立建機株式会社 Lifting equipment for construction machinery
JP3214186B2 (en) 1993-10-07 2001-10-02 三菱電機株式会社 Method for manufacturing semiconductor device
CN1125481A (en) * 1994-03-11 1996-06-26 川崎制铁株式会社 Method of evaluating siloxane used for forming insulation coating, coating fluid used for forming insulation coating, process for producing the fluid, process for forming insulation coating for.......
JP3407086B2 (en) 1994-06-17 2003-05-19 日本テキサス・インスツルメンツ株式会社 Method for manufacturing semiconductor device
KR0128806B1 (en) * 1994-07-06 1998-04-07 김주용 Interlayer insulating film forming method of semiconductor device
US5889330A (en) 1995-03-10 1999-03-30 Mitsubishi Denki Kabushiki Kaisha Semiconductor device whose flattening resin film component has a controlled carbon atom content
US5723264A (en) 1996-03-14 1998-03-03 Eastman Kodak Company Pattern transfer techniques for fabrication of lenslet arrays using specialized polyesters
EP0849774B1 (en) 1996-12-19 2004-12-15 Texas Instruments Incorporated System and method for delivering a spin-on-glass on a substrate
US5855962A (en) 1997-01-09 1999-01-05 International Business Machines Corporation Flowable spin-on insulator
US5883011A (en) 1997-06-18 1999-03-16 Vlsi Technology, Inc. Method of removing an inorganic antireflective coating from a semiconductor substrate
JP3819604B2 (en) * 1998-08-31 2006-09-13 株式会社東芝 Deposition method

Also Published As

Publication number Publication date
JP2000138214A (en) 2000-05-16
KR20000027686A (en) 2000-05-15
US6313044B1 (en) 2001-11-06
KR100314806B1 (en) 2002-02-19
JP3554686B2 (en) 2004-08-18

Similar Documents

Publication Publication Date Title
TW451000B (en) Plasma treatment method and apparatus thereof
TW425620B (en) Method for forming a spin-on-glass layer
Tsaur et al. Epitaxial alignment of polycrystalline Si films on (100) Si
JPH02236282A (en) Production of silicon-containing coating,using organosilicic compound and nitrogen trifluoride
US6482751B2 (en) Titanium dioxide layer serving as a mask and its removed method
TWI273652B (en) Method of preparing the surface of a Si substrate or layer or source and drain recess of semiconductor elements for depositing an epitaxial layer of SiGe
CN100350589C (en) Shallow trench isolation method forming round corners by cleaning
US5966616A (en) Method of manufacturing a semiconductor device having "shallow trench isolation"
US20120180716A1 (en) Methods for epitaxial silicon growth
CN109904070A (en) A kind of substrate edge processing method of diameter wafers
JP2945234B2 (en) Method of forming semiconductor thin film
TW314657B (en) Manufacturing method of passivating thin film by NH3
CN108726524A (en) The technique that MFI-type molecular screen membrane is prepared using the method for heat treatment seed layer
TW436928B (en) Method for forming field oxide layer
JPH07297151A (en) Fabrication of semiconductor device
TW392249B (en) Method of removing polysilicon residue after formation of field oxide by wet etching
TW388070B (en) Method for an inductively coupled plasma chemical vapor deposition and thin amorphous silicon film transistor utilizing thereof
JPS5544772A (en) Manufacture of semiconductor
JPS6425555A (en) Trench forming method
JPH06177142A (en) Fabrication of transistor
TW445578B (en) Method of forming shallow trench isolation free of kink effect
TW439198B (en) A method to prevent the recess of silicon oxide layer in the shallow trench isolation process
TW201015641A (en) A method for mounting a thinned semiconductor wafer on a carrier substrate for further processing
JP3354947B2 (en) Semiconductor substrate manufacturing method
JPH06349801A (en) Surface treatment method

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees