KR0128806B1 - Interlayer insulating film forming method of semiconductor device - Google Patents
Interlayer insulating film forming method of semiconductor deviceInfo
- Publication number
- KR0128806B1 KR0128806B1 KR1019940016083A KR19940016083A KR0128806B1 KR 0128806 B1 KR0128806 B1 KR 0128806B1 KR 1019940016083 A KR1019940016083 A KR 1019940016083A KR 19940016083 A KR19940016083 A KR 19940016083A KR 0128806 B1 KR0128806 B1 KR 0128806B1
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- KR
- South Korea
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- film
- sog film
- interlayer insulating
- sog
- semiconductor device
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02334—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment in-situ cleaning after layer formation, e.g. removing process residues
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Formation Of Insulating Films (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
제 1a도 내지 제1d도는 본 발명에 의한 반도체 소자의 층간 절연막 형성단계를 도시한 소자의 단면도.1A to 1D are cross-sectional views of a device showing a step of forming an interlayer insulating film of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 웨이퍼 2 : 금속배선1: wafer 2: metal wiring
3 : 제 1CVD 산화막 4 : SOG막3: first CVD oxide film 4: SOG film
5 : 알콜성분의 미립자 6 : 제 2CVD 산화막5: alcoholic fine particles 6: second CVD oxide film
본 발명은 반도체 소자의 층간 절연막 형성방법에 관한 것으로,특히단차비(aspect ratio)가 높은 토폴러지(topology)를 갖는 웨이퍼 표면을 평탄화하기 위하여 SOG막을 표함하는 적층구조의 층간 절연막을 형성 할 때, SOG막을 도포한 후 인-시투(in-situ)로 알콜성분용액을 분사시켜 SOG막을 일정두께만큼 희석시키면서 원심력에 의해 SOG막의 희석된 부분을 제거하여 표면 평탄화를 이룰 수 있는 반도체 소자의 층간 절연막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an interlayer insulating film of a semiconductor device, and more particularly, when forming an interlayer insulating film having a stacked structure including an SOG film to planarize a wafer surface having a high topology ratio. After the SOG film is applied, the alcohol component solution is sprayed in-situ to dilute the SOG film by a certain thickness while removing the diluted portion of the SOG film by centrifugal force to form an interlayer insulating film of a semiconductor device that can achieve surface planarization. It is about a method.
집적도가 높은 반도체 소자에서 금속배선을 다층으로 할 경우 금속배선 사이의 층간 절연막의 평탄화가 금속배선의 신뢰도를 향상시키기 위해 중요하다. 층간 절연막은 단층 또는 적층 구조를 갖는데, 단차비가 높은 토폴지를 갖는 웨이퍼 표면의 평탄화를 향상시키기 위하여 SOG막이 포함된 적층구조의 층간 절연막이 많이 사용된다. 그러나 SOG막 자체에 다량 함유된 수분으로 인하여 소자의 신뢰성을 저하시키는 문제점이 있다. 종래 SOG막을 사용하는 층간 절연막 형성공정은 SOG막을 도포한 후 블랭켓 에치 백(blanket etch back) 공정없이 적용하거나, SOG막을 도포한 후 블랭켓 에치 백 공정을 실시하여 적용하는 두가지 방법이 있다. 블랭켓 에치 백 공정없이 SOG막을 적용할 경우 하부 금속배선에 상부 금속배선을 연결하기 위한 콘택홀 형성시 SOG막이 콘택홀 측벽에서 노출됨에 의해 금속배선의 신뢰성을 저하시키게 된다. 이러한 문제점을 해결하는 방안으로 SOG막 도포후 큐링(curing)한 다음 블랭켓 에치 백 공정을 실시하여 후속공정으로 형성되는 콘택홀 측벽에 SOG막의 노출을 방지한다. 그러나 에치 백 공정시 폴리머와 같은 파티클의 발생과 균일도 및 재현성이 어렵다는 문제가 있다. 따라서, 본 발명은 SOG막을 도포한 후 알콜성분용액을 이용하여 인-시투로 블랭켓 에치 백하여 공정을 단순화 시키면서 신뢰성을 향상시킬 수 있는 반도체 소자의 층간 절연막을 형성하는 방법을 제공함에 그 목적이 있다.When the metal wiring is multi-layered in a semiconductor device with high integration, planarization of the interlayer insulating film between the metal wirings is important for improving the reliability of the metal wiring. The interlayer insulating film has a single layer or a lamination structure, and in order to improve the planarization of the surface of the wafer having a high topology, a lamination structure including a SOG film is often used. However, there is a problem in that the reliability of the device is lowered due to the moisture contained in the SOG film itself. There are two methods of forming an interlayer insulating film using a conventional SOG film without applying a blanket etch back process after applying the SOG film, or by applying a blanket etch back process after applying the SOG film. When the SOG film is applied without the blanket etch back process, the SOG film is exposed on the sidewalls of the contact hole when forming the contact hole for connecting the upper metal wire to the lower metal wire, thereby reducing the reliability of the metal wire. In order to solve this problem, the SOG film is coated and then cured, followed by a blanket etch back process to prevent the SOG film from being exposed to the sidewalls of the contact holes formed in a subsequent process. However, there is a problem that generation and uniformity and reproducibility of particles such as polymers are difficult during the etch back process. Accordingly, an object of the present invention is to provide a method for forming an interlayer insulating film of a semiconductor device which can improve the reliability while simplifying the process by blanket-etching in-situ using an alcohol solution after applying the SOG film. have.
이러한 목적을 달성하기 위한 본 발명의 층간 절연막 형성방법은 하부층으로 제 1CVD 산화막(3)을 형성한 후 웨이퍼를 회전시키면서 상기 제1CVD 산화막(3)상에 SOG막(4)을 소정두께로 도포하는 단계와, 상기 단계로부터 상기 SOG막(4)상에 알콜성분용액을 분사시켜 알콜성분용액의 미립자(5)가 SOG막(4)을 일정두께 희석시키는 단계와, 상기 단계로부터 웨이퍼의 회전에 의한 원심력으로 상기 SOG막 (4)의 희석된 부분을 제거하는 단계와, 상기 단계로부터 남아있는 SOG막 (4)을 큐링하고, 그 상부에 제 2CVD 산화막(6)을 형성하는 단계로 이루어지는 것을 특징으로 한다.The interlayer insulating film forming method of the present invention for achieving this purpose is to form a first CVD oxide film 3 as a lower layer, and then to apply a SOG film 4 to the first CVD oxide film 3 to a predetermined thickness while rotating the wafer. And spraying an alcohol component solution onto the SOG film 4 from the step so that the fine particles 5 of the alcohol component solution dilute the SOG film 4 to a predetermined thickness, and by rotating the wafer from the step. Removing the diluted portion of the SOG film 4 by centrifugal force, and curing the remaining SOG film 4 from the step, and forming a second CVD oxide film 6 thereon. do.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다. 제1a도 내지 제1d도는 본 발명에 의한 반도체 소자의 층간 절연막 형성단계를 도시한 소자의 단면도로서, 제1a도는 소정의 공정을 거친 웨이퍼(1)상에 다수의 금속배선(2)이 형성된 상태에서, 전체구조 상부에 제 1CVD 산화막(3)을 형성한 상태를 도시한 것이다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. 1A to 1D are cross-sectional views of a device showing a step of forming an interlayer insulating film of a semiconductor device according to the present invention, and FIG. 1A is a state in which a plurality of metal wires 2 are formed on a wafer 1 that has undergone a predetermined process. In the figure, a state in which the first CVD oxide film 3 is formed on the entire structure is shown.
제1b도는 상기 제 1CVD 산화막(3) 상에 SOG막(4)을 소정두께로 도포한 상태를 도시한 것이다. 제1c도는 상기 SOG막(4) 도포후 인-시투로 알콜성분의 용액을 분사시켜 알콜성분용액의 미립자(5)가 SOG막(4)을 일정두께 희석시킨 상태를 도시한 것이다. 상기에서 알콜성분용액의 분사는 초음파를 사용한 매우 작은 노즐(nozzle)을 통해 분사되며, 더욱 작은 미립자를 만들기 위해 N2, Ar 등의 비활성개스를 불어넣어준다. 제1d도는 상기 알콜성분용액에 의해 희석된 SOG막(4)을 제거하고, 남아있는 SOG막(4)을 큐링한 후 전체구조 상부에 제2CVD 산화막(6)을 형성하여 제 1CVD 산화막(3), SOG막(4) 및제2 CVD 산화막(6)의 적층구조로된 층간 절연막을 형성한 상태를 도시한 것이다.FIG. 1B shows a state in which the SOG film 4 is applied on the first CVD oxide film 3 to a predetermined thickness. FIG. 1C shows a state in which the fine particles 5 of the alcohol component solution are diluted with a predetermined thickness by spraying an alcohol component solution in-situ after the application of the SOG film 4. In the above, the injection of the alcohol component solution is injected through a very small nozzle using ultrasonic waves, and blows an inert gas such as N 2 or Ar to make smaller particles. FIG. 1d illustrates the removal of the SOG film 4 diluted by the alcohol component solution, the remaining SOG film 4 being cured, and a second CVD oxide film 6 formed on the entire structure to form the first CVD oxide film 3. And an interlayer insulating film having a laminated structure of the SOG film 4 and the second CVD oxide film 6 are shown.
본 발명에 의하면, SOG막(4) 도포후 인-시투로 알콜성분용액을 SOG막(4)에 분사시켜 SOG막(4)의 점성도를 낮추고, 웨이퍼의 회전에 의한 원심력으로 점성도가 낮아진 SOG막(4)을 제거한다. 그리고 상기 알콜성분용액을 분사하고 희석된 SOG막(4)을 제거하는 방법은 2가지가 있는데, 첫째 웨이퍼를 회전시키면서 SOG막(4)을 도포한 후 웨이퍼 회전을 정지한 상태에서 알콜성분용액을 분사하고, 이후 웨이퍼를 회전시켜 희석된 SOG막(4)을 제거하는 방법이 있고, 둘째, 웨이퍼를 회전시키면서 SOG막(4)을 도포한 후 웨이퍼가 회전하는 상태로 알콜성분용액을 분사하면서 희석되는 SOG막(4)을 제거하는 방법이 있다. 첫째방법은 SOG막(4)이 두껍게 도포되었을 때 사용하고, 둘째방법은 SOG막(4)이 얇게 도포되었을 때 주로 사용한다. 상술한 바와 같이 층간 절연막 평탄화 공정으로 SOG막을 사용할 때, SOG막을 알콜성분용액으로 점성도를 낮추어 원심력으로 제거하되, SOG막 도포후 인-시투로 공정이 행해지므로써 단순한 공정으로 층간 절연막의 평탄화를 이룰 수 있고 소자의 신뢰성을 향상시킬 수 있다.According to the present invention, after applying the SOG film 4, the alcohol component solution is sprayed on the SOG film 4 by in-situ to lower the viscosity of the SOG film 4, and the SOG film whose viscosity is lowered by centrifugal force by the rotation of the wafer. Remove (4). There are two methods for spraying the alcohol component solution and removing the diluted SOG film (4). First, while applying the SOG film (4) while rotating the wafer, the alcohol component solution is stopped while the wafer rotation is stopped. Spraying, and then rotating the wafer to remove the diluted SOG film 4, and second, applying the SOG film 4 while rotating the wafer and diluting while spraying the alcohol component solution while the wafer is rotating. There is a method of removing the SOG film 4. The first method is used when the SOG film 4 is thickly applied. The second method is mainly used when the SOG film 4 is thinly coated. As described above, when the SOG film is used as the interlayer insulating film flattening process, the SOG film is removed by centrifugal force by lowering the viscosity with an alcohol-based solution, but after the SOG film is applied, the in-situ process is performed to achieve flattening of the interlayer insulating film in a simple process. And improve the reliability of the device.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940016083A KR0128806B1 (en) | 1994-07-06 | 1994-07-06 | Interlayer insulating film forming method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940016083A KR0128806B1 (en) | 1994-07-06 | 1994-07-06 | Interlayer insulating film forming method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960005933A KR960005933A (en) | 1996-02-23 |
| KR0128806B1 true KR0128806B1 (en) | 1998-04-07 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940016083A KR0128806B1 (en) | 1994-07-06 | 1994-07-06 | Interlayer insulating film forming method of semiconductor device |
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| KR (1) | KR0128806B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100314806B1 (en) * | 1998-10-29 | 2002-02-19 | 박종섭 | Method for forming spin on glass layer |
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1994
- 1994-07-06 KR KR1019940016083A patent/KR0128806B1/en not_active IP Right Cessation
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| KR960005933A (en) | 1996-02-23 |
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