TW364161B - Semiconductor and method relating to semiconductors - Google Patents
Semiconductor and method relating to semiconductorsInfo
- Publication number
- TW364161B TW364161B TW086103707A TW86103707A TW364161B TW 364161 B TW364161 B TW 364161B TW 086103707 A TW086103707 A TW 086103707A TW 86103707 A TW86103707 A TW 86103707A TW 364161 B TW364161 B TW 364161B
- Authority
- TW
- Taiwan
- Prior art keywords
- area
- semiconductor
- semiconductors
- areas
- doped
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 2
- 229920005591 polysilicon Polymers 0.000 abstract 2
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 238000000926 separation method Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Inorganic Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Bipolar Transistors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE9700773A SE519628C2 (sv) | 1997-03-04 | 1997-03-04 | Tillverkningsförfarande för halvledarkomponent med deponering av selektivt utformat material,vilket är ogenomträngligt för dopjoner |
Publications (1)
Publication Number | Publication Date |
---|---|
TW364161B true TW364161B (en) | 1999-07-11 |
Family
ID=20406016
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW086103707A TW364161B (en) | 1997-03-04 | 1997-03-24 | Semiconductor and method relating to semiconductors |
Country Status (10)
Country | Link |
---|---|
US (2) | US6140194A (zh) |
EP (1) | EP0966757A1 (zh) |
JP (1) | JP2001513945A (zh) |
KR (1) | KR20000075706A (zh) |
CN (1) | CN1249848A (zh) |
AU (1) | AU6644398A (zh) |
CA (1) | CA2283396A1 (zh) |
SE (1) | SE519628C2 (zh) |
TW (1) | TW364161B (zh) |
WO (1) | WO1998039797A1 (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI554710B (zh) * | 2015-02-24 | 2016-10-21 | 蔡晉暉 | 手電筒改良結構 |
TWI655772B (zh) * | 2017-05-05 | 2019-04-01 | 旺宏電子股份有限公司 | 半導體元件 |
US10256307B2 (en) | 2017-05-08 | 2019-04-09 | Macronix International Co., Ltd. | Semiconductor device |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001127071A (ja) * | 1999-08-19 | 2001-05-11 | Hitachi Ltd | 半導体装置及びその製造方法 |
US7432179B2 (en) * | 2004-12-15 | 2008-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Controlling gate formation by removing dummy gate structures |
US7701034B2 (en) * | 2005-01-21 | 2010-04-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy patterns in integrated circuit fabrication |
US7939384B2 (en) * | 2008-12-19 | 2011-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Eliminating poly uni-direction line-end shortening using second cut |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4110126A (en) * | 1977-08-31 | 1978-08-29 | International Business Machines Corporation | NPN/PNP Fabrication process with improved alignment |
JPS57500219A (zh) * | 1980-02-22 | 1982-02-04 | ||
JPS5737870A (en) * | 1980-08-20 | 1982-03-02 | Toshiba Corp | Semiconductor device |
EP0122004A3 (en) * | 1983-03-08 | 1986-12-17 | Trw Inc. | Improved bipolar transistor construction |
US4573256A (en) * | 1983-08-26 | 1986-03-04 | International Business Machines Corporation | Method for making a high performance transistor integrated circuit |
GB2172744B (en) * | 1985-03-23 | 1989-07-19 | Stc Plc | Semiconductor devices |
US4962053A (en) * | 1987-01-30 | 1990-10-09 | Texas Instruments Incorporated | Bipolar transistor fabrication utilizing CMOS techniques |
US4866001A (en) * | 1988-07-01 | 1989-09-12 | Bipolar Integrated Technology, Inc. | Very large scale bipolar integrated circuit process |
EP0414013A3 (en) * | 1989-08-23 | 1991-10-16 | Texas Instruments Incorporated | Method for forming bipolar transistor in conjunction with complementary metal oxide semiconductor transistors |
US5212397A (en) * | 1990-08-13 | 1993-05-18 | Motorola, Inc. | BiCMOS device having an SOI substrate and process for making the same |
US5406113A (en) * | 1991-01-09 | 1995-04-11 | Fujitsu Limited | Bipolar transistor having a buried collector layer |
JP3798808B2 (ja) * | 1991-09-27 | 2006-07-19 | ハリス・コーポレーション | 高いアーリー電壓,高周波性能及び高降伏電壓特性を具備した相補型バイポーラトランジスター及びその製造方法 |
US5389561A (en) * | 1991-12-13 | 1995-02-14 | Sony Corporation | Method for making SOI type bipolar transistor |
US5326710A (en) * | 1992-09-10 | 1994-07-05 | National Semiconductor Corporation | Process for fabricating lateral PNP transistor structure and BICMOS IC |
US5416031A (en) * | 1992-09-30 | 1995-05-16 | Sony Corporation | Method of producing Bi-CMOS transistors |
DE4308958A1 (de) * | 1993-03-21 | 1994-09-22 | Prema Paezisionselektronik Gmb | Verfahren zur Herstellung von Bipolartransistoren |
US5451532A (en) * | 1994-03-15 | 1995-09-19 | National Semiconductor Corp. | Process for making self-aligned polysilicon base contact in a bipolar junction transistor |
US5516708A (en) * | 1994-11-17 | 1996-05-14 | Northern Telecom Limited | Method of making single polysilicon self-aligned bipolar transistor having reduced emitter-base junction |
US5489541A (en) * | 1995-04-14 | 1996-02-06 | United Microelectronics Corporation | Process of fabricating a bipolar junction transistor |
US5708287A (en) * | 1995-11-29 | 1998-01-13 | Kabushiki Kaisha Toshiba | Power semiconductor device having an active layer |
-
1997
- 1997-03-04 SE SE9700773A patent/SE519628C2/sv not_active IP Right Cessation
- 1997-03-24 TW TW086103707A patent/TW364161B/zh active
-
1998
- 1998-03-03 US US09/033,714 patent/US6140194A/en not_active Expired - Fee Related
- 1998-03-04 EP EP98908408A patent/EP0966757A1/en not_active Withdrawn
- 1998-03-04 KR KR1019997007774A patent/KR20000075706A/ko not_active Application Discontinuation
- 1998-03-04 CA CA002283396A patent/CA2283396A1/en not_active Abandoned
- 1998-03-04 AU AU66443/98A patent/AU6644398A/en not_active Abandoned
- 1998-03-04 WO PCT/SE1998/000388 patent/WO1998039797A1/en not_active Application Discontinuation
- 1998-03-04 JP JP53844898A patent/JP2001513945A/ja active Pending
- 1998-03-04 CN CN98802982A patent/CN1249848A/zh active Pending
-
1999
- 1999-01-26 US US09/236,619 patent/US6153919A/en not_active Expired - Fee Related
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI554710B (zh) * | 2015-02-24 | 2016-10-21 | 蔡晉暉 | 手電筒改良結構 |
TWI655772B (zh) * | 2017-05-05 | 2019-04-01 | 旺宏電子股份有限公司 | 半導體元件 |
US10256307B2 (en) | 2017-05-08 | 2019-04-09 | Macronix International Co., Ltd. | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
AU6644398A (en) | 1998-09-22 |
SE9700773L (sv) | 1998-09-05 |
WO1998039797A1 (en) | 1998-09-11 |
SE519628C2 (sv) | 2003-03-18 |
SE9700773D0 (sv) | 1997-03-04 |
EP0966757A1 (en) | 1999-12-29 |
CA2283396A1 (en) | 1998-09-11 |
US6140194A (en) | 2000-10-31 |
JP2001513945A (ja) | 2001-09-04 |
US6153919A (en) | 2000-11-28 |
KR20000075706A (ko) | 2000-12-26 |
CN1249848A (zh) | 2000-04-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
ATE174123T1 (de) | Mikromechanische vorrichtung und verfahren zu deren herstellung | |
WO2000007218A3 (en) | Method for manufacturing a semiconductor device having a metal layer floating over a substrate | |
CA2279786A1 (en) | A composition and method for selectively etching a silicon nitride film | |
EP0899784A3 (en) | Semiconductor device and method of fabricating thereof | |
IE822900L (en) | Providing a groove in a substrate | |
EP0715344A3 (en) | Process for forming gate oxides possessing different thicknesses on a semiconductor substrate | |
EP1263062A3 (en) | Organic semiconductor device and process of manufacturing the same | |
AU2001249659A1 (en) | Method of forming vias in silicon carbide and resulting devices and circuits | |
CA2051556A1 (en) | Gas sensor | |
TW327700B (en) | The method for using rough oxide mask to form isolating field oxide | |
EP0971391A3 (en) | A method for reducing particles from an electrostatic chuck and an equipment for manufacturing a semiconductor | |
EP0236123A3 (en) | A semiconductor device and method for preparing the same | |
NL1012430A1 (nl) | Werkwijze voor het vervaardigen van halfgeleidereenheden, een etssamenstelling voor het vervaardigen van halfgeleidereenheden, en daarmee verkregen halfgeleidereenheden. | |
TW373256B (en) | A semiconductor device having discontinuous insulating regions and the manufacturing method thereof | |
WO2003034484A3 (en) | A method for forming a layered semiconductor structure and corresponding structure | |
EP0999584A3 (en) | Method for manufacturing semiconductor device | |
TW364161B (en) | Semiconductor and method relating to semiconductors | |
WO1996036067A3 (en) | Self-alignment technique for junction isolation and wells | |
EP0967649A3 (en) | Palladium surface coatings suitable for wirebonding and process for forming palladium surface coatings | |
EP1249862A3 (en) | Semiconductor device and method for forming the same | |
EP0856923A3 (en) | Method of manufacturing semiconductor device | |
TW357405B (en) | Method for pre-shaping a semiconductor substrate for polishing and structure | |
EP0930646A3 (en) | Lead-on-chip type semicoductor device having thin plate and method for manufacturing the same | |
EP0997996A3 (en) | Semiconductor device and method for fabricating the same | |
TW359005B (en) | Method for manufacturing mixed circuit bi-gap wall structure |