NL1012430A1 - Werkwijze voor het vervaardigen van halfgeleidereenheden, een etssamenstelling voor het vervaardigen van halfgeleidereenheden, en daarmee verkregen halfgeleidereenheden. - Google Patents

Werkwijze voor het vervaardigen van halfgeleidereenheden, een etssamenstelling voor het vervaardigen van halfgeleidereenheden, en daarmee verkregen halfgeleidereenheden.

Info

Publication number
NL1012430A1
NL1012430A1 NL1012430A NL1012430A NL1012430A1 NL 1012430 A1 NL1012430 A1 NL 1012430A1 NL 1012430 A NL1012430 A NL 1012430A NL 1012430 A NL1012430 A NL 1012430A NL 1012430 A1 NL1012430 A1 NL 1012430A1
Authority
NL
Netherlands
Prior art keywords
semiconductor units
manufacturing semiconductor
etching composition
obtained therewith
manufacturing
Prior art date
Application number
NL1012430A
Other languages
English (en)
Other versions
NL1012430C2 (nl
Inventor
Gyu-Hwan Kwag
Se-Jong Ko
Kyung-Seuk Hwang
Jun-Ing Gil
Sang-O Park
Dae-Hoon Kim
Sang-Moon Chun
Ho-Gyun Jung
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of NL1012430A1 publication Critical patent/NL1012430A1/nl
Application granted granted Critical
Publication of NL1012430C2 publication Critical patent/NL1012430C2/nl

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K13/00—Etching, surface-brightening or pickling compositions
    • C09K13/04—Etching, surface-brightening or pickling compositions containing an inorganic acid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Electrodes Of Semiconductors (AREA)
NL1012430A 1998-06-25 1999-06-24 Werkwijze voor het vervaardigen van halfgeleidereenheden, een etssamenstelling voor het vervaardigen van halfgeleidereenheden, en daarmee verkregen halfgeleidereenheden. NL1012430C2 (nl)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR19980024232 1998-06-25
KR19980024232 1998-06-25
KR19980031544 1998-08-03
KR1019980031544A KR100271769B1 (ko) 1998-06-25 1998-08-03 반도체소자의 제조방법, 이를 위한 반도체소자 제조용 식각액조성물 및 반도체소자

Publications (2)

Publication Number Publication Date
NL1012430A1 true NL1012430A1 (nl) 2000-01-04
NL1012430C2 NL1012430C2 (nl) 2004-10-13

Family

ID=26633814

Family Applications (1)

Application Number Title Priority Date Filing Date
NL1012430A NL1012430C2 (nl) 1998-06-25 1999-06-24 Werkwijze voor het vervaardigen van halfgeleidereenheden, een etssamenstelling voor het vervaardigen van halfgeleidereenheden, en daarmee verkregen halfgeleidereenheden.

Country Status (5)

Country Link
JP (3) JP4180741B2 (nl)
KR (1) KR100271769B1 (nl)
DE (1) DE19928570B4 (nl)
NL (1) NL1012430C2 (nl)
TW (1) TW478130B (nl)

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US20010054706A1 (en) * 1999-07-19 2001-12-27 Joseph A. Levert Compositions and processes for spin etch planarization
KR100641950B1 (ko) * 2000-06-27 2006-11-02 주식회사 하이닉스반도체 반도체소자의 콘택플러그 형성방법
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KR100372647B1 (ko) * 2000-10-13 2003-02-19 주식회사 하이닉스반도체 다마신 금속게이트 형성방법
WO2002044763A2 (en) * 2000-11-28 2002-06-06 Lightcross, Inc. Formation of a smooth surface on an optical component
JP3609761B2 (ja) 2001-07-19 2005-01-12 三洋電機株式会社 半導体装置の製造方法
KR100881388B1 (ko) * 2002-11-04 2009-02-05 주식회사 하이닉스반도체 반도체 소자의 제조 방법
KR100536593B1 (ko) * 2002-12-05 2005-12-14 삼성전자주식회사 선택적인 막 제거를 위한 세정 용액 및 그 세정 용액을사용하여 실리사이드 공정에서 막을 선택적으로 제거하는방법
JP4355201B2 (ja) * 2003-12-02 2009-10-28 関東化学株式会社 タングステン金属除去液及びそれを用いたタングステン金属の除去方法
US7351642B2 (en) * 2005-01-14 2008-04-01 Infineon Technologies Richmond, Lp Deglaze route to compensate for film non-uniformities after STI oxide processing
KR100624089B1 (ko) 2005-07-12 2006-09-15 삼성전자주식회사 패턴 형성 방법, 이를 이용한 다중게이트 산화막 및 플래쉬메모리 셀의 제조 방법
KR101264421B1 (ko) 2005-12-09 2013-05-14 동우 화인켐 주식회사 금속막 식각용액
US8466071B2 (en) 2006-01-31 2013-06-18 Sumco Corporation Method for etching single wafer
JP4906417B2 (ja) 2006-07-11 2012-03-28 ラピスセミコンダクタ株式会社 半導体装置の製造方法
KR100860367B1 (ko) * 2006-08-21 2008-09-25 제일모직주식회사 금속실리사이드막 대비 실리콘 산화막에 대한 상대적인 식각 선택성이 향상된 식각용액
JP5017709B2 (ja) 2006-09-07 2012-09-05 ジルトロニック アクチエンゲゼルシャフト シリコンウェーハのエッチング方法および半導体シリコンウェーハの製造方法
US8623236B2 (en) 2007-07-13 2014-01-07 Tokyo Ohka Kogyo Co., Ltd. Titanium nitride-stripping liquid, and method for stripping titanium nitride coating film
JP5047881B2 (ja) * 2007-07-13 2012-10-10 東京応化工業株式会社 窒化チタン剥離液、及び窒化チタン被膜の剥離方法
JP5439466B2 (ja) * 2011-12-26 2014-03-12 富士フイルム株式会社 シリコンエッチング方法、これに用いられるシリコンエッチング液、及びそのキット
KR101554190B1 (ko) * 2011-12-27 2015-09-18 후지필름 가부시키가이샤 반도체 기판 제품의 제조방법 및 이것에 이용되는 에칭방법
JP2014146623A (ja) * 2013-01-25 2014-08-14 Fujifilm Corp 半導体基板のエッチング方法、エッチング液及び半導体素子の製造方法
JP6454605B2 (ja) 2015-06-01 2019-01-16 東芝メモリ株式会社 基板処理方法および基板処理装置
JP6917807B2 (ja) * 2017-07-03 2021-08-11 東京エレクトロン株式会社 基板処理方法
JP7398969B2 (ja) 2019-03-01 2023-12-15 東京エレクトロン株式会社 基板処理方法、基板処理装置および記憶媒体

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Also Published As

Publication number Publication date
JP4180741B2 (ja) 2008-11-12
DE19928570B4 (de) 2008-04-10
JP2005057304A (ja) 2005-03-03
KR100271769B1 (ko) 2001-02-01
KR20000004840A (ko) 2000-01-25
NL1012430C2 (nl) 2004-10-13
JP2005045285A (ja) 2005-02-17
JP2000031114A (ja) 2000-01-28
TW478130B (en) 2002-03-01
JP4343084B2 (ja) 2009-10-14
DE19928570A1 (de) 1999-12-30

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RD2N Patents in respect of which a decision has been taken or a report has been made (novelty report)
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V1 Lapsed because of non-payment of the annual fee

Effective date: 20140101