TW358228B - Method of minimizing damage to gate dielectric layer during gate electrode plasma etching - Google Patents
Method of minimizing damage to gate dielectric layer during gate electrode plasma etchingInfo
- Publication number
- TW358228B TW358228B TW085106892A TW85106892A TW358228B TW 358228 B TW358228 B TW 358228B TW 085106892 A TW085106892 A TW 085106892A TW 85106892 A TW85106892 A TW 85106892A TW 358228 B TW358228 B TW 358228B
- Authority
- TW
- Taiwan
- Prior art keywords
- gate electrode
- forming
- layer
- plasma etching
- dielectric layer
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 2
- 238000001020 plasma etching Methods 0.000 title abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Drying Of Semiconductors (AREA)
- Electrodes Of Semiconductors (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW085106892A TW358228B (en) | 1996-06-08 | 1996-06-08 | Method of minimizing damage to gate dielectric layer during gate electrode plasma etching |
US08/697,024 US5759919A (en) | 1996-06-08 | 1996-08-16 | Method for reducing gate oxide damages during gate electrode plasma etching |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW085106892A TW358228B (en) | 1996-06-08 | 1996-06-08 | Method of minimizing damage to gate dielectric layer during gate electrode plasma etching |
Publications (1)
Publication Number | Publication Date |
---|---|
TW358228B true TW358228B (en) | 1999-05-11 |
Family
ID=21625279
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW085106892A TW358228B (en) | 1996-06-08 | 1996-06-08 | Method of minimizing damage to gate dielectric layer during gate electrode plasma etching |
Country Status (2)
Country | Link |
---|---|
US (1) | US5759919A (zh) |
TW (1) | TW358228B (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW526550B (en) * | 2000-10-26 | 2003-04-01 | United Microelectronics Corp | Conductive structure capable of preventing wafer from being damaged by plasma and method for producing the same |
US6635573B2 (en) * | 2001-10-29 | 2003-10-21 | Applied Materials, Inc | Method of detecting an endpoint during etching of a material within a recess |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4472237A (en) * | 1981-05-22 | 1984-09-18 | At&T Bell Laboratories | Reactive ion etching of tantalum and silicon |
US5030590A (en) * | 1989-06-09 | 1991-07-09 | Applied Materials, Inc. | Process for etching polysilicon layer in formation of integrated circuit structure |
JPH05121701A (ja) * | 1991-10-25 | 1993-05-18 | Rohm Co Ltd | Nand構造の半導体装置の製造方法 |
JP3179872B2 (ja) * | 1991-12-19 | 2001-06-25 | 東京エレクトロン株式会社 | エッチング方法 |
US5603848A (en) * | 1995-01-03 | 1997-02-18 | Texas Instruments Incorporated | Method for etching through a substrate to an attached coating |
-
1996
- 1996-06-08 TW TW085106892A patent/TW358228B/zh active
- 1996-08-16 US US08/697,024 patent/US5759919A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US5759919A (en) | 1998-06-02 |
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