TW353732B - Processing system and method of operation - Google Patents

Processing system and method of operation

Info

Publication number
TW353732B
TW353732B TW083105508A TW83105508A TW353732B TW 353732 B TW353732 B TW 353732B TW 083105508 A TW083105508 A TW 083105508A TW 83105508 A TW83105508 A TW 83105508A TW 353732 B TW353732 B TW 353732B
Authority
TW
Taiwan
Prior art keywords
execution
instruction
processing system
execution circuitry
response
Prior art date
Application number
TW083105508A
Other languages
English (en)
Inventor
Seung-Yoon Peter Song
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of TW353732B publication Critical patent/TW353732B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Hardware Redundancy (AREA)
  • Preparation Of Compounds By Using Micro-Organisms (AREA)
  • Communication Control (AREA)
  • Debugging And Monitoring (AREA)
TW083105508A 1994-03-31 1994-06-17 Processing system and method of operation TW353732B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US22099394A 1994-03-31 1994-03-31

Publications (1)

Publication Number Publication Date
TW353732B true TW353732B (en) 1999-03-01

Family

ID=22825892

Family Applications (1)

Application Number Title Priority Date Filing Date
TW083105508A TW353732B (en) 1994-03-31 1994-06-17 Processing system and method of operation

Country Status (13)

Country Link
US (1) US6041167A (zh)
EP (1) EP0753173B1 (zh)
JP (1) JP2742392B2 (zh)
KR (1) KR0145035B1 (zh)
CN (1) CN1099082C (zh)
AT (1) ATE177546T1 (zh)
CA (1) CA2137046C (zh)
DE (1) DE69417071T2 (zh)
HU (1) HUT75816A (zh)
PL (1) PL177392B1 (zh)
RU (1) RU2150738C1 (zh)
TW (1) TW353732B (zh)
WO (1) WO1995027246A1 (zh)

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WO1999008184A1 (en) * 1997-08-06 1999-02-18 Advanced Micro Devices, Inc. An apparatus and method for accessing special registers without serialization
JP5093237B2 (ja) * 2007-06-20 2012-12-12 富士通株式会社 命令処理装置
EP2169539A4 (en) * 2007-06-20 2010-12-29 Fujitsu Ltd INSTRUCTION MANAGEMENT DEVICE AND METHOD
US7913067B2 (en) * 2008-02-20 2011-03-22 International Business Machines Corporation Method and system for overlapping execution of instructions through non-uniform execution pipelines in an in-order processor
CN106030518B (zh) * 2014-03-27 2019-03-26 英特尔公司 用于整理和退出存储的处理器、方法、系统和装置
CN108255743A (zh) * 2017-12-06 2018-07-06 中国航空工业集团公司西安航空计算技术研究所 一种用于在染色内核中写回仲裁电路
KR102692866B1 (ko) * 2021-04-26 2024-08-08 한국전자통신연구원 컴퓨팅 자원 분할 운용 방법 및 장치

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US5051940A (en) * 1990-04-04 1991-09-24 International Business Machines Corporation Data dependency collapsing hardware apparatus
JPH06103494B2 (ja) * 1986-11-18 1994-12-14 株式会社日立製作所 ベクトル処理装置の制御方式
JPH02103656A (ja) * 1988-10-12 1990-04-16 Fujitsu Ltd 主記憶参照の遂次化制御方式
US5075840A (en) * 1989-01-13 1991-12-24 International Business Machines Corporation Tightly coupled multiprocessor instruction synchronization
JPH0630094B2 (ja) * 1989-03-13 1994-04-20 インターナショナル・ビジネス・マシーンズ・コーポレイション マルチプロセツサ・システム
JP2519798B2 (ja) * 1989-05-30 1996-07-31 富士通株式会社 多重プロセッサシステムにおけるシリアライズ機能の検証方式
US5136697A (en) * 1989-06-06 1992-08-04 Advanced Micro Devices, Inc. System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
US5129067A (en) * 1989-06-06 1992-07-07 Advanced Micro Devices, Inc. Multiple instruction decoder for minimizing register port requirements
US5075846A (en) * 1989-09-29 1991-12-24 Motorola, Inc. Memory access serialization as an MMU page attribute
US5471593A (en) * 1989-12-11 1995-11-28 Branigin; Michael H. Computer processor with an efficient means of executing many instructions simultaneously
US5487156A (en) * 1989-12-15 1996-01-23 Popescu; Valeri Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched
US5185871A (en) * 1989-12-26 1993-02-09 International Business Machines Corporation Coordination of out-of-sequence fetching between multiple processors using re-execution of instructions
JPH07101410B2 (ja) * 1990-01-17 1995-11-01 インターナショナル、ビジネス、マシーンズ、コーポレーション データ処理ネットワークにおいて逐次化手段の試験のため命令流の実行を同期させる方法
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JP2532300B2 (ja) * 1990-10-17 1996-09-11 三菱電機株式会社 並列処理装置における命令供給装置
JP2535252B2 (ja) * 1990-10-17 1996-09-18 三菱電機株式会社 並列処理装置
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Also Published As

Publication number Publication date
EP0753173B1 (en) 1999-03-10
JP2742392B2 (ja) 1998-04-22
KR0145035B1 (ko) 1998-08-17
EP0753173A1 (en) 1997-01-15
KR950027573A (ko) 1995-10-18
PL177392B1 (pl) 1999-11-30
CA2137046C (en) 2000-01-18
HU9602595D0 (en) 1996-11-28
DE69417071D1 (de) 1999-04-15
CN1099082C (zh) 2003-01-15
WO1995027246A1 (en) 1995-10-12
HUT75816A (en) 1997-05-28
US6041167A (en) 2000-03-21
DE69417071T2 (de) 1999-10-14
JPH07271582A (ja) 1995-10-20
RU2150738C1 (ru) 2000-06-10
CN1121210A (zh) 1996-04-24
PL316566A1 (en) 1997-01-20
ATE177546T1 (de) 1999-03-15
CA2137046A1 (en) 1995-10-01

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