TW347612B - Counter and semiconductor memory including the counter - Google Patents

Counter and semiconductor memory including the counter

Info

Publication number
TW347612B
TW347612B TW086112323A TW86112323A TW347612B TW 347612 B TW347612 B TW 347612B TW 086112323 A TW086112323 A TW 086112323A TW 86112323 A TW86112323 A TW 86112323A TW 347612 B TW347612 B TW 347612B
Authority
TW
Taiwan
Prior art keywords
counter
logic circuits
signal
circuits
semiconductor memory
Prior art date
Application number
TW086112323A
Other languages
English (en)
Inventor
Yutaka Shirai
Hiroyuki Koimuma
Original Assignee
Toshiba Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Co Ltd filed Critical Toshiba Co Ltd
Application granted granted Critical
Publication of TW347612B publication Critical patent/TW347612B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
TW086112323A 1996-08-30 1997-08-27 Counter and semiconductor memory including the counter TW347612B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23014696A JP3238076B2 (ja) 1996-08-30 1996-08-30 カウンタ回路及びこのカウンタ回路を備えた半導体記憶装置

Publications (1)

Publication Number Publication Date
TW347612B true TW347612B (en) 1998-12-11

Family

ID=16903317

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086112323A TW347612B (en) 1996-08-30 1997-08-27 Counter and semiconductor memory including the counter

Country Status (5)

Country Link
US (1) US6078636A (zh)
JP (1) JP3238076B2 (zh)
KR (1) KR100264463B1 (zh)
CN (1) CN1110900C (zh)
TW (1) TW347612B (zh)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6691261B1 (en) * 1999-10-01 2004-02-10 Agere Systems Inc. De-interleaver and method of de-interleaving
US6324238B1 (en) * 1999-12-15 2001-11-27 Stmicroelectronics S.R.L. Bit counter stage, particularly for memories
US6363032B2 (en) 2000-06-30 2002-03-26 Micron Technology, Inc. Programmable counter circuit for generating a sequential/interleave address sequence
US6215729B1 (en) * 2000-06-30 2001-04-10 Micron Technology, Inc. Programmable counter circuit for generating a sequential/interleave address sequence
US6545942B2 (en) * 2001-02-21 2003-04-08 Fujitsu Limited Semiconductor memory device and information processing unit
KR100424118B1 (ko) * 2001-05-03 2004-03-24 주식회사 하이닉스반도체 클럭 신호의 주파수 정보를 이용하여 셀 동작을 제어하는동기식 반도체 메모리 장치
US20090167373A1 (en) * 2005-06-30 2009-07-02 Nxp B.V. Multi-phase frequency divider
FR2895601A1 (fr) * 2005-12-22 2007-06-29 St Microelectronics Sa Diviseur de frequence binaire
CN101093994B (zh) * 2006-06-19 2011-08-17 浩凯微电子(上海)有限公司 集成电路芯片中的自纠错高速大范围梯状分频器
CN101320970B (zh) * 2007-06-05 2010-06-09 财团法人工业技术研究院 可编程整数/分数分频器
KR100954951B1 (ko) 2008-05-21 2010-04-27 주식회사 하이닉스반도체 카운팅 회로 및 이를 이용한 어드레스 카운터
US8799750B1 (en) * 2011-05-09 2014-08-05 Xilinx, Inc. Convolutional interleaver for bursty memory access
CN114822625A (zh) * 2022-05-23 2022-07-29 长鑫存储技术有限公司 计数器电路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2740063B2 (ja) * 1990-10-15 1998-04-15 株式会社東芝 半導体記憶装置
JPH07192461A (ja) * 1993-12-27 1995-07-28 Toshiba Corp 半導体記憶装置
JPH09282886A (ja) * 1996-01-19 1997-10-31 Sgs Thomson Microelectron Inc メモリセルへの書込の開始をトラッキングする回路及び方法
JPH09231764A (ja) * 1996-01-19 1997-09-05 Sgs Thomson Microelectron Inc バーストカウンタ回路及びその動作方法

Also Published As

Publication number Publication date
CN1110900C (zh) 2003-06-04
JP3238076B2 (ja) 2001-12-10
US6078636A (en) 2000-06-20
KR19980019210A (ko) 1998-06-05
CN1180960A (zh) 1998-05-06
JPH1074389A (ja) 1998-03-17
KR100264463B1 (ko) 2000-08-16

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees