TW339457B - Semiconductor device and the manufacturing method - Google Patents
Semiconductor device and the manufacturing methodInfo
- Publication number
- TW339457B TW339457B TW086110740A TW86110740A TW339457B TW 339457 B TW339457 B TW 339457B TW 086110740 A TW086110740 A TW 086110740A TW 86110740 A TW86110740 A TW 86110740A TW 339457 B TW339457 B TW 339457B
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor device
- scale
- manufacturing
- design
- formed onto
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8197528A JPH1041302A (ja) | 1996-07-26 | 1996-07-26 | 半導体装置およびその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW339457B true TW339457B (en) | 1998-09-01 |
Family
ID=16375974
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW086110740A TW339457B (en) | 1996-07-26 | 1997-07-25 | Semiconductor device and the manufacturing method |
Country Status (4)
Country | Link |
---|---|
US (1) | US5945740A (zh) |
JP (1) | JPH1041302A (zh) |
KR (1) | KR100256524B1 (zh) |
TW (1) | TW339457B (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19834234C2 (de) * | 1998-07-29 | 2000-11-30 | Siemens Ag | Integrierter Halbleiterchip mit Füllstrukturen |
KR100399441B1 (ko) * | 2001-06-29 | 2003-09-29 | 주식회사 하이닉스반도체 | 반도체 소자의 미세패턴 형성방법 |
KR100519795B1 (ko) * | 2003-02-07 | 2005-10-10 | 삼성전자주식회사 | 다층배선 형성을 위한 포토마스크 세트 및 이를 사용하여제조된 반도체장치 |
JP6617067B2 (ja) * | 2016-03-30 | 2019-12-04 | 日東電工株式会社 | 配線回路基板およびその製造方法 |
JP6795323B2 (ja) | 2016-04-07 | 2020-12-02 | 日東電工株式会社 | 配線回路基板およびその製造方法 |
JP6787693B2 (ja) * | 2016-06-07 | 2020-11-18 | 日東電工株式会社 | 配線回路基板の製造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62135837A (ja) * | 1985-12-10 | 1987-06-18 | Matsushita Electric Ind Co Ltd | ホトマスクおよびそれを用いた写真蝕刻法 |
JPS62234347A (ja) * | 1986-04-04 | 1987-10-14 | Seiko Epson Corp | 配線層の形成方法 |
JPS62279660A (ja) * | 1986-05-28 | 1987-12-04 | Seiko Epson Corp | 配線層の形成方法 |
JPH0574701A (ja) * | 1991-09-13 | 1993-03-26 | Hitachi Ltd | レジストパターン形成方法 |
-
1996
- 1996-07-26 JP JP8197528A patent/JPH1041302A/ja active Pending
-
1997
- 1997-07-25 TW TW086110740A patent/TW339457B/zh active
- 1997-07-26 KR KR1019970036388A patent/KR100256524B1/ko not_active IP Right Cessation
- 1997-07-28 US US08/901,765 patent/US5945740A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US5945740A (en) | 1999-08-31 |
KR980011730A (ko) | 1998-04-30 |
KR100256524B1 (ko) | 2000-06-01 |
JPH1041302A (ja) | 1998-02-13 |
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