TW333628B - Method, processor and computer system for interrupt control used for different lengths of commands that the interrupt command can be correctly executed. - Google Patents

Method, processor and computer system for interrupt control used for different lengths of commands that the interrupt command can be correctly executed.

Info

Publication number
TW333628B
TW333628B TW086108589A TW86108589A TW333628B TW 333628 B TW333628 B TW 333628B TW 086108589 A TW086108589 A TW 086108589A TW 86108589 A TW86108589 A TW 86108589A TW 333628 B TW333628 B TW 333628B
Authority
TW
Taiwan
Prior art keywords
command
interrupt
address
commands
processor
Prior art date
Application number
TW086108589A
Other languages
English (en)
Inventor
Kazuhiko Tanaka
Tooru Nojiri
Keiji Ojima
Kiyokazu Nishioka
Yoshitake Kurokawa
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW333628B publication Critical patent/TW333628B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/327—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for interrupts
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/262—Arrangements for next microinstruction selection
    • G06F9/268—Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Bus Control (AREA)
TW086108589A 1996-07-08 1997-06-19 Method, processor and computer system for interrupt control used for different lengths of commands that the interrupt command can be correctly executed. TW333628B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17777396A JP3439033B2 (ja) 1996-07-08 1996-07-08 割り込み制御装置及びプロセッサ

Publications (1)

Publication Number Publication Date
TW333628B true TW333628B (en) 1998-06-11

Family

ID=16036873

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086108589A TW333628B (en) 1996-07-08 1997-06-19 Method, processor and computer system for interrupt control used for different lengths of commands that the interrupt command can be correctly executed.

Country Status (4)

Country Link
US (1) US5815696A (zh)
JP (1) JP3439033B2 (zh)
KR (1) KR100291602B1 (zh)
TW (1) TW333628B (zh)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6016543A (en) * 1997-05-14 2000-01-18 Mitsubishi Denki Kabushiki Kaisha Microprocessor for controlling the conditional execution of instructions
US6546479B1 (en) * 1998-02-10 2003-04-08 Koninklijke Philips Electronics N.V. Reduced instruction fetch latency in a system including a pipelined processor
US6965991B1 (en) * 2000-05-12 2005-11-15 Pts Corporation Methods and apparatus for power control in a scalable array of processor elements
US6789184B1 (en) 2000-09-29 2004-09-07 Intel Corporation Instruction address generation and tracking in a pipelined processor
JP2002189603A (ja) * 2000-12-19 2002-07-05 Fujitsu Ltd 計算機とその制御方法
US6950150B2 (en) * 2001-06-11 2005-09-27 Analog Devices, Inc. Method and a processor for processing two digital video signals clocked by respective clock signals of identical frequency but with a constant phase shift therebetween
JP3738842B2 (ja) * 2002-06-04 2006-01-25 富士通株式会社 遅延分岐機能を備えた情報処理装置
JP4073721B2 (ja) * 2002-06-28 2008-04-09 株式会社ルネサステクノロジ データ処理装置
US7831979B2 (en) * 2004-04-28 2010-11-09 Agere Systems Inc. Processor with instruction-based interrupt handling
US8037468B2 (en) * 2006-08-02 2011-10-11 Sandisk Il Ltd. Methods for synchronous code retrieval from an asynchronous source
US8230198B2 (en) * 2006-08-02 2012-07-24 Sandisk Il Ltd. System for synchronous code retrieval from an asynchronous source
US8099559B2 (en) * 2007-09-11 2012-01-17 International Business Machines Corporation System and method for generating fast instruction and data interrupts for processor design verification and validation
US20090070570A1 (en) * 2007-09-11 2009-03-12 Shubhodeep Roy Choudhury System and Method for Efficiently Handling Interrupts
US7992059B2 (en) 2007-09-11 2011-08-02 International Business Machines Corporation System and method for testing a large memory area during processor design verification and validation
US8006221B2 (en) 2007-09-11 2011-08-23 International Business Machines Corporation System and method for testing multiple processor modes for processor design verification and validation
US8019566B2 (en) * 2007-09-11 2011-09-13 International Business Machines Corporation System and method for efficiently testing cache congruence classes during processor design verification and validation
US8473725B2 (en) * 2009-12-21 2013-06-25 Ceva D.S.P., Ltd. System and method for processing interrupts in a computing system
US11768689B2 (en) 2013-08-08 2023-09-26 Movidius Limited Apparatus, systems, and methods for low power computational imaging
US10001993B2 (en) 2013-08-08 2018-06-19 Linear Algebra Technologies Limited Variable-length instruction buffer management
WO2016016726A2 (en) * 2014-07-30 2016-02-04 Linear Algebra Technologies Limited Vector processor
CN108710506B (zh) * 2018-05-31 2021-01-22 北京智行者科技有限公司 车辆的指令处理方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4881196A (en) * 1985-02-19 1989-11-14 Mitsubishi Denki Kabushiki Kaisha Data transmission line branching system
EP0402524B1 (en) * 1988-11-25 1996-10-02 Nec Corporation Microcomputer capable of quickly processing a branch instruction code
US5287522A (en) * 1990-06-29 1994-02-15 Bull Hn Information Systems, Inc. External procedure invocation apparatus utilizing internal branch vector interrupts and vector address generation, in a RISC chip
JPH05143363A (ja) * 1991-11-19 1993-06-11 Toshiba Corp 割込み処理方式
JPH0749790A (ja) * 1993-06-01 1995-02-21 Matsushita Electric Ind Co Ltd プロセッサにおける割り込み制御方法及び割り込み制御回路
JP3159345B2 (ja) * 1993-07-02 2001-04-23 日本電気株式会社 パイプライン演算処理装置

Also Published As

Publication number Publication date
KR100291602B1 (ko) 2001-09-17
JP3439033B2 (ja) 2003-08-25
JPH1021074A (ja) 1998-01-23
US5815696A (en) 1998-09-29
KR980010764A (ko) 1998-04-30

Similar Documents

Publication Publication Date Title
TW333628B (en) Method, processor and computer system for interrupt control used for different lengths of commands that the interrupt command can be correctly executed.
GB2358943A (en) Memory controller which increases bus utilization by reordering memory requests
EP0374074A3 (en) Computer system having efficient data transfer operations
KR900012155A (ko) 데이타 처리 시스템
HK1049719A1 (en) Execution of multiple threads in a parallel processor
KR920001319A (ko) 처리기 및 처리기의 처리방법
HK1049899A1 (en) Sdram controller for parallel processor architecture
SG145543A1 (en) Allocation of data to threads in multi-threaded network processor
AU2003213840A8 (en) Memory system with burst length shorter than prefetch length
GB2325320A (en) Fast access to a shared resource on a computer bus
EP0388300A3 (en) Controller for direct memory access
EP0330226A3 (en) Apparatus of and method for executing subprogram in bank switching data processing system
KR970705080A (ko) 외부 메모리로의 액세스 요청을 파이프라이닝하는 마이크로프로세서(Microprocessor with Pipelined Access Request to External Memory)
EP0389175A3 (en) Data prefetch system
KR930700907A (ko) 스톨캐쉬를 제공하기 위한 장치 및 방법
JPS5779557A (en) Data processor
EP0240606A2 (en) Pipe-line processing system and microprocessor using the system
EP0299075A4 (en) TREATMENT UNIT HAVING AT LEAST ONE CO-OWNER.
EP1573517A3 (en) Method and apparatus for processing transactions in a data processing system
WO2001086432A3 (en) Cryptographic data processing systems, computer program products, and methods of operating same, using parallel execution units
KR880006607A (ko) 캐쉬 디렉토리 및 캐쉬 메모리를 가진 마이크로 프로세서 시스템
JPH03209543A (ja) パーソナルコンピュータ
ES2091606T3 (es) Sistema de ordenador.
US5619714A (en) Microcomputer having an instruction decoder with a fixed area and a rewritable area
KR970016886A (ko) 효율적인 파우어 온 초기화를 갖는 정보 처리 시스템