TW315515B - - Google Patents

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Publication number
TW315515B
TW315515B TW085115320A TW85115320A TW315515B TW 315515 B TW315515 B TW 315515B TW 085115320 A TW085115320 A TW 085115320A TW 85115320 A TW85115320 A TW 85115320A TW 315515 B TW315515 B TW 315515B
Authority
TW
Taiwan
Prior art keywords
wire
main surface
item
gasket
top surface
Prior art date
Application number
TW085115320A
Other languages
English (en)
Chinese (zh)
Original Assignee
Lucent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lucent Technologies Inc filed Critical Lucent Technologies Inc
Application granted granted Critical
Publication of TW315515B publication Critical patent/TW315515B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Combinations Of Printed Boards (AREA)
TW085115320A 1995-12-28 1996-12-11 TW315515B (https=)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US58022095A 1995-12-28 1995-12-28

Publications (1)

Publication Number Publication Date
TW315515B true TW315515B (https=) 1997-09-11

Family

ID=24320199

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085115320A TW315515B (https=) 1995-12-28 1996-12-11

Country Status (4)

Country Link
EP (1) EP0782191A2 (https=)
JP (1) JPH09186289A (https=)
KR (1) KR970053214A (https=)
TW (1) TW315515B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI799312B (zh) * 2022-07-05 2023-04-11 瑞昱半導體股份有限公司 輸出入埠電路及其晶片

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100467946B1 (ko) * 1997-01-24 2005-01-24 로무 가부시키가이샤 반도체 칩의 제조방법
DE19743264C2 (de) * 1997-09-30 2002-01-17 Infineon Technologies Ag Verfahren zur Herstellung einer Emulationsschaltkreisanordnung sowie Emulationsschaltkreisanordnung mit zwei integrierten Schaltkreisen
US6413797B2 (en) 1997-10-09 2002-07-02 Rohm Co., Ltd. Semiconductor device and method for making the same
CA2218307C (en) * 1997-10-10 2006-01-03 Gennum Corporation Three dimensional packaging configuration for multi-chip module assembly
JP2000164796A (ja) * 1998-11-27 2000-06-16 Nec Corp マルチチップモジュール
JP3512657B2 (ja) * 1998-12-22 2004-03-31 シャープ株式会社 半導体装置
JP3662461B2 (ja) * 1999-02-17 2005-06-22 シャープ株式会社 半導体装置、およびその製造方法
JP2001044358A (ja) * 1999-07-28 2001-02-16 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6605875B2 (en) 1999-12-30 2003-08-12 Intel Corporation Integrated circuit die having bond pads near adjacent sides to allow stacking of dice without regard to dice size
JP2001196529A (ja) * 2000-01-17 2001-07-19 Mitsubishi Electric Corp 半導体装置及びその配線方法
US6344401B1 (en) * 2000-03-09 2002-02-05 Atmel Corporation Method of forming a stacked-die integrated circuit chip package on a water level
KR100464561B1 (ko) * 2000-04-11 2004-12-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 이것의 제조방법
JP2002176137A (ja) 2000-09-28 2002-06-21 Toshiba Corp 積層型半導体デバイス
KR100537835B1 (ko) * 2000-10-19 2005-12-19 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조방법
DE60108413T2 (de) 2000-11-10 2005-06-02 Unitive Electronics, Inc. Verfahren zum positionieren von komponenten mit hilfe flüssiger antriebsmittel und strukturen hierfür
US6863209B2 (en) 2000-12-15 2005-03-08 Unitivie International Limited Low temperature methods of bonding components
JP3558595B2 (ja) * 2000-12-22 2004-08-25 松下電器産業株式会社 半導体チップ，半導体チップ群及びマルチチップモジュール
US6762122B2 (en) 2001-09-27 2004-07-13 Unitivie International Limited Methods of forming metallurgy structures for wire and solder bonding
EP1367646A1 (fr) * 2002-05-23 2003-12-03 Valtronic S.A. Module électronique
US7547623B2 (en) 2002-06-25 2009-06-16 Unitive International Limited Methods of forming lead free solder bumps
US7531898B2 (en) 2002-06-25 2009-05-12 Unitive International Limited Non-Circular via holes for bumping pads and related structures
US6960828B2 (en) 2002-06-25 2005-11-01 Unitive International Limited Electronic structures including conductive shunt layers
TWI225899B (en) 2003-02-18 2005-01-01 Unitive Semiconductor Taiwan C Etching solution and method for manufacturing conductive bump using the etching solution to selectively remove barrier layer
JP4406300B2 (ja) * 2004-02-13 2010-01-27 株式会社東芝 半導体装置及びその製造方法
JP4205613B2 (ja) * 2004-03-01 2009-01-07 エルピーダメモリ株式会社 半導体装置
US7427557B2 (en) 2004-03-10 2008-09-23 Unitive International Limited Methods of forming bumps using barrier layers as etch masks
JP4061551B2 (ja) * 2004-03-24 2008-03-19 サンケン電気株式会社 半導体装置
US7358174B2 (en) 2004-04-13 2008-04-15 Amkor Technology, Inc. Methods of forming solder bumps on exposed metal pads
US7700409B2 (en) 2004-05-24 2010-04-20 Honeywell International Inc. Method and system for stacking integrated circuits
US7863720B2 (en) 2004-05-24 2011-01-04 Honeywell International Inc. Method and system for stacking integrated circuits
FR2873853B1 (fr) * 2004-07-27 2006-12-15 St Microelectronics Sa Dispositif electronique comprenant plusieurs plaquettes de circuits empilees et procede de realisation d'un tel dispositif
JP4509052B2 (ja) 2005-03-29 2010-07-21 三洋電機株式会社 回路装置
SG130055A1 (en) 2005-08-19 2007-03-20 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
US7674701B2 (en) 2006-02-08 2010-03-09 Amkor Technology, Inc. Methods of forming metal layers using multi-layer lift-off patterns
US7932615B2 (en) 2006-02-08 2011-04-26 Amkor Technology, Inc. Electronic devices including solder bumps on compliant dielectric layers
JP5559452B2 (ja) 2006-12-20 2014-07-23 富士通セミコンダクター株式会社 半導体装置及びその製造方法
KR102190382B1 (ko) 2012-12-20 2020-12-11 삼성전자주식회사 반도체 패키지
KR102012505B1 (ko) 2012-12-20 2019-08-20 에스케이하이닉스 주식회사 토큰 링 루프를 갖는 스택 패키지

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI799312B (zh) * 2022-07-05 2023-04-11 瑞昱半導體股份有限公司 輸出入埠電路及其晶片

Also Published As

Publication number Publication date
KR970053214A (ko) 1997-07-29
JPH09186289A (ja) 1997-07-15
EP0782191A2 (en) 1997-07-02

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