TW289841B - Process of VLSI node contact under no isolation rule - Google Patents

Abstract

A method of fabricating electric node contact of integrated circuit on semiconductor substrate comprises the steps of: (1) supplying one semiconductor substrate with active area with field oxide isolation; (2) by first conductive layer with pattern on the substrate forming semiconductor device portion on the active area, and forming electric connection on other field oxide region; (3) on the patterned first conductive layer and around it depositing one insulator and planarizing it, therefore forming one planar insulator; (4) on the planarized insulator depositing second conductive layer; (5) via patterned photoresist mask on the second conductive layer by anisotropical etch etching opening of node contact, in which the opening aligns with the above active area and performs partial etching around edge of first patterned conductive layer and the planarized insulator; (6) removing the above patterned photoresist mask; (7) on the above second conductive layer and in node contact opening uniformly depositing third conductive layer; (8) performing totally anisotropical etch back to the above third conductive layer, so that in the above opening there forms side wall spacer made of third conductive layer, and the above etch back makes insulator surface in the above opening expose; (9) with the above second conductive layer and side wall spacer as etching mask selectively performing anisotropical etching to insulator in the above opening until the semiconductor substrate surface, therefore forming the above node contact opening in the above planarized insulator; (10) on the above second conductive layer and in small node contact opening depositing fourth conductive layer, therefore forming electric contact to the above semiconductor active area; (11) patterning the fourth and second conductive layer, finishing the above electric node contact and electrically connected conductive layer above it.