TW224530B - New memory examiner - Google Patents

Abstract

A new memory examiner comprises one parity-bit inspector, one or several bit storages and one parity-bit generator, in which - the parity-bit inspector receives the parity-bit input signal generated y the parity-bit generator and the written data bus of computer system, nd, according to an inspection protocol, if the two data are not matched o a relation set by the protocol, a bit value representing no match is enerated by controlling R/W control signals and sent to the bit storage; - the bit storage receives the bit value generated by the parity-bit inspector nd R/W control signals from system to control the writting of the bit value rom the parity-bit inspector to the bit storage or the reading of the bit alue from the bit storage to the parity-bit generator and resetting the it-storage; - the parity-bit generator receives the R/W control signals from the system, y reading the bit value from the bit storage and the data bus from memory odule and according to the relation set by the inspection protocol, to enerate and send a bit value to the system parity-bit inspector, and ommand the system parity-bit inspector to inspect, according to the elation set by the inspection protocol, the error status of the data read rom the momory module and generate an interrupt signal to the system.