TW202404096A - 半導體元件 - Google Patents

半導體元件 Download PDF

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Publication number
TW202404096A
TW202404096A TW112120208A TW112120208A TW202404096A TW 202404096 A TW202404096 A TW 202404096A TW 112120208 A TW112120208 A TW 112120208A TW 112120208 A TW112120208 A TW 112120208A TW 202404096 A TW202404096 A TW 202404096A
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Taiwan
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layer
gate electrode
channel layer
gate
source
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TW112120208A
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English (en)
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宋昇珉
姜明一
金孝眞
崔道永
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南韓商三星電子股份有限公司
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Publication of TW202404096A publication Critical patent/TW202404096A/zh

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Abstract

一種半導體元件包括：位於基板上的主動區；位於主動區上且彼此間隔開的通道層，包括下部通道層及上部通道層；位於最上部的下部通道層與最下部的上部通道層之間的中間絕緣層；與主動區相交的閘極，包括環繞下部通道層的下部閘極電極與環繞上部通道層的上部閘極電極；位於中間絕緣層一側上的上部閘極電極與下部閘極電極之間的絕緣圖案；位於閘極的至少一側上的源極/汲極區，包括連接至下部通道層的下部源極/汲極區與連接至上部通道層的上部源極/汲極區；以及接觸插塞，包括連接至下部源極/汲極區的水平延伸部分與連接至水平延伸部分的垂直延伸部分。

Description

半導體元件
[相關申請案的交叉參考]
本申請案主張2022年7月6日於韓國智慧財產局提出申請的韓國專利申請案第10-2022-0083050號的優先權權益，所述韓國專利申請案的揭露內容全部併入本案供參考。
本申請案是有關於一種半導體元件。
隨著對高效能、高速及/或多功能半導體元件的需求增大，半導體元件的積體程度不斷提高。為了克服由於平坦金屬氧化物半導體場效電晶體（field effect transistor，FET）的大小減小所致的對操作特性的限制，正在努力地開發包括具有鰭形通道的鰭FET（FinFET）、具有由閘極環繞的奈米片的環繞式閘極場效電晶體（gate-all-around field effect transistor，GAAFET）等在內的半導體元件。
根據實施例的態樣，一種半導體元件包括：主動區，在基板上在第一水平方向上延伸；多個通道層，堆疊於所述主動區上、彼此間隔開，所述多個通道層包括下部通道層及位於所述下部通道層上的上部通道層；中間絕緣層，位於所述下部通道層中最上部的下部通道層與所述上部通道層中最下部的上部通道層之間；閘極結構，與所述基板上的所述主動區及所述多個通道層相交，在第二水平方向上延伸，且包括環繞所述多個通道層的閘極電極，所述閘極電極包括環繞所述下部通道層的下部閘極電極及環繞所述上部通道層的上部閘極電極；絕緣圖案，在所述中間絕緣層的在所述第二水平方向上的第一側上位於所述上部閘極電極與所述下部閘極電極；源極/汲極區，位於所述閘極結構的至少一側上，且包括連接至所述下部通道層的下部源極/汲極區與連接至位於所述下部源極/汲極區上的所述上部通道層的上部源極/汲極區；以及接觸插塞，包括連接至所述下部源極/汲極區中的每一者且在與所述基板平行的水平方向上延伸的水平延伸部分以及連接至所述水平延伸部分且在與所述基板的上表面垂直的垂直方向上延伸的垂直延伸部分。
根據實施例的態樣，一種半導體元件包括：主動區，在基板上在第一水平方向上彼此平行地延伸；多個電晶體結構，在所述基板上在第二水平方向上彼此間隔開；以及閘極隔離圖案，將所述多個電晶體結構實體地分隔開，其中所述多個電晶體結構中的第一電晶體結構包括彼此間隔開且堆疊於所述主動區中的第一主動區上的第一通道層，所述第一通道層包括下部通道層及位於所述下部通道層上的上部通道層；第一中間絕緣層，位於所述下部通道層中最上部的下部通道層與所述上部通道層中最下部的上部通道層之間；第一閘極結構，與所述基板上的所述第一主動區及所述第一通道層相交，在所述第二水平方向上延伸，且包括環繞所述第一通道層的第一閘極電極；第一絕緣圖案，位於所述第一中間絕緣層在所述第二水平方向上的所述第一側與所述閘極隔離圖案之間；以及第一源極/汲極區，位於所述第一閘極結構的至少一側上，且包括連接至所述下部通道層的下部源極/汲極區與連接至位於所述下部源極/汲極區上的所述上部通道層的上部源極/汲極區。
根據實施例的態樣，一種半導體元件包括：主動區，在基板上在第一水平方向上延伸；多個通道層，堆疊於所述主動區上以彼此間隔開，所述多個通道層包括下部通道層及位於所述下部通道層上的上部通道層；閘極結構，與所述基板上的所述主動區及所述多個通道層相交，在第二水平方向上延伸，且包括環繞所述多個通道層的閘極電極，所述閘極電極包括環繞所述下部通道層的下部閘極電極及環繞所述上部通道層的上部閘極電極；絕緣圖案，位於所述上部閘極電極與所述下部閘極電極之間；源極/汲極區，位於所述閘極結構的至少一側上，且包括連接至所述下部通道層的下部源極/汲極區與連接至位於所述下部源極/汲極區上的所述上部通道層的位於上部源極/汲極區；以及接觸插塞，包括連接至水平延伸部分且在與所述基板的上表面垂直的垂直方向上延伸的垂直延伸部分及連接至所述下部源極/汲極區中的每一者且在與所述基板平行的水平方向上延伸的水平延伸部分，其中所述下部閘極電極具有接觸所述上部閘極電極的一部分，所述絕緣圖案在所述垂直方向上不與所述多個通道層交疊，且所述絕緣圖案的至少一部分處於等於所述水平延伸部分的至少一部分的水平高度的水平高度處。
圖1是說明根據實例性實施例的半導體元件的平面圖。圖2A、圖2B及圖2C是說明分別沿著圖1的線I-I’、II-II’及III-III’以及IV-IV’的橫截面的剖視圖。
參考圖1至圖2C，半導體元件100可包括：基板101；主動區105，位於基板101上；多個電晶體結構TRS，位於基板101上；及閘極隔離圖案GC，將所述多個電晶體結構TRS彼此分隔開。
所述多個電晶體結構TRS中的每一者可包括下部電晶體TRa及設置於下部電晶體TRa上的上部電晶體TRb。上部電晶體TRa及下部電晶體TRb可在Z方向上垂直地堆疊，且可提供互補FET（complementary FET，CFET）。上部電晶體TRa及下部電晶體TRb可提供P型金屬氧化物半導體FET（p-type metal oxide semiconductor FET，PMOSFET）上N型金屬氧化物半導體FET（n-type MOSFET，NMOSFET）或NMOSFET上PMOSFET。在另一實例中，半導體元件100可堆疊電晶體結構TRS以提供層疊式CMOSFET（CMOSFET-on-CMOSFET）。
在實例性實施例中，所述多個電晶體結構TRS可包括第一電晶體結構TRS1、第二電晶體結構TRS2及第三電晶體結構TRS3。在本說明書中，第二電晶體結構TRS2及第三電晶體結構TRS3可具有與第一電晶體結構TRS1相同或類似的特性，除非另有規定；且第一電晶體結構TRS1亦可被稱為「電晶體結構」。
電晶體結構TRS1可包括：多個通道層140，在Z方向上堆疊於主動區105上且彼此間隔開；閘極結構160，與主動區105及所述多個通道層140相交且在Y方向上延伸；及源極/汲極區150，在閘極結構160的兩側上連接至所述多個通道層140。閘極結構160可包括閘極介電層162、閘極電極165及閘極間隔件164。
電晶體結構TRS1的下部電晶體TRa可包括：下部通道層140a；下部閘極電極165a，環繞下部通道層140a；下部源極/汲極區150a，在下部閘極電極165a的兩側上連接至層140a；及下部閘極介電層162a，位於下部通道層140a與下部閘極電極165a之間。
電晶體結構TRS1的上部電晶體TRb可包括：上部通道層140b；上部閘極電極165b，環繞上部通道層140b；上部源極/汲極區150b，在上部閘極電極165b的兩側上連接至層140b；及上部閘極介電層162b，位於上部通道層140b與上部閘極電極165b之間。
在實例性實施例中，電晶體結構TRS1可更包括：中間絕緣層130，位於上部電晶體TRa及下部電晶體TRb之間；及絕緣圖案135，設置於中間絕緣層130的一側上。電晶體結構TRS1可具有其中上部閘極電極165a與下部閘極電極165b在未設置中間絕緣層130及絕緣圖案135的區中連接的共同閘極電極結構。
半導體元件100可更包括元件隔離層107、接觸插塞171、172及173、上部互連線191、下部互連線196及層間絕緣層181、182、183、184、185及186。
在半導體元件100中，主動區105可具有鰭結構，且閘極電極165可被設置成環繞所述多個通道層140。因此，半導體元件100可提供多橋通道FET（multi-bridge-channel FET，MBCFET™）。
基板101可包含半導體材料，例如第IV族半導體、第III-V族化合物半導體或第II-VI族化合物半導體。舉例而言，第IV族半導體可包括矽（Si）、鍺（Ge）或矽鍺（SiGe）。基板101可被設置為例如體晶圓、磊晶層、絕緣體上矽（silicon-on-insulator，SOI）層、絕緣體上半導體（semiconductor-on-insulator，SeOI）層等。
主動區105可在基板101上由元件隔離層107界定，且可被設置成在第一水平方向（例如X方向）上在長度方向上延伸。主動區105可具有自基板101突出的結構。主動區105的上端可被設置成自元件隔離層107的上表面突出預定的高度，例如在元件隔離層107的上表面上方突出。主動區105可被形成為基板101的一部分，或可包括自基板101生長的磊晶層。然而，在閘極結構160的兩側上，基板101上的主動區105可部分地凹陷，且下部源極/汲極區150a可設置於凹陷的主動區105上。根據實施例，主動區105可包含雜質。
多個主動區105可被設置成在第二方向（例如，Y方向）上彼此間隔開。在實例性實施例中，主動區105可包括在Y方向上依序排列的第一主動區105a、第二主動區105b、第三主動區105c及第四主動區105d。
元件隔離層107可在基板101上界定主動區105。可藉由例如淺溝槽隔離（shallow trench isolation，STI）製程形成元件隔離層107。元件隔離層107可暴露出主動區105的上部側表面。元件隔離層107可在X方向上在長度方向上延伸，且可覆蓋在主動區105的暴露的上部側表面下方的側表面。根據實施例，元件隔離層107可包括在主動區105之間更深地延伸於基板101下方的區。隨著元件隔離層107靠近主動區105，元件隔離層107可具有水平高度較高的彎曲上表面，但元件隔離層107的上表面的形狀並不僅限於此。元件隔離層107可由絕緣材料形成。元件隔離層107可由例如氧化矽、氮化矽、氮氧化矽或其組合形成。
所述多個通道層140可於在與基板101的上表面垂直的方向上（例如，在Z方向上）彼此間隔開的同時堆疊於主動區105上，且可包括下部通道層140a及位於下部通道層140a上的上部通道層140b。
下部通道層140a可連接至下部源極/汲極區150a。下部通道層140a可包括在主動區105上在Z方向上彼此間隔開的多個半導體層。在圖2A及圖2C中，說明所述多個半導體層的數目是兩個，但半導體層的數目並不僅限於此，且可具有各種改變。所述多個半導體層可由半導體材料（例如，矽（Si）、矽鍺（SiGe）或鍺（Ge）中的至少一種）形成。
上部通道層140b可連接至上部源極/汲極區150b。上部通道層140b可設置於下部通道層140a上，且可與下部通道層140a在垂直方向上交疊。上部通道層140b可包括在Z方向上彼此間隔開的多個半導體層。在圖2A及圖2C中，說明所述多個半導體層的數目是兩個，但半導體層的數目並不僅限於此且可具有各種改變。構成上部通道層140b的所述多個半導體層可由半導體材料（例如，矽（Si）、矽鍺（SiGe）或鍺（Ge）中的至少一種）形成。
在實例性實施例中，上部通道層140a或下部通道層140b中的至少一者可包括包含雜質的半導體層。
閘極結構160可在主動區105及元件隔離層107上在Z方向上延伸。閘極結構160可包括：閘極電極165，例如在長度方向上在第二水平方向（例如，Y方向）上延伸，同時環繞所述多個通道層140；閘極介電層162，位於閘極電極165與所述多個通道層140之間；及閘極間隔件164，設置於閘極電極165的相對側（例如兩側）上。舉例而言，閘極結構160可更包括閘極頂蓋層，所述閘極頂蓋層設置於閘極電極165的上表面及閘極間隔件164的上表面上。
閘極電極165可包括下部電晶體TRa的下部閘極電極165a及上部電晶體TRb的上部閘極電極165b。
下部閘極電極165a可與主動區105及主動區105上的下部通道層140a相交，且可例如在長度方向上在第二方向（例如，Y方向）上延伸。下部電晶體TRa的通道區可形成於與下部閘極電極165a相交的主動區105及下部通道層140a中。下部閘極電極165a可環繞下部通道層140a，且下部閘極介電層162a可設置於下部閘極電極165a與下部通道層140a之間。
上部閘極電極165b可與下部通道層140a上的上部通道層140b相交，且可例如在長度方向上在Y方向上延伸。上部電晶體的通道區可形成於與上部閘極電極165b相交的上部通道層140b中。上部閘極電極165b可環繞上部通道層140b，且上部閘極介電層162b可設置於上部閘極電極165b與上部通道層140b之間。
閘極電極165可包含導電材料，例如W、Ti、Ta、Mo、TiN、TaN、WN、TiON、TiAlC、TiAlN或TaAlC中的至少一種。根據實施例，閘極電極165可包含半導體材料，例如經過摻雜的複晶矽。
舉例而言，上部閘極電極165a與下部閘極電極165b可包含不同的材料。上部閘極電極165a與下部閘極電極165b中的至少一者可由兩層或更多層形成。在實例性實施例中，上部閘極電極165b可包括環繞上部通道層140b的第一上部閘極電極165b_1及位於第一上部閘極電極165b_1上的第二上部閘極電極165b_2。第一上部閘極電極165b_1與第二上部閘極電極165b_2可包含不同的材料，或即使當其包含相同的材料時，根據製程條件邊界可能是明顯的。
在實例性實施例中，第一上部閘極電極165b_1可包括：第一部分P1，覆蓋絕緣圖案135的上表面及下部閘極電極165a的上表面；及第二部分P2，覆蓋上部通道層140b。舉例而言，如圖2A中所說明，第一部分P1可以是水平的，例如在第二方向上在長度方向上且平行於基板101的上表面延伸；且第二部分P2可在垂直方向上自第一部分P1延伸且包括環繞上部通道層140b的垂直部分及水平部分兩者。例如相對於基板101的上表面而言，第一部分P1的上表面可位於較第二部分P2的上表面的水平高度低的水平高度處。第二上部閘極電極165b_2可在第二部分P2與閘極隔離圖案GC之間延伸成接觸第一部分P1。舉例而言，如圖2A中所說明，第二上部閘極電極165b_2可例如連續地延伸且直接接觸第二部分P2的上表面及側表面、閘極隔離圖案GC的側表面及第一部分P1的上表面。
閘極介電層162可包括下部電晶體TRa的下部閘極介電層162a及上部電晶體TRb的上部閘極介電層162b。閘極介電層162可包含例如氧化物、氮化物及/或高介電常數（high-κ）材料。所述高介電常數材料可指代介電常數高於氧化矽層（SiO 2）的介電常數的介電材料。所述高介電常數材料可以是例如以下各項中的至少一種：氧化鋁（Al 2O 3）、氧化鉭（Ta 2O 3）、氧化鈦（TiO 2）、氧化釔（Y 2O 3）、氧化鋯（ZrO 2）、氧化鋯矽（ZrSi xO y）、氧化鉿（HfO 2）、氧化鉿矽（HfSi xO y）、氧化鑭（La 2O 3）、氧化鑭鋁（LaAl xO y）、氧化鑭鉿（LaHfxOyLaHf xO y）、氧化鉿鋁（HfAl xO y）及氧化鐠（Pr 2O 3）。舉例而言，上部閘極介電層162a及下部閘極介電層162b可包含不同的材料，但並不僅限於此。
閘極間隔件164可設置於閘極結構160的兩個側表面上。在實例性實施例中，閘極間隔件164可包括具有彎曲外表面的部分，使得閘極間隔件164中的每一者的上部部分的寬度窄於下部部分的寬度。根據實例性實施例，閘極間隔件164可具有多層結構。閘極間隔件164可包含例如氧化矽、氮化矽及氮氧化矽中的至少一種。
源極/汲極區150可包括下部電晶體TRa的下部源極/汲極區150a及上部電晶體TRb的上部源極/汲極區150b。
下部源極/汲極區150a可在下部通道層140a的兩側上設置於主動區105的凹陷區上。下部源極/汲極區150a可用作下部電晶體TRa的源極區或汲極區。可藉由使主動區105的上部部分部分地凹陷來設置下部源極/汲極區150a，但在實施例中，凹部存在還是不存在以及凹部的深度可具有各種改變。
上部源極/汲極區150b可設置於上部通道層140b的兩側上。上部源極/汲極區150b可用作上部電晶體TRb的源極區或汲極區。上部源極/汲極區150b可與下部源極/汲極區150a間隔開。舉例而言，如圖2B中所說明，上部源極/汲極區150b可藉由第一層間絕緣層181及/或第二層間絕緣層182與下部源極/汲極區150a分隔開。在另一實例中，上部源極/汲極區150b可藉由單獨的絕緣結構與下部源極/汲極區150a分隔開。
源極/汲極區150a及150b可包括包含矽（Si）的半導體層，且可包括多個磊晶層。源極/汲極區150a及150b可包含不同類型及/或濃度的雜質。舉例而言，當下部電晶體TRa是PMOSFET時，下部源極/汲極區150a可包含經過p型摻雜的矽鍺（SiGe），且當上部電晶體TRb是NMOSFET時，上部源極/汲極區150b可包含經過n型摻雜的矽（Si）。
中間絕緣層130可設置於下部通道層140a中最上部的下部通道層140a與上部通道層140b中最下部的上部通道層140b之間。中間絕緣層130可設置於主動區105上，例如中間絕緣層130可在垂直方向上與主動區105的上表面交疊。在實例性實施例中，整個中間絕緣層130可在垂直方向上與閘極結構160交疊，但根據實施例可包括不與閘極結構160在垂直方向上交疊的部分。
在實例性實施例中，中間絕緣層130的至少一部分可被閘極介電層162覆蓋。中間絕緣層130可例如藉由閘極介電層162與上部閘極電極165a及下部閘極電極165b間隔開。
中間絕緣層130可包含絕緣材料，例如氮化矽、氮氧化矽及碳氮化矽中的至少一種。中間絕緣層130可以是單絕緣材料層或多材料層。
絕緣圖案135可在上部閘極電極165b與下部閘極電極165a之間設置於中間絕緣層130的一側上。舉例而言，絕緣圖案135可位於上部閘極電極165b的第一部分P1與下部閘極電極165a之間，例如，絕緣圖案135與第一部分P1可彼此完全交疊且接觸（例如，鄰接）中間絕緣層130的側面。絕緣圖案135可設置於中間絕緣層130的一側與閘極隔離圖案GC之間。舉例而言，絕緣圖案135可接觸閘極隔離圖案GC。絕緣圖案135可不與所述多個通道層140在Z方向上交疊。
絕緣圖案135的上表面可接觸（例如直接接觸）上部閘極電極165b，且絕緣圖案135的下表面可接觸（例如直接接觸）下部閘極電極165a。上部閘極電極165b與下部閘極電極165a可在不與絕緣圖案135及中間絕緣層130在垂直方向上交疊的區中彼此接觸。
絕緣圖案135可設置於中間絕緣層130的一側上以與中間絕緣層130間隔開。絕緣圖案135可藉由閘極介電層162與中間絕緣層130間隔開。
在實例性實施例中，例如相對於基板101的上表面而言，絕緣圖案135的下表面可設置於與中間絕緣層130的下表面實質上相同的水平高度上（例如與中間絕緣層130的下表面共面），或可設置於較中間絕緣層130的下表面高的位置處。
絕緣圖案135可包含絕緣材料，例如氧化矽及氮化矽中的至少一者。舉例而言，絕緣圖案135可包含與中間絕緣層130的材料不同的材料。
在實例性實施例中，中間絕緣層130的第一厚度t1可厚於絕緣圖案135的第二厚度t2。第一厚度t1可處於例如約30奈米至約80奈米的範圍內。
中間絕緣層130可包括在第二水平方向（例如，Y方向）上的第一側130S1及與所述第一側S1相對的第二側130S2。舉例而言，如圖2A中所說明，絕緣圖案135可僅位於第一側130S1及第二側130S2中的一者上。
在實例性實施例中，絕緣圖案135可設置於或可不設置於所述多個電晶體結構TRS1、TRS2及TRS3內的不同位置中。
舉例而言，在第一電晶體結構TRS1中，絕緣圖案135可設置於中間絕緣層130的第一側130S1上。在此種情形中，上部閘極電極165b與下部閘極電極165a可在鄰近中間絕緣層130的第二側130S2的區中直接接觸。
舉例而言，在第二電晶體結構TRS2中，絕緣圖案135可設置於中間絕緣層130的第二側130S2上。在此種情形中，上部閘極電極165b與下部閘極電極165a可在鄰近中間絕緣層130的第一側130S1的區中直接接觸。
舉例而言，在第三電晶體結構TRS3中，可不設置絕緣圖案135。在此種情形中，上部閘極電極165b與下部閘極電極165a可在鄰近中間絕緣層130的第一側S1及第二側S2兩者的區中直接接觸。並且，閘極電極165可完全環繞中間絕緣層130。
在圖1至圖2C中，儘管多個電晶體結構TRS被說明為在Y方向上按照第一電晶體結構TRS1、第二電晶體結構TRS2、第一電晶體結構TRS1及第三電晶體結構TRS3的次序排列，但第一電晶體結構TRS1、第二電晶體結構TRS2及第三電晶體結構TRS3的排列次序可根據實施例而具有各種改變。並且，根據實施例，所述多個電晶體結構TRS可包括第一電晶體TRS1或第二電晶體TRS2中的至少一者，且可不包括第三電晶體結構TRS3。
接觸插塞171、172及173可包括電性連接至下部源極/汲極區150a的第一接觸插塞171、電性連接至上部源極/汲極區150b的第二接觸插塞172及電性連接至閘極結構160的第三接觸插塞173。第一接觸插塞171及第二接觸插塞172可電性連接至下部互連線196，且第三接觸插塞173可電性連接至上部互連線191。
第一接觸插塞171可包括在Z方向上延伸的垂直延伸部分171V及在與Z方向垂直的水平方向上延伸的水平延伸部分171H。舉例而言，如圖2B中所說明，垂直延伸部分171V及水平延伸部分171H可排列成T形，其中垂直延伸部分171V在下部源極/汲極區150a與接觸下部源極/汲極區150a的頂部的水平延伸部分171H之間延伸。
詳細而言，垂直延伸部分171V可電性連接至下部互連線196，且可在鄰近主動區105之間延伸穿過基板101。垂直延伸部分171V可具有恆定的寬度，如圖2B中所說明；但可具有寬度在自基板101的下表面朝向基板101的上表面的方向上減小的傾斜側表面。另外，根據實施例，垂直延伸部分171V可具有寬度在自基板101的下表面朝向基板101的上表面的方向上減小的傾斜側表面。
在實例性實施例中，水平延伸部分171H可自垂直延伸部分171V的上部部分朝向下部源極/汲極區150a延伸。垂直延伸部分171V可接觸下部源極/汲極區150a的上端。
絕緣圖案135的至少一部分可設置於與水平延伸部分171H的至少一部分相同的水平高度上（圖2C）。舉例而言，絕緣圖案135可具有在第一水平方向（例如，X方向）上與水平延伸部分171H交疊的一部分，例如，絕緣圖案135的側面與水平延伸部分171H可面向彼此且彼此交疊。絕緣圖案135可防止或最小化水平延伸部分171H與閘極結構160之間的寄生電容的出現，以改良半導體元件100的電性特性及可靠性。絕緣圖案135可與中間絕緣層130一起抑制寄生電容。由於絕緣圖案135僅設置於中間絕緣層130的一側上，因此可提供具有其中在將寄生電容最小化的同時使上部閘極電極165b與下部閘極電極165a連接的共同閘極電極結構的半導體元件。
水平延伸部分171H的第三厚度t3可薄於中間絕緣層130的第一厚度。舉例而言，第三厚度t3可與絕緣圖案135的第二厚度t2實質上相同。例如相對於基板101的上表面而言，水平延伸部分171H的上表面可位於較中間絕緣層130的上表面的水平高度低的水平高度處。
在圖1至圖2C中，第一接觸插塞171被說明為用於同時連接鄰近主動區105上的下部源極/汲極區150a的共同接觸插塞，但可以是連接至一個下部源極/汲極區150a的單接觸插塞。
第二接觸插塞172可包括在Z方向上延伸的垂直延伸部分172V及在與Z方向垂直的水平方向上延伸的水平延伸部分172H。水平延伸部分172H可接觸上部源極/汲極區150b的上端。舉例而言，如圖2B中所說明，垂直延伸部分172V及水平延伸部分172H可排列成倒置的L形。
第三接觸插塞173可連接至上部閘極電極165b。下部閘極電極165a及上部閘極電極165b可彼此電性連接，且可經由第三接觸插塞173施加相同的電性訊號。
第一接觸插塞171、第二接觸插塞172及第三接觸插塞173可包含例如氮化鈦（TiN）、氮化鉭（TaN）、氮化鎢（WN）、氮化鎢碳（WCN）、鈦（Ti）、鉭（Ta）、鎢（W）、銅（Cu）、鋁（Al）、鈷（Co）、釕（Ru）或鉬（Mo）中的至少一種。
閘極隔離圖案GC可將所述多個電晶體結構TRS在第二水平方向（例如，Y方向）上實體地分隔開。閘極隔離圖案GC可設置於鄰近的電晶體結構TRS之間。閘極隔離圖案GC可被設置成在Y方向上彼此間隔開。閘極隔離圖案GC可例如在長度方向上在Z方向上延伸成接觸元件隔離層107。閘極隔離圖案GC可包含絕緣材料，例如氮化物系材料。
上部互連線191可設置於閘極結構160上，且下部互連線196可設置於基板101下方。上部互連線191及下部互連線196中的每一者被說明為單層，但根據實施例可具有具有多種水平高度的多層結構。第一接觸插塞171及第二接觸插塞172被說明為連接至下部互連線191，且第三接觸插塞173被說明為連接至上部互連線191，但根據實施例接觸插塞171、172及173與上部互連線191及下部互連線196之間的連接關係可具有各種改變。
層間絕緣層181、182、183、184、185及186可包含絕緣材料，例如氧化矽。層間絕緣層181、182、183、184、185及186可包括：第一層間絕緣層181，覆蓋基板101上的下部電晶體TRa；第二層間絕緣層182，在第一層間絕緣層181上覆蓋上部電晶體TRb；第一上部層間絕緣層183及第二上部層間絕緣層184，位於第二層間絕緣層182上；以及第一下部層間絕緣層185及第二下部層間絕緣層186，位於基板101下方。根據實施例，第一層間絕緣層181與第二層間絕緣層182之間的邊界可不明顯。
圖3A及圖3B是說明根據實例性實施例的半導體元件的剖視圖。圖3A說明與圖1的半導體元件的沿著線I-I’截取的橫截面對應的區，且圖3B說明與圖1的半導體元件的沿著線III-III’及IV-IV’截取的橫截面對應的區。
參考圖3A及圖3B，在半導體元件100a中，絕緣圖案135的第二厚度t2’可相對厚於圖2A至圖2C的半導體元件的厚度。在實例性實施例中，絕緣圖案135的第二厚度t2’可與中間絕緣層130的第一厚度t1實質上相同。由於絕緣圖案135是藉由與中間絕緣層130分離的製程形成，因此可將絕緣圖案135調整成具有各種厚度。舉例而言，絕緣圖案135可具有在不會使上部通道層140b與上部閘極電極165b之間的電性特性劣化的情況下能夠防止與第一接觸插塞171的寄生電容的最佳厚度。
圖4A及圖4B是說明根據實例性實施例的半導體元件的剖視圖。圖4A說明與圖1的半導體元件的沿著線I-I’截取的橫截面對應的區，且圖4B說明與圖1的半導體元件的沿著線III-III’及IV-IV’截取的橫截面對應的區。
參考圖4A及圖4B，在半導體元件100b中，下部閘極電極165a的最上表面可位於較中間絕緣層130的下表面的水平高度高的水平高度處。下部閘極電極165a可覆蓋中間絕緣層130的下表面、及中間絕緣層130的側表面的一部分。下部閘極電極165a的上表面的高度可根據製程條件而具有各種改變。
絕緣圖案135可設置於下部閘極電極165a的最上表面上。因此，絕緣圖案135的下表面可位於較中間絕緣層130的下表面的水平高度高的水平高度處。在實例性實施例中，絕緣圖案135的上表面可與中間絕緣層130的上表面實質上相同，或位於較中間絕緣層130的上表面的水平高度低的水平高度處。
圖5是說明根據實例性實施例的半導體元件的剖視圖。圖5說明與圖1的半導體元件的沿著線I-I’截取的橫截面對應的區。
參考圖5，在半導體元件100c中，上部閘極電極165b’可具有與圖2A至圖2C的上部閘極電極165b的結構不同的結構。
上部閘極電極165b’可包括第一上部閘極電極165b_1’及位於第一上部閘極電極165b_1’上的第二上部閘極電極165b_2’。第一上部閘極電極165b_1’可包括：第一部分P1’，覆蓋絕緣圖案135的上表面及下部閘極電極165a的上表面；及第二部分P2，覆蓋上部通道層140b。與圖2A至圖2C不同，第一部分P1’的最上表面可位於較第二部分P2的上表面的水平高度高的水平高度處。第一部分P1’可包括在第二部分P2與閘極隔離圖案GC之間沿著閘極隔離圖案GC的側表面延伸的區段。
圖6是說明根據實例性實施例的半導體元件的剖視圖。圖6說明與圖1的半導體元件的沿著線II-II’截取的橫截面對應的區。
參考圖6，半導體元件100d可包括與圖2A至圖2C的半導體元件100的接觸插塞不同的接觸插塞171’及172’。
第一接觸插塞171’可包括垂直延伸部分171V’及水平延伸部分171H，且垂直延伸部分171V’可連接至上部互連線191。舉例而言，垂直延伸部分171V’可穿過第一層間絕緣層181及第二層間絕緣層182以接觸水平延伸部分171H，且水平延伸部分171H可自垂直延伸部分171V’的下部部分朝向下部源極/汲極區150a延伸。
與第一接觸插塞171’類似，第二接觸插塞172’可連接至上部互連線191。
圖7A至圖7F是說明根據實例性實施例的製造半導體元件的方法的各個階段的視圖。圖7A至圖7F是說明與圖2A對應的區的視圖。
參考圖7A，可在基板101上形成主動區105、元件隔離層107及所述多個通道層140a及140b，可形成源極/汲極區150，可形成下部閘極電極165a，且可形成絕緣材料層135’。
可在基板101上交替地堆疊所述多個通道層140a及140b以及犧牲層，且可移除所述多個通道層140a及140b的一部分、所述犧牲層的一部分及基板101的一部分以界定主動區105。在此操作中，可在下部通道層140a與上部通道層140b之間形成中間絕緣層130，且可將中間絕緣層130的一部分與所述多個通道層140a及140b的一部分以及犧牲層的一部分一起移除。可藉由後續的製程移除犧牲層以提供使用閘極介電層162a及162b以及閘極電極165a及165b來填充的空間。
所述多個通道層140a及140b與犧牲層可包含不同的半導體材料。舉例而言，所述多個通道層140a及140b可包含矽（Si），且犧牲層可包含矽鍺（SiGe）。可藉由移除基板101的所述部分來將主動區105界定為基板101的突出鰭部分，且主動區105可被形成為具有在一個方向（例如，X方向）上延伸的線性形狀。可藉由填充絕緣材料且然後使主動區105凹陷成突出來在從中移除了基板101的所述部分的區中形成元件隔離層107。在X方向上延伸的主動區105、所述多個通道層140a及140b以及犧牲層可形成半導體結構。
可在基板101上形成與半導體結構相交且在一個方向（例如，Y方向）上延伸的犧牲閘極結構，且可在所述犧牲閘極結構的兩側上形成閘極間隔件164（參考圖1）。
可使用犧牲閘極結構及閘極間隔件164作為遮罩來蝕刻半導體結構的暴露部分，以形成上表面暴露於主動區105的凹部區。根據實施例，在此操作中，可自側表面另外移除犧牲層的一部分以形成內間隔件。可在具有凹部區的主動區105的上表面上形成下部源極/汲極區150a（參考圖1及圖2C）。下部源極/汲極區150a可包括藉由執行磊晶生長製程自主動區105及下部通道層140a生長的磊晶層。下部源極/汲極區150a可因原位摻雜而包含雜質，且可包括具有不同的摻雜元素及/或摻雜濃度的多個層。
可形成覆蓋下部源極/汲極區150a的第一層間絕緣層181（參考圖2C），且可形成接觸插塞171、172及173（參考圖2C）的水平延伸部分171H及172H。此外，可形成第二層間絕緣層182（參考圖2C）的一部分。可執行磊晶生長製程以形成上部源極/汲極區150b，所述上部源極/汲極區150b可以是自上部通道層140b生長的磊晶層。上部源極/汲極區150b可與下部源極/汲極區150a在垂直方向上交疊。上部源極/汲極區150b可因原位摻雜而包含雜質，且可包括具有不同的摻雜元素及/或摻雜濃度的多個層。摻雜於上部源極/汲極區150b中的雜質的導電性類型可不同於摻雜於下部源極/汲極區150a中的雜質的導電性類型。
可藉由移除犧牲閘極結構以暴露出犧牲層的側表面並執行剝離製程以相對於所述多個通道層140a及140b選擇性地移除所述犧牲層來形成開口。可藉由在所述開口中沈積介電材料來形成閘極介電層162a及162b。在此操作中，可對與下部通道層140a交替地堆疊的下部犧牲層單獨地執行剝離製程且對與上部通道層140b交替地堆疊的上部犧牲層單獨地執行剝離製程，或可對上部犧牲層及下部犧牲層的開口單獨地執行介電材料沈積製程，以形成具有不同的材料或不同的厚度的上部閘極介電層162b及下部閘極介電層162a。
可藉由在開口中及在從中移除了犧牲閘極結構的區中填充導電材料且移除所述導電材料的一部分來形成下部閘極電極165a。所述導電材料可包括例如W、Ti、Ta、Mo、TiN、TaN、WN、TiON、TiAlC、TiAlN及TaAlC中的至少一種。儘管下部閘極電極165a的上表面的水平高度被說明為等於中間絕緣層130的下表面的水平高度，但可根據製程條件對下部閘極電極165a的上表面的水平高度進行各種調整。在此操作中，導電材料可保留於上部通道層140b之間以形成虛設導電材料層165ad。
可在下部閘極電極165a上形成覆蓋下部閘極電極165a及上部通道層140b的絕緣材料層135’。絕緣材料層135’可包含例如氧化矽或氮化矽。
參考圖7B，可部分地移除絕緣材料層135’以暴露出虛設導電材料層165ad。
可相對於上部通道層140b及上部閘極介電層162b選擇性地蝕刻絕緣材料層135’，使得絕緣材料層135’的上表面的水平高度被形成為與中間絕緣層130的上表面的水平高度相同或低於中間絕緣層130的上表面的水平高度。因此，可將絕緣材料層135’的厚度調整成薄於中間絕緣層130的厚度。
絕緣材料層135’的其餘部分可設置於與水平延伸部分171H平行的水平高度處。絕緣材料層135’的至少一部分可與水平延伸部分171H在X方向上交疊。因此，可將水平延伸部分171H與上部閘極電極165b及下部閘極電極165a之間的導電材料的寄生電容的出現最小化。
參考圖7C，可移除虛設導電材料層165ad以形成犧牲金屬層120。
可相對於上部通道層140b及上部閘極介電層162b選擇性地移除虛設導電材料層165ad，且可在從中移除了虛設導電材料層165ad的區中填充導電材料以形成犧牲金屬層120。可藉由使用導電材料來填充從中移除了犧牲閘極結構的區（包括從中移除了虛設導電材料層165a的區）且執行回蝕製程來形成犧牲金屬層120。所述導電材料可包括例如W、Ti、Ta、Mo、TiN、TaN、WN、TiON、TiAlC、TiAlN及TaAlC中的至少一種。所述導電材料可包括與下部閘極電極165a或虛設導電材料層165ad的材料不同的材料。因此，犧牲金屬層120可在特定蝕刻條件下相對於下部閘極電極165a而具有蝕刻選擇性比率。
根據實施例，可省略形成犧牲金屬層120的操作。
參考圖7D，可使用遮罩HM形成絕緣圖案135。可使用遮罩HM藉由圖案化製程移除絕緣材料層135’的一部分以形成絕緣圖案135。
中間絕緣層130可包括在第二水平方向（例如，Y方向）上的第一側130S1及與所述第一側130S1相對的第二側130S2。可藉由調整遮罩HM的開口的位置來移除設置於中間絕緣層130的第一側130S1或第二側130S2中的至少一者上的絕緣材料層135’。因此，絕緣圖案135可設置於中間絕緣層130的第一側130S1上或中間絕緣層130的第二側130S2上。
從中移除了中間絕緣層130的區中可暴露出下部閘極電極165a。因此，藉由後續的製程形成的上部閘極電極165b與下部閘極電極165a可彼此連接以形成共同閘極電極結構。
可藉由圖案化製程所形成的絕緣圖案135提供具有共同閘極電極結構且被控制成將接觸插塞與閘極電極之間的寄生電容最小化的半導體元件。在所述圖案化製程中，可僅移除犧牲金屬層120而不移除下部閘極電極165a。在形成絕緣圖案135之後，可移除遮罩HM。
參考圖7E，可形成第一上部閘極電極165b_1。可沈積導電材料以形成第一上部閘極電極165b_1，所述第一上部閘極電極165b_1在共形地覆蓋下部閘極電極165a及絕緣圖案135的同時環繞上部通道層140b。第一上部閘極電極165b_1可在填充從中移除了犧牲金屬層120的空間的同時在上部通道層140b之間延伸。
參考圖7F，可形成第二上部閘極電極165b_2，且可形成閘極隔離圖案GC。
可藉由在第一上部閘極電極165b_1上沈積導電材料且執行平坦化製程來形成第二上部閘極電極165b_2。舉例而言，第二上部閘極電極165b_2可包含與第一上部閘極電極165b_1的導電材料不同的導電材料。可形成第二上部閘極電極165b_2以準備包括第一上部閘極電極165b_1及第二上部閘極電極165b_2的上部閘極電極165b。
可藉由形成穿過上部閘極電極165b及下部閘極電極165a暴露出元件隔離層107的開口且使用絕緣材料填充所述開口來形成閘極隔離圖案GC。閘極隔離圖案GC可被設置成在Y方向上間隔開，且可將鄰近的上部閘極電極165b與下部閘極電極165a實體地分隔開。因此，可形成彼此分隔開的多個閘極結構160。
接下來，參考圖2A至圖2C，可形成上部層間絕緣層183及184，且可形成第三接觸插塞173及上部互連線191，且可形成下部層間絕緣層185及186、下部互連線196、以及第一接觸插塞171及第二接觸插塞172的垂直延伸部分171V及172V。根據實施例，可藉由不同的製程操作形成第一接觸插塞171及第二接觸插塞172的垂直延伸部分171V及172V。
圖8A至圖8G是根據實例性實施例的製造半導體元件的方法的各個階段的視圖。
參考圖8A，可首先執行與圖7A中所述的製程相同或類似的製程。接下來，可形成閘極隔離圖案GC。可藉由在穿過絕緣材料層135’及下部閘極電極165a使得暴露出主動區105之間的元件隔離層107的開口中填充絕緣材料來形成閘極隔離圖案GC。
參考圖8B，可部分地移除絕緣材料層135’以暴露出虛設導電材料層165ad。可藉由相對於通道層140b及上部閘極介電層162b選擇性地蝕刻絕緣材料層135’來調整絕緣材料層135’的厚度。在蝕刻製程中，可不蝕刻閘極隔離圖案GC。因此，可暴露出閘極隔離圖案GC的側表面的一部分。
參考圖8C，可移除虛設導電材料層165ad，且可形成犧牲金屬層120。與參考圖7C所述的類似，可移除虛設導電材料層165ad，且可在被移除的區中形成包含與虛設導電材料層165ad不同的導電材料的犧牲金屬層120。
參考圖8D，可使用第一遮罩HM1形成絕緣圖案135。與參考圖7D所述的類似，可使用第一遮罩HM1藉由圖案化製程移除絕緣材料層135’的一部分來形成絕緣圖案135。在實例性實施例中，在圖案化製程中，可不蝕刻閘極隔離圖案GC，但根據實施例，可蝕刻閘極隔離圖案GC的上端的一部分。
參考圖8E，可形成第一上部閘極電極165b_1’。可藉由在下部閘極電極165a及絕緣圖案135上沈積導電材料以覆蓋上部通道層140b及閘極隔離圖案GC來形成第一上部閘極電極165b_1’。
第一上部閘極電極165b_1’可在形成閘極隔離圖案GC之後形成，且可因此包括沿著閘極隔離圖案GC的暴露的側表面延伸的一部分。因此，第一上部閘極電極165b_1’可包括突出部。
參考圖8F，可使用第二遮罩HM2移除第一上部閘極電極165b_1’的上端的一部分。第二遮罩HM2可形成於閘極隔離圖案GC之間，且可移除第一上部閘極電極165b_1’在第二遮罩HM2與閘極隔離圖案GC之間的一部分以暴露出閘極隔離圖案GC的側表面的一部分。舉例而言，可移除第一上部閘極電極165b_1’的突出部的一部分。在此操作中，可調整第一上部閘極電極165b_1’的上表面的水平高度。在移除第一上部閘極電極165b_1’的上端的所述部分之後，可移除第二遮罩HM2。
參考圖8G，可形成第二上部閘極電極165b_2’。可藉由在第一上部閘極電極165b_1’上沈積導電材料且執行平坦化製程來形成第二上部閘極電極165b_2’。第二上部閘極電極165b_2’可覆蓋閘極隔離圖案GC的側表面的一部分及第一上部閘極電極165b_1’在鄰近的閘極隔離圖案GC之間的突出部。
接下來，可形成上部層間絕緣層183及184以及上部互連線191，且可形成下部層間絕緣層185及186以及下部互連線196。
實施例的態樣提供一種具有改良的電性特性及可靠性的半導體元件。即，根據實施例，可在維持上部閘極電極與下部閘極電極之間的電性連接的同時在上部閘極電極與下部閘極電極之間的區中形成絕緣圖案以減小或最小化接觸插塞與閘極電極之間的寄生電容，進而提供具有改良的電性特性及可靠性的半導體元件。
本文中已揭露實例性實施例，且儘管採用具體用語，但該些用語僅在一般意義及闡述意義上使用及解釋且不用於限制目的。在一些實例中，截至對本申請案提出申請為止對於熟習此項技術者而言將顯而易見的是，結合特定實施例所述的特徵、特性及/或構件可單獨使用或與結合其他實施例所述的特徵、特性及/或構件組合使用，除非另有明確指示。因此，熟習此項技術者將理解，可做出形式及細節上的各種改變，而此並不背離以下申請專利範圍中陳述的本發明的精神及範疇。
100、100a、100b、100c、100d:半導體元件 101:基板 105:主動區 105a:第一主動區 105b:第二主動區 105c:第三主動區 105d:第四主動區 107:元件隔離層 120:犧牲金屬層 130:中間絕緣層 130S1:第一側 130S2:第二側 135:絕緣圖案 135’:絕緣材料層 140:通道層 140a:下部通道層/層 140b:上部通道層/層/通道層 150:源極/汲極區 150a:下部源極/汲極區/源極/汲極區 150b:上部源極/汲極區/源極/汲極區 160:閘極結構 162:閘極介電層 162a:下部閘極介電層/閘極介電層 162b:上部閘極介電層/閘極介電層 164:閘極間隔件 165:閘極電極 165a:下部閘極電極/閘極電極 165ad:虛設導電材料層 165b:上部閘極電極/閘極電極 165b’:上部閘極電極 165b_1、165b_1’:第一上部閘極電極 165b_2、165b_2’:第二上部閘極電極 171、171’:接觸插塞/第一接觸插塞 171H、172H:水平延伸部分 171V、171V’、172V:垂直延伸部分 172、172’:接觸插塞/第二接觸插塞 173:接觸插塞/第三接觸插塞 181:層間絕緣層/第一層間絕緣層 182:層間絕緣層/第二層間絕緣層 183:層間絕緣層/第一上部層間絕緣層/上部層間絕緣層 184:層間絕緣層/第二上部層間絕緣層/上部層間絕緣層 185:層間絕緣層/第一下部層間絕緣層/下部層間絕緣層 186:層間絕緣層/第二下部層間絕緣層/下部層間絕緣層 191:上部互連線 196:下部互連線 GC:閘極隔離圖案 HM:遮罩 HM1:第一遮罩 HM2:第二遮罩 I-I’、II-II’、III-III’、IV-IV’:線 P1、P1’:第一部分 P2:第二部分 t1:第一厚度 t2、t2’:第二厚度 t3:第三厚度 TRa:下部電晶體 TRb:上部電晶體 TRS:電晶體結構 TRS1:第一電晶體結構/電晶體結構 TRS2:第二電晶體結構/電晶體結構 TRS3:第三電晶體結構/電晶體結構 X、Y、Z:方向
藉由參考附圖詳細地闡述示例性實施例，各個特徵對於熟習此項技術者而言將變得顯而易見，在附圖中： 圖1是說明根據實例性實施例的半導體元件的平面圖。 圖2A至圖2C是說明根據實例性實施例的半導體元件的剖視圖。 圖3A及圖3B是說明根據實例性實施例的半導體元件的剖視圖。 圖4A及圖4B是說明根據實例性實施例的半導體元件的剖視圖。 圖5是說明根據實例性實施例的半導體元件的剖視圖。 圖6是說明根據實例性實施例的半導體元件的剖視圖。 圖7A至圖7F是說明根據實例性實施例的製造半導體元件的方法的製程順序的視圖。 圖8A至圖8G是說明根據實例性實施例的製造半導體元件的方法的製程順序的視圖。
100:半導體元件
105:主動區
105a:第一主動區
105b:第二主動區
105c:第三主動區
105d:第四主動區
135:絕緣圖案
150:源極/汲極區
160:閘極結構
164:閘極間隔件
165:閘極電極
171:接觸插塞/第一接觸插塞
GC:閘極隔離圖案
I-I’、II-II’、III-III’、IV-IV’:線
TRS:電晶體結構
TRS1:第一電晶體結構/電晶體結構
TRS2:第二電晶體結構/電晶體結構
TRS3:第三電晶體結構/電晶體結構
X、Y、Z:方向

Claims (10)

  1. 一種半導體元件，包括： 基板； 至少一個主動區，在第一水平方向上在所述基板上延伸； 通道層，堆疊於所述至少一個主動區上且彼此間隔開，所述通道層包括下部通道層與位於所述下部通道層上的上部通道層； 中間絕緣層，位於所述下部通道層中最上部的下部通道層與所述上部通道層中最下部的上部通道層之間； 閘極結構，與所述基板上的所述至少一個主動區及所述通道層相交，所述閘極結構在第二水平方向上延伸且包括環繞所述通道層的閘極電極，且所述閘極電極包括環繞所述下部通道層的下部閘極電極與環繞所述上部通道層的上部閘極電極； 絕緣圖案，位於所述上部閘極電極與所述下部閘極電極之間，所述絕緣圖案位於所述中間絕緣層在所述第二水平方向上的第一側上； 源極/汲極區，位於所述閘極結構的至少一側上，所述源極/汲極區包括連接至所述下部通道層的下部源極/汲極區與位於所述下部源極/汲極區上且連接至所述上部通道層的上部源極/汲極區；以及 接觸插塞，包括水平延伸部分與連接至所述水平延伸部分的垂直延伸部分，所述水平延伸部分連接至所述下部源極/汲極區中的每一者且在與所述基板平行的水平方向上延伸，且所述垂直延伸部分在與所述基板的上表面垂直的垂直方向上延伸。
  2. 如請求項1所述的半導體元件，其中所述絕緣圖案的至少一部分處於等於所述水平延伸部分的至少一部分的水平高度的水平高度處。
  3. 如請求項1所述的半導體元件，其中所述中間絕緣層的第一厚度大於所述絕緣圖案的第二厚度。
  4. 如請求項1所述的半導體元件，其中： 所述絕緣圖案的上表面接觸所述上部閘極電極，以及 所述絕緣圖案的下表面接觸所述下部閘極電極。
  5. 如請求項1所述的半導體元件，其中在鄰近所述中間絕緣層的與所述第一側相對的第二側的區中，所述上部閘極電極具有接觸所述下部閘極電極的區。
  6. 如請求項1所述的半導體元件，更包括位於所述基板下方的下部互連線， 其中所述至少一個主動區包括在所述第一水平方向上平行地延伸的多個主動區，以及 其中所述垂直延伸部分連接至所述下部互連線且自所述下部互連線穿過所述基板以在所述多個主動區中的鄰近的主動區之間延伸。
  7. 如請求項1所述的半導體元件，其中所述閘極結構更包括位於所述通道層與所述閘極電極之間的閘極介電層，所述閘極介電層覆蓋所述中間絕緣層的至少一個表面。
  8. 如請求項7所述的半導體元件，其中所述絕緣圖案藉由所述閘極介電層而與所述中間絕緣層間隔開。
  9. 一種半導體元件，包括： 基板； 主動區，在所述基板上在第一水平方向上彼此平行地延伸； 電晶體結構，在所述基板上在第二水平方向上彼此間隔開；以及 閘極隔離圖案，將所述電晶體結構實體地分隔開， 其中所述電晶體結構中的第一電晶體結構包括： 第一通道層，彼此間隔開且堆疊於所述主動區中的第一主動區上，所述第一通道層包括下部通道層及位於所述下部通道層上的上部通道層； 第一中間絕緣層，位於所述下部通道層中最上部的下部通道層與所述上部通道層中最下部的上部通道層之間； 第一閘極結構，與所述基板上的所述第一主動區及所述第一通道層相交，在所述第二水平方向上延伸且包括環繞所述第一通道層的第一閘極電極； 第一絕緣圖案，位於所述第一中間絕緣層在所述第二水平方向上的第一側與所述閘極隔離圖案之間；以及 第一源極/汲極區，位於所述第一閘極結構的至少一側上，所述第一源極/汲極區包括連接至所述下部通道層的下部源極/汲極區與連接至所述下部源極/汲極區上的所述上部通道層的上部源極/汲極區。
  10. 如請求項9所述的半導體元件，其中所述第一絕緣圖案的上表面及下表面接觸所述第一閘極電極，所述第一絕緣圖案的一個側表面接觸所述閘極隔離圖案。
TW112120208A 2022-07-06 2023-05-31 半導體元件 TW202404096A (zh)

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