TW202349615A - 增進打線接合承受力之晶片封裝的凸塊結構 - Google Patents

增進打線接合承受力之晶片封裝的凸塊結構 Download PDF

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TW202349615A
TW202349615A TW111121072A TW111121072A TW202349615A TW 202349615 A TW202349615 A TW 202349615A TW 111121072 A TW111121072 A TW 111121072A TW 111121072 A TW111121072 A TW 111121072A TW 202349615 A TW202349615 A TW 202349615A
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Taiwan
Prior art keywords
bump
chip
layer
thickness
wire bonding
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TW111121072A
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English (en)
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TWI819644B (zh
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于鴻祺
林俊榮
古瑞庭
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華東科技股份有限公司
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Priority to TW111121072A priority Critical patent/TWI819644B/zh
Priority to KR2020230001001U priority patent/KR20230002362U/ko
Priority to JP2023001932U priority patent/JP3243076U/ja
Priority to US18/206,591 priority patent/US20230395537A1/en
Application granted granted Critical
Publication of TWI819644B publication Critical patent/TWI819644B/zh
Publication of TW202349615A publication Critical patent/TW202349615A/zh

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

一種增進打線接合承受力之晶片封裝的凸塊結構，其中該晶片封裝之至少一凸塊係一具有一定厚度的金屬堆疊結構體，且各該凸塊的整體厚度係設定為4.5~20微米（µm），藉此增進各該凸塊的結構強度以承受來自打線接合（Wire Bonding）作業或形成一第一銲點時所產生的正壓力，使該晶片之至少一內部線路不會因該正壓力而受到破壞，而使各該內部線路能容許通過或安排在該晶片之至少一晶墊（Die Pad）的下方，有效地解決製造端需重新安排晶片之內部線路的設計而導致製造端成本增加的問題，有利於降低製造端的成本。

Description

增進打線接合承受力之晶片封裝的凸塊結構
本發明係一種晶片封裝的凸塊結構，尤指一種增進打線接合承受力之晶片封裝的凸塊結構。
在晶片封裝領域中，欲使晶片封裝與電子元件電性連結，可藉由打線接合（Wire Bonding）之技藝來實現，即藉一銲線以在晶片封裝結構上形成一銲點與電子元件上形成另一銲點，以使晶片封裝結構與電子元件電性連結在一起。然而，當在進行打線接合作業時，現有的晶片封裝結構承受來自打線接合作業或形成該銲點時所產生的正壓力，使晶片之內部線路因該正壓力而受到破壞，而使內部線路不容易或無法通過或安排在晶片內的各晶墊的下方，為此，製造端需重新安排晶片之內部線路的設計，進而導致製造端成本增加。
因此，一種有效地解決製造端需重新安排晶片之內部線路的設計而導致製造端成本增加之問題的增進打線接合承受力之晶片封裝的凸塊結構，為目前相關產業之迫切期待者。
本發明之主要目的在於提供一種增進打線接合承受力之晶片封裝的凸塊結構，其中該晶片封裝之至少一凸塊係一具有一定厚度的金屬堆疊結構體，且各該凸塊的整體厚度係設定為4.5~20微米（µm），藉此增進各該凸塊的結構強度以承受來自打線接合（Wire Bonding）作業或形成一第一銲點時所產生的正壓力，使該晶片之至少一內部線路不會因該正壓力而受到破壞，而使各該內部線路能容許通過或安排在該晶片之至少一晶墊（Die Pad）的下方，有效地解決製造端需重新安排晶片之內部線路的設計而導致製造端成本增加的問題。
為達成上述目的，本發明提供一種增進打線接合承受力之晶片封裝的凸塊結構，該晶片封裝包含一晶片、至少一介電層及至少一凸塊；其中該晶片具有一第一表面及至少一內部線路，該第一表面上設有至少一晶墊（Die Pad）及至少一保護層，其中該晶片係由一晶圓上所分割下來形成；其中各該介電層係對應地覆蓋設於該晶片之該第一表面上，各該介電層具有至少一開口且各該開口與該晶片之各該晶墊位置對應；其中各該凸塊係設於各該介電層之各該開口內並向上露出，且各該凸塊係一層狀堆疊結構體且電性連結地設於該晶片之各該晶墊之頂面上；其中當在進行打線接合（Wire Bonding）作業時，藉一銲線以在各該凸塊上形成一第一銲點與一電子元件上形成一第二銲點，以使該晶片封裝與該電子元件電性連結在一起；該晶片封裝特徵在於：各該凸塊係一由各該晶墊之頂面上往上依序包括一鎳（Ni）層及一金（Au）層所組成且具有一定厚度的金屬堆疊結構體，其中各該凸塊的整體厚度係設定為4.5~20微米（µm），藉此增進各該凸塊的結構強度以承受來自打線接合作業或形成該第一銲點時所產生的正壓力，使該晶片之各該內部線路不會因該正壓力而受到破壞，而使各該內部線路能容許通過或安排在各該晶墊的下方，有利於降低製造端的成本。
在本發明一較佳實施例中，該金（Au）層在各該凸塊中的所佔的厚度為0.005~0.2微米（µm），其餘的各該凸塊厚度為該鎳（Ni）層的厚度。
為達成上述目的，本發明更提供一種增進打線接合承受力之晶片封裝的凸塊結構，該晶片封裝包含一晶片、至少一介電層及至少一凸塊；其中該晶片具有一第一表面及至少一內部線路，該第一表面上設有至少一晶墊（Die Pad）及至少一保護層，其中該晶片係由一晶圓上所分割下來形成；其中各該介電層係對應地覆蓋設於該晶片之該第一表面上，各該介電層具有至少一開口且各該開口與該晶片之各該晶墊位置對應；其中各該凸塊係設於各該介電層之各該開口內並向上露出，且各該凸塊係一層狀堆疊結構體且電性連結地設於該晶片之各該晶墊之頂面上；其中當在進行打線接合（Wire Bonding）作業時，藉一銲線以在各該凸塊上形成一第一銲點與一電子元件上形成一第二銲點，以使該晶片封裝與該電子元件電性連結在一起；其特徵在於：各該凸塊係一由各該晶墊之頂面上往上依序包括一鎳（Ni）層、一鈀（Pd）層及一金（Au）層所組成且具有一定厚度的金屬堆疊結構體，其中各該凸塊的整體厚度係設定為4.5~20微米（µm），藉此增進各該凸塊的結構強度以承受來自打線接合作業或形成該第一銲點時所產生的正壓力，使該晶片之各該內部線路不會因該正壓力而受到破壞，而使各該內部線路能容許通過或安排在各該晶墊的下方，有利於降低製造端的成本。
在本發明一較佳實施例中，該金（Au）層在各該凸塊中的所佔的厚度為0.005~0.2微米（µm），該鈀（Pd）層在各該凸塊中的所佔的厚度為0.005~0.3微米（µm），其餘的各該凸塊厚度為該鎳（Ni）層的厚度。
配合圖示，將本發明的結構及其技術特徵詳述如後，其中各圖示只用以說明本發明的結構關係及相關功能，因此各圖示中各元件的尺寸並非依實際比例畫製且非用以限制本發明。
參考圖1、3、5及6，本發明提供一種增進打線接合承受力之晶片封裝的凸塊結構，該晶片封裝1、1a包含一晶片10、至少一介電層20及至少一凸塊30；其中該晶片10具有一第一表面10a及至少一內部線路13，該第一表面10a上設有至少一晶墊（Die Pad）11及至少一保護層12，其中該晶片10係由一晶圓2上所分割下來形成（如圖2及4所示）；其中各該介電層20係對應地覆蓋設於該晶片10之該第一表面10a上，各該介電層20具有至少一開口21且各該開口21與該晶片10之各該晶墊11位置對應；其中各該凸塊30係設於各該介電層20之各該開口21內並向上露出，且各該凸塊30係一層狀堆疊結構體且電性連結地設於該晶片10之各該晶墊11之頂面上；其中當在進行打線接合（Wire Bonding）作業時如圖1及3所示，藉一銲線3以在各該凸塊30上形成一第一銲點31與一電子元件4上形成一第二銲點4a，以使該晶片封裝1、1a與該電子元件4電性連結在一起如圖1及3所示。
其中，各該內部線路13係包含13a陣列區（Array）、13b電路區（Circuitry area）或電路細胞元（Cell）（未圖示）但不限制如圖9及10所示。
根據本發明的各該凸塊30的組成該層狀堆疊結構體的組成材料或成分的不同，可進一步分為第一實施例（該晶片封裝1）及第二實施例（該晶片封裝1a）如圖1及3所示；其中該晶片10及各該介電層20在第一實施例（該晶片封裝1）中或第二實施例（該晶片封裝1a）中的結構構造或技術特徵上皆相同。
在圖1、2、5及7中所示之實施例為本發明之第一實施例（該晶片封裝1），在第一實施例中，各該凸塊30係一由各該晶墊11之頂面上往上依序包括一鎳（Ni）層32及一金（Au）層33所組成且具有一定厚度的金屬堆疊結構體如圖1及5所示，其中各該凸塊30的整體厚度係設定為4.5~20微米（µm）如圖7所示，藉此增進各該凸塊30的結構強度以承受來自打線接合作業或形成該第一銲點31時所產生的正壓力N如圖1所示，使該晶片10之各該內部線路13不會因該正壓力N（如圖1所示）而受到破壞，而使各該內部線路13能容許通過或安排在各該晶墊11的下方如圖1及10所示。
其中，該金（Au）層33在各該凸塊30中的所佔的厚度為0.005~0.2微米（µm）但不限制如圖7所示，其餘的各該凸塊30厚度為該鎳（Ni）層32的厚度，如此的比例分配能降低較高成本的該金（Au）層33之使用量，又能使各該凸塊30不失去一定的結構強度，有利於降低製造端成本。
在圖3、4、6及8中所示之實施例為本發明之第二實施例（該晶片封裝1a），在第二實施例中，各該凸塊30係一由各該晶墊11之頂面上往上依序包括一鎳（Ni）層32、一鈀（Pd）層34及一金（Au）層33所組成且具有一定厚度的金屬堆疊結構體如圖3及6所示，其中各該凸塊30的整體厚度係設定為4.5~20微米（µm）如圖8所示，藉此增進各該凸塊30的結構強度以承受來自打線接合作業或形成該第一銲點31時所產生的正壓力N如圖3所示，使該晶片10之各該內部線路13不會因該正壓力N（如圖3所示）而受到破壞，而使各該內部線路13能容許通過或安排在各該晶墊11的下方如圖3及10所示。
其中，該金（Au）層33在各該凸塊30中的所佔的厚度為0.005~0.2微米（µm）但不限制如圖8所示，該鈀（Pd）層34在各該凸塊30中的所佔的厚度為0.005~0.3微米（µm）但不限制如圖8所示，其餘的各該凸塊30厚度為該鎳（Ni）層32的厚度，如此的比例分配能降低較高成本的該金（Au）層33之使用量，又能使各該凸塊30不失去一定的結構強度，有利於降低製造端成本。
本發明與現有的晶片封裝結構相較，具有以下優點：
本發明的該晶片封裝1、1a（即第一實施例及第二實施例）之各該凸塊30係一具有一定厚度的金屬堆疊結構體，如上述第一實施例（如圖1、2、5及7所示）所揭示由該鎳（Ni）層32及該金（Au）層33、或第二實施例（如圖3、4、6及8所示）所揭示由該鎳（Ni）層32、該鈀（Pd）層34及金（Au）層33所組成，且各該凸塊30的整體厚度係設定為4.5~20微米（µm）如圖7及8所示，藉此增進各該凸塊30的結構強度以承受來自打線接合作業或形成該第一銲點31時所產生的正壓力N如圖1及3所示，使該晶片10之各該內部線路13不會因該正壓力N（如圖1及3所示）而受到破壞，而使各該內部線路13能容許通過或安排在該晶片10之各該晶墊11的下方如圖10所示，有效地解決製造端需重新安排晶片之內部線路的設計而導致製造端成本增加的問題，有利於降低製造端的成本。
以上該僅為本發明的優選實施例，對本發明而言僅是說明性的，而非限制性的；本領域普通技術人員理解，在本發明權利要求所限定的精神和範圍內可對其進行許多改變，修改，甚至等效變更，但都將落入本發明的保護範圍內。
1:晶片封裝 1a:晶片封裝 10:晶片 10a:第一表面 11:晶墊 12:保護層 13:內部線路 13a:陣列區 13b:電路區 20:介電層 21:開口 30:凸塊 31:第一銲點 32:鎳層 33:金層 34:鈀層 2:晶圓 3:銲線 4:電子元件 4a:第二銲點
圖1為本發明第一實施例之側視剖面平面示意圖。 圖2為第一實施例之晶片係由晶圓上所分割之側視剖面平面示意圖。 圖3為本發明第二實施例之側視剖面平面示意圖。 圖4為第二實施例之晶片係由晶圓上所分割之側視剖面平面示意圖。 圖5為第一實施例之晶片封裝之側視剖面平面示意圖。 圖6為第二實施例之晶片封裝之側視剖面平面示意圖。 圖7為圖5之局部放大示意圖。 圖8為圖6之局部放大示意圖。 圖9為本發明之內部線路之上視平面示意圖。 圖10為本發明之晶片封裝之上視平面示意圖。
1:晶片封裝
10:晶片
10a:第一表面
11:晶墊
12:保護層
13:內部線路
20:介電層
21:開口
30:凸塊
31:第一銲點
32:鎳層
33:金層
3:銲線
4:電子元件
4a:第二銲點

Claims (4)

  1. 一種增進打線接合承受力之晶片封裝的凸塊結構，該晶片封裝包含一晶片、至少一介電層及至少一凸塊；其中該晶片具有一第一表面及至少一內部線路，該第一表面上設有至少一晶墊（Die Pad）及至少一保護層，其中該晶片係由一晶圓上所分割下來形成；其中各該介電層係對應地覆蓋設於該晶片之該第一表面上，各該介電層具有至少一開口且各該開口與該晶片之各該晶墊位置對應；其中各該凸塊係設於各該介電層之各該開口內並向上露出，且各該凸塊係一層狀堆疊結構體且電性連結地設於該晶片之各該晶墊之頂面上；其中當在進行打線接合（Wire Bonding）作業時，藉一銲線以在各該凸塊上形成一第一銲點與一電子元件上形成一第二銲點，以使該晶片封裝與該電子元件電性連結在一起；其特徵在於： 各該凸塊係一由各該晶墊之頂面上往上依序包括一鎳（Ni）層及一金（Au）層所組成且具有一定厚度的金屬堆疊結構體，其中各該凸塊的整體厚度係設定為4.5~20微米（µm），藉此增進各該凸塊的結構強度以承受來自打線接合作業或形成該第一銲點時所產生的正壓力，使該晶片之各該內部線路不會因該正壓力而受到破壞，而使各該內部線路能容許通過或安排在各該晶墊的下方。
  2. 如請求項1所述之晶片封裝的凸塊結構，其中該金（Au）層在各該凸塊中的所佔的厚度為0.005~0.2微米（µm），其餘的各該凸塊厚度為該鎳（Ni）層的厚度。
  3. 一種增進打線接合承受力之晶片封裝的凸塊結構，該晶片封裝包含一晶片、至少一介電層及至少一凸塊；其中該晶片具有一第一表面及至少一內部線路，該第一表面上設有至少一晶墊（Die Pad）及至少一保護層，其中該晶片係由一晶圓上所分割下來形成；其中各該介電層係對應地覆蓋設於該晶片之該第一表面上，各該介電層具有至少一開口且各該開口與該晶片之各該晶墊位置對應；其中各該凸塊係設於各該介電層之各該開口內並向上露出，且各該凸塊係一層狀堆疊結構體且電性連結地設於該晶片之各該晶墊之頂面上；其中當在進行打線接合（Wire Bonding）作業時，藉一銲線以在各該凸塊上形成一第一銲點與一電子元件上形成一第二銲點，以使該晶片封裝與該電子元件電性連結在一起；其特徵在於： 各該凸塊係一由各該晶墊之頂面上往上依序包括一鎳（Ni）層、一鈀（Pd）層及一金（Au）層所組成且具有一定厚度的金屬堆疊結構體，其中各該凸塊的整體厚度係設定為4.5~20微米（µm），藉此增進各該凸塊的結構強度以承受來自打線接合作業或形成該第一銲點時所產生的正壓力，使該晶片之各該內部線路不會因該正壓力而受到破壞，而使各該內部線路能容許通過或安排在各該晶墊的下方。
  4. 如請求項3所述之晶片封裝的凸塊結構，其中該金（Au）層在各該凸塊中的所佔的厚度為0.005~0.2微米（µm），該鈀（Pd）層在各該凸塊中的所佔的厚度為0.005~0.3微米（µm），其餘的各該凸塊厚度為該鎳（Ni）層的厚度。
TW111121072A 2022-06-07 2022-06-07 增進打線接合承受力之晶片封裝的凸塊結構 TWI819644B (zh)

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