CN117293106A - 增进打线接合承受力的芯片封装的凸块结构 - Google Patents

增进打线接合承受力的芯片封装的凸块结构 Download PDF

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CN117293106A
CN117293106A CN202210690421.6A CN202210690421A CN117293106A CN 117293106 A CN117293106 A CN 117293106A CN 202210690421 A CN202210690421 A CN 202210690421A CN 117293106 A CN117293106 A CN 117293106A
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bump
chip
layer
thickness
wire bonding
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于鸿祺
林俊荣
古瑞庭
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Walton Advanced Engineering Inc
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    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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Abstract

本发明公开一种增进打线接合承受力的芯片封装的凸块结构，其中该芯片封装的至少一凸块为一具有一定厚度的金属堆叠结构体，且每一该凸块的整体厚度设定为4.5～20微米(μm)，以此增进每一该凸块的结构强度以承受来自打线接合(Wire Bonding)作业或形成一第一焊点时所产生的正压力，使该芯片的至少一内部线路不会因该正压力而受到破坏，而使每一该内部线路能容许通过或安排在该芯片的至少一晶垫(Die Pad)的下方，有效地解决制造端需重新安排芯片的内部线路的设计而导致制造端成本增加的问题，有利于降低制造端的成本。

Description

增进打线接合承受力的芯片封装的凸块结构
技术领域
本发明涉及一种芯片封装的凸块结构，尤指一种增进打线接合承受力的芯片封装的凸块结构。
背景技术
在芯片封装领域中，欲使芯片封装与电子元件电性连接，可通过打线接合(WireBonding)的技艺来实现，即通过一焊线以在芯片封装结构上形成一焊点与电子元件上形成另一焊点，以使芯片封装结构与电子元件电性连接在一起。然而，当在进行打线接合作业时，现有的芯片封装结构承受来自打线接合作业或形成该焊点时所产生的正压力，使芯片的内部线路因该正压力而受到破坏，而使内部线路不容易或无法通过或安排在芯片内的各晶垫的下方，为此，制造端需重新安排芯片的内部线路的设计，进而导致制造端成本增加。
因此，一种有效地解决制造端需重新安排芯片的内部线路的设计而导致制造端成本增加的问题的增进打线接合承受力的芯片封装的凸块结构，为目前相关产业的迫切期待。
发明内容
本发明的主要目的在于提供一种增进打线接合承受力的芯片封装的凸块结构，其中该芯片封装的至少一凸块为一具有一定厚度的金属堆叠结构体，且每一该凸块的整体厚度设定为4.5～20微米(μm)，以此增进每一该凸块的结构强度以承受来自打线接合(WireBonding)作业或形成一第一焊点时所产生的正压力，使该芯片的至少一内部线路不会因该正压力而受到破坏，而使每一该内部线路能容许通过或安排在该芯片的至少一晶垫(DiePad)的下方，有效地解决制造端需重新安排芯片的内部线路的设计而导致制造端成本增加的问题。
为达成上述目的，本发明提供一种增进打线接合承受力的芯片封装的凸块结构，该芯片封装包含一芯片、至少一介电层及至少一凸块；其中该芯片具有一第一表面及至少一内部线路，该第一表面上设有至少一晶垫(Die Pad)及至少一保护层，其中该芯片是由一晶圆上所分割下来形成；其中每一该介电层对应地覆盖设于该芯片的该第一表面上，每一该介电层具有至少一开口且每一该开口与该芯片的每一该晶垫位置对应；其中每一该凸块设于每一该介电层的每一该开口内并向上露出，且每一该凸块为一层状堆叠结构体且电性连接地设于该芯片的每一该晶垫的顶面上；其中当在进行打线接合(Wire Bonding)作业时，通过一焊线以在每一该凸块上形成一第一焊点与一电子元件上形成一第二焊点，以使该芯片封装与该电子元件电性连接在一起；该芯片封装中：每一该凸块是一由每一该晶垫的顶面上往上依序包括一镍(Ni)层及一金(Au)层所组成且具有一定厚度的金属堆叠结构体，其中每一该凸块的整体厚度设定为4.5～20微米(μm)，以此增进每一该凸块的结构强度以承受来自打线接合作业或形成该第一焊点时所产生的正压力，使该芯片的每一该内部线路不会因该正压力而受到破坏，而使每一该内部线路能容许通过或安排在每一该晶垫的下方，有利于降低制造端的成本。
在本发明一较佳实施例中，该金(Au)层在每一该凸块中的所占的厚度为0.005～0.2微米(μm)，每一该凸块厚度其余的为该镍(Ni)层的厚度。
为达成上述目的，本发明还提供一种增进打线接合承受力的芯片封装的凸块结构，该芯片封装包含一芯片、至少一介电层及至少一凸块；其中该芯片具有一第一表面及至少一内部线路，该第一表面上设有至少一晶垫(Die Pad)及至少一保护层，其中该芯片是由一晶圆上所分割下来形成；其中每一该介电层对应地覆盖设于该芯片的该第一表面上，每一该介电层具有至少一开口且每一该开口与该芯片的每一该晶垫位置对应；其中每一该凸块设于每一该介电层的每一该开口内并向上露出，且每一该凸块为一层状堆叠结构体且电性连接地设于该芯片的每一该晶垫的顶面上；其中当在进行打线接合(Wire Bonding)作业时，通过一焊线以在每一该凸块上形成一第一焊点与一电子元件上形成一第二焊点，以使该芯片封装与该电子元件电性连接在一起；其中：每一该凸块是一由每一该晶垫的顶面上往上依序包括一镍(Ni)层、一钯(Pd)层及一金(Au)层所组成且具有一定厚度的金属堆叠结构体，其中每一该凸块的整体厚度设定为4.5～20微米(μm)，以此增进每一该凸块的结构强度以承受来自打线接合作业或形成该第一焊点时所产生的正压力，使该芯片的每一该内部线路不会因该正压力而受到破坏，而使每一该内部线路能容许通过或安排在每一该晶垫的下方，有利于降低制造端的成本。
在本发明一较佳实施例中，该金(Au)层在每一该凸块中的所占的厚度为0.005～0.2微米(μm)，该钯(Pd)层在每一该凸块中的所占的厚度为0.005～0.3微米(μm)，每一该凸块其余的厚度为该镍(Ni)层的厚度。
附图说明
图1为本发明第一实施例的侧视剖面平面示意图。
图2为第一实施例的芯片由晶圆上所分割的侧视剖面平面示意图。
图3为本发明第二实施例的侧视剖面平面示意图。
图4为第二实施例的芯片由晶圆上所分割的侧视剖面平面示意图。
图5为第一实施例的芯片封装的侧视剖面平面示意图。
图6为第二实施例的芯片封装的侧视剖面平面示意图。
图7为图5的局部放大示意图。
图8为图6的局部放大示意图。
图9为本发明的内部线路的上视平面示意图。
图10为本发明的芯片封装的上视平面示意图。
附图标记说明：1-芯片封装；1a-芯片封装；10-芯片；10a-第一表面；11-晶垫；12-保护层；13-内部线路；13a-阵列区；13b-电路区；20-介电层；21-开口；30-凸块；31-第一焊点；32-镍层；33-金层；34-钯层；2-晶圆；3-焊线；4-电子元件；4a-第二焊点。
具体实施方式
配合图示，将本发明的结构及其技术特征详述如下，其中各图示只用以说明本发明的结构关系及相关功能，因此各图示中各元件的尺寸并非依实际比例画制且非用以限制本发明。
参考图1、图3、图5及图6，本发明提供一种增进打线接合承受力的芯片封装的凸块结构，该芯片封装1、1a包含一芯片10、至少一介电层20及至少一凸块30；其中该芯片10具有一第一表面10a及至少一内部线路13，该第一表面10a上设有至少一晶垫(Die Pad)11及至少一保护层12，其中该芯片10是由一晶圆2上所分割下来形成(如图2及图4所示)；其中每一该介电层20对应地覆盖设于该芯片10的该第一表面10a上，每一该介电层20具有至少一开口21且每一该开口21与该芯片10的各晶垫11位置对应；其中每一该凸块30设于各介电层20的各开口21内并向上露出，且每一该凸块30为一层状堆叠结构体且电性连接地设于该芯片10的各晶垫11的顶面上；其中当在进行打线接合(Wire Bonding)作业时如图1及图3所示，通过一焊线3以在各凸块30上形成一第一焊点31与一电子元件4上形成一第二焊点4a，以使该芯片封装1、1a与该电子元件4电性连接在一起如图1及图3所示。
其中，每一该内部线路13包含13a阵列区(Array)、13b电路区(Circuitry area)或电路细胞元(Cell)(未图示)但不限制如图9及图10所示。
根据本发明的每一该凸块30的组成该层状堆叠结构体的组成材料或成分的不同，可进一步分为第一实施例(该芯片封装1)及第二实施例(该芯片封装1a)如图1及图3所示；其中该芯片10及每一该介电层20在第一实施例(该芯片封装1)中或第二实施例(该芯片封装1a)中的结构构造或技术特征上皆相同。
在图1、图2、图5及图7中所示的实施例为本发明的第一实施例(该芯片封装1)，在第一实施例中，每一该凸块30是一由各晶垫11的顶面上往上依序包括一镍(Ni)层32及一金(Au)层33所组成且具有一定厚度的金属堆叠结构体如图1及图5所示，其中每一该凸块30的整体厚度设定为4.5～20微米(μm)如图7所示，以此增进每一该凸块30的结构强度以承受来自打线接合作业或形成该第一焊点31时所产生的正压力N如图1所示，使该芯片10的各内部线路13不会因该正压力N(如图1所示)而受到破坏，而使各内部线路13能容许通过或安排在各晶垫11的下方如图1及图10所示。
其中，该金(Au)层33在每一该凸块30中的所占的厚度为0.005～0.2微米(μm)但不限制如图7所示，各凸块30其余的厚度为该镍(Ni)层32的厚度，如此的比例分配能降低较高成本的该金(Au)层33的使用量，又能使每一该凸块30不失去一定的结构强度，有利于降低制造端成本。
在图3、图4、图6及图8中所示的实施例为本发明的第二实施例(该芯片封装1a)，在第二实施例中，每一该凸块30是一由各晶垫11的顶面上往上依序包括一镍(Ni)层32、一钯(Pd)层34及一金(Au)层33所组成且具有一定厚度的金属堆叠结构体如图3及图6所示，其中每一该凸块30的整体厚度设定为4.5～20微米(μm)如图8所示，以此增进各凸块30的结构强度以承受来自打线接合作业或形成该第一焊点31时所产生的正压力N如图3所示，使该芯片10的各内部线路13不会因该正压力N(如图3所示)而受到破坏，而使各内部线路13能容许通过或安排在各晶垫11的下方如图3及图10所示。
其中，该金(Au)层33在各凸块30中的所占的厚度为0.005～0.2微米(μm)但不限制如图8所示，该钯(Pd)层34在各凸块30中的所占的厚度为0.005～0.3微米(μm)但不限制如图8所示，各凸块30其余的厚度为该镍(Ni)层32的厚度，如此的比例分配能降低较高成本的该金(Au)层33的使用量，又能使各凸块30不失去一定的结构强度，有利于降低制造端成本。
本发明与现有的芯片封装结构相较，具有以下优点：
本发明的该芯片封装1、1a(即第一实施例及第二实施例)的各凸块30是一具有一定厚度的金属堆叠结构体，如上述第一实施例(如图1、图2、图5及图7所示)所揭示由该镍(Ni)层32及该金(Au)层33、或第二实施例(如图3、图4、图6及图8所示)所揭示由该镍(Ni)层32、该钯(Pd)层34及金(Au)层33所组成，且各凸块30的整体厚度设定为4.5～20微米(μm)如图7及图8所示，以此增进各凸块30的结构强度以承受来自打线接合作业或形成该第一焊点31时所产生的正压力N如图1及图3所示，使该芯片10的各内部线路13不会因该正压力N(如图1及图3所示)而受到破坏，而使各内部线路13能容许通过或安排在该芯片10的各晶垫11的下方如图10所示，有效地解决制造端需重新安排芯片的内部线路的设计而导致制造端成本增加的问题，有利于降低制造端的成本。
以上所述仅为本发明的优选实施例，对本发明而言其仅是说明性的，而非限制性的；本领域普通技术人员理解，在本发明权利要求所限定的精神和范围内可对其进行许多改变，修改，甚至等效变更，但都将落入本发明的保护范围内。

Claims (4)

1.一种增进打线接合承受力的芯片封装的凸块结构，该芯片封装包含一芯片、至少一介电层及至少一凸块；其中该芯片具有一第一表面及至少一内部线路，该第一表面上设有至少一晶垫及至少一保护层，其中该芯片是由一晶圆上所分割下来形成；其中每一该介电层对应地覆盖设于该芯片的该第一表面上，每一该介电层具有至少一开口且每一该开口与该芯片的每一该晶垫位置对应；其中每一该凸块设于每一该介电层的每一该开口内并向上露出，且每一该凸块为一层状堆叠结构体且电性连接地设于该芯片的每一该晶垫的顶面上；其中当在进行打线接合作业时，通过一焊线以在每一该凸块上形成一第一焊点与一电子元件上形成一第二焊点，以使该芯片封装与该电子元件电性连接在一起；其特征在于：
每一该凸块是一由每一该晶垫的顶面上往上依序包括一镍层及一金层所组成且具有一定厚度的金属堆叠结构体，其中每一该凸块的整体厚度设定为4.5～20微米，以此增进每一该凸块的结构强度以承受来自打线接合作业或形成该第一焊点时所产生的正压力，使该芯片的每一该内部线路不会因该正压力而受到破坏，而使每一该内部线路能容许通过或安排在每一该晶垫的下方。
2.如权利要求1所述的芯片封装的凸块结构，其特征在于，该金层在每一该凸块中的所占的厚度为0.005～0.2微米，每一该凸块其余的厚度为该镍层的厚度。
3.一种增进打线接合承受力的芯片封装的凸块结构，该芯片封装包含一芯片、至少一介电层及至少一凸块；其中该芯片具有一第一表面及至少一内部线路，该第一表面上设有至少一晶垫及至少一保护层，其中该芯片是由一晶圆上所分割下来形成；其中每一该介电层对应地覆盖设于该芯片的该第一表面上，每一该介电层具有至少一开口且每一该开口与该芯片的每一该晶垫位置对应；其中每一该凸块设于每一该介电层的每一该开口内并向上露出，且每一该凸块为一层状堆叠结构体且电性连接地设于该芯片的每一该晶垫的顶面上；其中当在进行打线接合作业时，通过一焊线以在每一该凸块上形成一第一焊点与一电子元件上形成一第二焊点，以使该芯片封装与该电子元件电性连接在一起；其特征在于：
每一该凸块是一由每一该晶垫的顶面上往上依序包括一镍层、一钯层及一金层所组成且具有一定厚度的金属堆叠结构体，其中每一该凸块的整体厚度设定为4.5～20微米，以此增进每一该凸块的结构强度以承受来自打线接合作业或形成该第一焊点时所产生的正压力，使该芯片的每一该内部线路不会因该正压力而受到破坏，而使每一该内部线路能容许通过或安排在每一该晶垫的下方。
4.如权利要求3所述的芯片封装的凸块结构，其特征在于，该金层在每一该凸块中的所占的厚度为0.005～0.2微米，该钯层在每一该凸块中的所占的厚度为0.005～0.3微米，每一该凸块其余的厚度为该镍层的厚度。
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