TW202347795A - 多堆疊半導體元件與其製造方法 - Google Patents
多堆疊半導體元件與其製造方法 Download PDFInfo
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- TW202347795A TW202347795A TW112112359A TW112112359A TW202347795A TW 202347795 A TW202347795 A TW 202347795A TW 112112359 A TW112112359 A TW 112112359A TW 112112359 A TW112112359 A TW 112112359A TW 202347795 A TW202347795 A TW 202347795A
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Abstract
本發明提供一種多堆疊半導體元件,包含:較低場效電晶體,其中較低通道結構由較低閘極結構圍繞,所述較低閘極結構包含較低閘極介電層、較低功函數金屬層以及較低閘極金屬圖案;以及較高場效電晶體,其中較高通道結構由較高閘極結構圍繞,所述較高閘極結構包含較高閘極介電層、較高功函數金屬層以及較高閘極金屬圖案,其中較高通道結構的通道寬度小於較低通道結構的通道寬度,且其中替換金屬閘極(RMG)內部間隔在較低通道結構並不由較高通道結構豎直地重疊的區處形成於較低功函數金屬層與較高功函數金屬層之間。
Description
根據實施例的設備及方法為關於包含具有替換金屬閘極(replacement metal gate;RMG)內部間隔的閘極結構的多堆疊半導體元件,所述替換金屬閘極內部間隔在多堆疊半導體元件的形成期間保護閘極結構的較低功函數金屬層。
發展需要具有已引入三維(three-dimensional;3D)多堆疊半導體元件的高元件密度的積體電路,所述三維多堆疊半導體元件中垂直地堆疊諸如奈米片電晶體的兩個或大於兩個場效電晶體。奈米片電晶體的特徵在於多個奈米片通道層豎直地堆疊於基底及圍繞奈米片通道層的所有表面的閘極結構上。因此,奈米片電晶體被稱作環繞式閘極(gate-all-around;GAA)電晶體、多橋接通道場效電晶體(multi-bridge channel field-effect transistor;MBCFET)。
包含兩個豎直地堆疊的奈米片電晶體的多堆疊半導體元件可由以下操作來製造:形成較低奈米片堆疊及位於所述較低奈米片堆疊上的較高奈米片堆疊,用虛設閘極結構封閉奈米片堆疊,在各奈米片堆疊上磊晶生長源極/汲極區域,以及用閘極結構替換虛設閘極結構,所述閘極結構包含閘極介電層、功函數金屬層及閘極金屬圖案,藉此形成較低奈米片電晶體及位於所述較低奈米片電晶體上的較高奈米片電晶體。由於閘極結構代替半導體元件的製造中的虛設閘極結構,因此閘極結構亦可稱為替換金屬閘極(RMG)結構。
當要求區分多堆疊半導體元件中的較低奈米片電晶體與較高奈米片電晶體之間的閘極結構時,可針對兩個電晶體的較低閘極結構及較高閘極結構以不同方式形成功函數金屬層。舉例而言,當多堆疊半導體元件將形成包含相對極性場效電晶體(即p型及n型場效電晶體)的互補金屬化氧化物電晶體(complementary-metal-oxide transistor;CMOS)結構時,閘極結構的較低功函數金屬層及較高功函數金屬層可形成為包含不同材料或材料化合物以具有不同臨限電壓,從而對於較低奈米片電晶體及較高奈米片電晶體不同地驅動較低閘極結構及較高閘極結構
然而,在形成用於多堆疊半導體元件中的較低奈米片電晶體及較高奈米片電晶體的兩個不同功函數金屬層中存在挑戰。
此背景技術部分中所揭露的資訊在達成本申請案的實施例的過程之前或期間已被本發明人知曉或得出,或為在達成實施例的過程中所獲取的技術資訊。因此,其可含有未形成已由公眾知曉的先前技術的資訊。
本發明提供一種多堆疊半導體元件及其製造方法,所述多堆疊半導體元件包含具有保護閘極結構的較低功函數金屬層的內部間隔的閘極結構。
根據實施例,提供一種多堆疊半導體元件,其可包含:基底;較低場效電晶體,其中較低通道結構由較低閘極結構圍繞,所述較低閘極結構包含較低閘極介電層、較低功函數金屬層以及較低閘極金屬圖案;以及較高場效電晶體,其中較高通道結構由較高閘極結構圍繞,所述較高閘極結構包含較高閘極介電層、較高功函數金屬層以及較高閘極金屬圖案,其中較高通道結構的通道寬度小於較低通道結構的通道寬度,且其中內部間隔在較低通道結構並不由較高通道結構豎直地重疊的區處形成於較低功函數金屬層與較高功函數金屬層之間。
根據實施例,多堆疊半導體元件的至少較低場效電晶體可為奈米片電晶體,且較低通道結構可包含豎直地堆疊於基底上的多個奈米片層。
根據實施例,內部間隔形成於其上的較低功函數金屬層的頂部表面低於較低閘極金屬圖案的頂部表面的層級。
根據實施例,提供一種多堆疊半導體元件,其可包含:基底;較低場效電晶體,其中較低通道結構由較低閘極結構圍繞,所述較低閘極結構包含較低閘極介電層、較低功函數金屬層以及較低閘極金屬圖案;以及較高場效電晶體,其中較高通道結構由較高閘極結構圍繞,所述較高閘極結構包含較高閘極介電層、較高功函數金屬層以及較高閘極金屬圖案,其中內部間隔在通道寬度方向上在較低閘極金屬圖案的一側處形成於較低功函數金屬層與較高功函數金屬層之間。
根據實施例,提供一種製造多堆疊半導體元件的方法。方法可包含:(a)為各別較低場效電晶體及較高場效電晶體提供由閘極結構圍繞的較低通道結構及較高通道結構,所述閘極結構包含第一功函數金屬層及第一閘極金屬圖案;(b)除形成於較高通道結構的較高通道層之間的第一功函數金屬層外,將第一閘極金屬圖案及第一功函數金屬層向下移除至較低通道結構與較高通道結構之間的層級,使得多個凹槽在選定區處形成於層級下方的第一功函數金屬層上的第一閘極金屬圖案的側處;(c)在多個凹槽中形成內部間隔,且移除較高通道層之間的第一功函數金屬層;(d)將包括不同於第一功函數金屬層的材料的第二功函數金屬層形成於較高通道結構上且將第一閘極金屬圖案剩餘在層級下方;以及以及(e)將第二閘極金屬圖案形成於第二功函數金屬層上。
本文中所描述的實施例為示例性實施例,且因此,本揭露內容不限於此且可以各種其他形式實現。以下描述中所提供的實施例中的各者不排除與本文中亦提供或本文中未提供但與本揭露內容一致的另一實例或另一實施例的一或多個特徵相關聯。舉例而言,即使特定實例或實施例中所描述的物質未在另外的不同實例或實施例中描述,除非在其描述中另外提及,否則所述物質仍可理解為與不同實例或實施例相關或與不同實例或實施例組合。另外,應理解,對本揭露內容的原理、態樣、實例以及實施例的所有描述均意欲涵蓋所述原理、態樣、實例以及特定實施例的結構及功能等效物。另外,此等等效物應理解為不僅包含當前眾所周知的等效物,且亦包含未來待開發的等效物,亦即,發明以進行相同功能的所有元件,無論其結構如何。舉例而言,只要本發明可應用於通道層、犧牲層、犧牲隔離層及通道隔離層,本文中所描述的通道層、犧牲層、犧牲隔離層及通道隔離層就可呈不同類型或形式。
應理解,當將半導體元件的元件、組件、層、圖案、結構、區域等(在下文中統稱為「元件」)稱為「在」半導體元件的另一元件「之上」、「上方」、「上」、「下方」、「下」、「底下」、「連接至」或「耦接至」所述另一元件時,其可直接「在」所述另一元件「之上」、「上方」、「上」、「下方」、「下」、「底下」、「連接至」或「耦接至」所述另一元件,或可存在插入元件。相反,當將半導體元件的元件稱為「直接在」半導體元件的另一元件「之上」、「直接在」所述另一元件「上方」、「直接在」所述另一元件「上」、「直接在」所述另一元件「下方」、「直接在」所述另一元件「下」、「直接在」所述另一元件「底下」、「直接連接至」或「直接耦接至」所述半導體元件的另一元件時,不存在插入元件。貫穿本揭露內容,相似編號指代相似元件。
為易於描述,本文中可使用空間相對術語,諸如「在……之上」、「在……上方」、「在……上」、「較高」、「在……下方」、「在……下」、「在……底下」、「較低」以及類似術語以描述如圖式中所示出的一個元件與另一元件的關係。應理解,除了圖中所描繪的定向之外,此類空間相對術語意欲涵蓋半導體元件在使用或操作中的不同定向。舉例而言,若翻轉圖式中的半導體元件,則描述為「在」其他元件「下方」或「在」其他元件「底下」的元件將隨後定向「在」其他元件「上方」。因此,術語「下方」可涵蓋在……上方及在……下方的定向兩者。半導體元件可以其他方式定向(旋轉90度或處於其他定向),且本文中所使用的空間相對描述詞相應地進行解釋。
如本文中所使用,諸如「……中的至少一者」的表述在位於元件清單之前時修飾整個元件清單,而並不修飾清單中的個別元件。舉例而言,表述「a、b以及c中的至少一者」應理解為包含僅a、僅b、僅c、a及b兩者、a及c兩者、b及c兩者,或a、b以及c中的所有者。在本文中,當術語「相同」用於比較兩個或多於兩個元件的尺寸時,所述術語可覆蓋「實質上相同」的尺寸。
應理解,儘管在本文中可使用術語第一、第二、第三、第四等來描述各種元件,但此等元件不應受限於此等術語。此等術語僅用以將一個元件與另一元件區分開來。因此,在不脫離本揭露內容的教示的情況下,下文所論述的第一元件可稱為第二元件。
亦應理解,即使製造設備或結構的某一步驟或操作比另一步驟或操作更晚描述,所述步驟或操作亦可比另一步驟或操作更晚執行,除非將所述另一步驟或操作描述為在所述步驟或操作之後執行。
本文參考為理想化實施例(及中間結構)的示意性說明的橫截面說明而描述實施例。因而,預期圖解說明的形狀因例如製造技術及/或公差有所變化。因此,實施例不應解釋為限於本文中所示出的區的特定形狀,而是包含由於(例如)製造造成的形狀偏差。舉例而言,示出為矩形的植入區將通常在其邊緣處具有圓形或曲線特徵及/或植入物濃度梯度,而非自植入區至非植入區的二元改變。同樣,由植入形成的內埋區可在內埋區與進行植入之表面之間的區域中產生某種植入。因此,諸圖中所示出的區在本質上為示意性的,且其形狀並不意欲示出元件區的實際形狀,且並不意欲限制本揭露的範疇。此外,在圖式中,出於清楚起見,可放大層及區的大小及相對大小。
出於簡潔起見,可或可不在本文中詳細描述包含奈米片電晶體的半導體元件的習知元件、結構或層。舉例而言,當此層或結構不與實施例的各種態樣相關時,本文中可省略半導體元件的某一隔離層或結構。
在下文中,應理解,術語「電晶體」可指包含基底上的閘極結構及源極/汲極區的半導體元件,且術語「電晶體結構」可指在形成閘極結構及源極/汲極區中的至少一者以使作為電晶體的半導體元件結構完整之前的中間半導體元件結構。
圖1A至圖1E示出根據實施例的包含閘極結構的多堆疊半導體元件,所述閘極結構具有保護閘極結構的較低功函數金屬層的內部間隔。
圖1E為多堆疊半導體元件10的俯視平面圖,出於簡潔目的,所述多堆疊半導體元件繪示通道結構及封閉通道結構的閘極結構而不繪示圖1A至圖1D中所示出的多個其他結構或元件。圖1A至圖1D為分別沿著圖1E中指示的線I-I'、線II-II'、線III-III'以及線IV-IV'截取的多堆疊半導體元件10的橫截面圖。
在本文中應理解,圖1E中所繪示的線I-I'及線II-II'指示多堆疊半導體元件10的通道長度方向,且圖1E中所繪示的線III-III'、線IV-IV'指示多堆疊半導體元件10的通道寬度方向。因此,圖1A至圖1B繪示由通道結構連接的通道結構及源極/汲極區的長度,且圖1C至圖1D繪示多堆疊半導體元件10中的通道結構及源極/汲極區的寬度。
參考圖1A至圖1C,多堆疊半導體元件10可包含形成於基底105上的較低奈米片電晶體10L及較高奈米片電晶體10U。基底105可為半導體材料的塊狀基底,例如矽或絕緣層上矽(silicon-on-insulator;SOI)基底。可圍繞基底105形成包含氮化矽或氧化矽的淺溝渠隔離(shallow trench isolation;STI)結構106以隔離多堆疊半導體元件10與包含多堆疊半導體元件10的積體電路中的另一多堆疊半導體元件或電路元件。
較低奈米片電晶體10L可包含作為多堆疊半導體元件10的較低通道結構110的多個較低通道層110C。較低通道層110C可為奈米片層,其在基底105上方豎直地堆疊且水平地彼此平行。較高奈米片電晶體10U亦可包含作為多堆疊半導體元件10的較高通道結構120的多個較高通道層120C。類似於較低通道層110C,較高通道層120C亦可為在較低通道層110C上方垂直地堆疊且水平地彼此平行的奈米片層。通道層110C及通道層120C可包含可自基底105磊晶生長的半導體材料,諸如矽。
參考圖1A、圖1B以及圖1C,較低源極/汲極區112可形成於包含較低通道層110C的較低通道結構110的在通道長度方向上的兩個末端上。較低源極/汲極區112亦可為自較低通道層110C及/或基底105生長的磊晶結構,且因此可包含較低通道層110C及基底105的相同材料或類似材料。較低通道層110C中的各者在其兩個末端處可連接至較低源極/汲極區112。類似地,較高源極/汲極區122可形成於包含較高通道層120C的較高通道結構的在通道長度方向上的兩個末端上。較高源極/汲極區122可為自較高通道層120C生長的磊晶結構,且因此可包含較低通道層110C的相同材料或類似材料。較高通道層120C中的各者在其兩個末端處可連接至較高源極/汲極區122。
取決於由較低源極/汲極區112或較高源極/汲極區122形成的場效電晶體的類型,較低源極/汲極區112及較高源極/汲極區122可摻雜有p型摻雜劑或n型摻雜劑。舉例而言,較低源極/汲極區112可摻雜有或植入有諸如砷或磷的n型摻雜劑以形成作為n型場效電晶體的較低奈米片電晶體10L,且較高源極/汲極區122可摻雜有或植入有諸如硼的p型摻雜劑以形成作為p型場效電晶體的較高奈米片電晶體10U。然而,實施例不限於此。較低源極/汲極區112可包含p型摻雜劑,而較高源極/汲極區122包含n型摻雜劑。此外,較低源極/汲極區112及較高源極/汲極區122可全部包含p型摻雜劑或n型摻雜劑。
如圖1A中所繪示,層間介電(interlayer dielectric;ILD)結構160可在較低通道結構110及較低源極/汲極區112分別由較高通道結構120及較高源極/汲極區122豎直地重疊的區(下文「重疊區」)處形成於較高源極/汲極區122上方及較高源極/汲極區122與較低源極/汲極區112之間。如圖1B中所繪示,重疊區包含多堆疊半導體元件(圖1A)沿著圖1E中所繪示的線I-I'的橫截面。ILD結構160亦可在下較低通道結構110及較低源極/汲極區112不分別由較高通道結構120及較高源極/汲極區122豎直地重疊的區(下文「非重疊區」)處形成於較低源極/汲極區112上方。非重疊區包含多堆疊半導體元件(圖1B)沿著圖1E中所繪示的線II-II'的橫截面。ILD結構可將較低源極/汲極區112與較高源極/汲極區122隔離,且亦可將較低源極/汲極區112及較高源極/汲極區122與多堆疊半導體元件10中的其他電路元件隔離。
圖1D繪示較高源極/汲極區122在通道寬度方向上可具有比較低源極/汲極區112更小的寬度。此是因為較高源極/汲極區122自包含較高通道層120C的較高通道結構120生長,所述較高通道層具有比包含較低通道層110C的較低通道結構110更小的寬度,如圖1C中所繪示。歸因於此通道寬度差異,較低通道結構110的一部分可不由較高通道結構120豎直地重疊,如圖1C中所繪示。
多堆疊半導體元件10可具有此通道寬度差異以實現較低源極/汲極區接觸結構(未繪示),所述較低源極/汲極區接觸結構自多堆疊半導體元件上方的後段製程(back-end-of-line;BEOL)結構(未繪示)向下延伸以落在圖1D中所繪示的較低源極/汲極區112的頂部表面上。否則,當較低通道結構110及較高通道結構120具有相等通道寬度時,較低源極/汲極區112及較高源極/汲極區122可具有相等寬度,且隨後,較低源極/汲極區接觸結構可必須彎曲且連接至較低源極/汲極區112的側表面,所述較低源極/汲極區的形成更困難且易於出錯。
相反,較高通道結構120可具有比較低通道結構110更多的通道層數目。舉例而言,較高通道層120C的數目為三(3),而較低通道層110C的數目為二(2),但此等數目不限於此。因此,雖然通道寬度出於以上原因而區分,但較低奈米片電晶體10L及較高奈米片電晶體10U可具有不同數目個通道層,使得多堆疊半導體元件在較低奈米片電晶體10L及較高奈米片電晶體10U中可具有相等有效通道寬度(W
eff)。
雖然較低源極/汲極區112連接至較低通道結構110,但所述較低源極/汲極區可由較低內部間隔117與較低閘極結構115隔離,如圖1A中所繪示。類似地,連接至較高通道結構120的較高源極/汲極區122可由較高內部間隔127與較高閘極結構125隔離,亦如圖1A中所繪示的。較低內部間隔117及較高內部間隔127可由包含氮化矽、氧化矽、氮氧化矽、碳氧化矽、碳氮化矽硼、氧碳氮化矽等的一或多種材料形成,但不限於此。
參考圖1A至圖1C,包含較低通道層110C的較低通道結構110可由較低閘極結構115圍繞,所述較低閘極結構包含較低閘極介電層115D、形成於較低閘極介電層115D上的較低功函數金屬層115F以及形成於較低功函數金屬層115F上的較低閘極金屬圖案115M。包含較高通道層120C的較高通道結構120可由較高閘極結構125圍繞,所述較高閘極結構包含較高閘極介電層125D、形成於較高閘極介電層125D上的較高功函數金屬層125F以及形成於較高功函數金屬層125F上的較高閘極金屬圖案125M。
較低閘極介電層115D及較高閘極介電層125D可各自包含介面層及高k層。可提供介面層以保護通道層110C及通道層120C,促進其上高k層的生長,且為通道層110C及通道層120C提供必要特徵介面。介面層可由氧化矽、氮氧化矽形成,但不限於此。可提供高k層以實現在通道層110C及通道層120C處無相關聯電流洩漏的情況下增加閘極電容。高κ層可由以下一或多種材料形成:氧化鉿(HfO
2)、矽酸鉿(HfSiO)、氮氧化鉿(HfON)、氮氧化鉿矽(HfSiON)、氧化鉿鋁(HfAlO
3)、氧化鑭(LaO)、氧化鑭鋁(LaAlO)、氧化鋯(ZrO)、矽酸鋯(ZrSiO)、氮氧化鋯(ZrON)、氮氧化鋯矽(ZrSiON)、氧化鈦(TiO
2)、氧化鋇鍶鈦(BaSrTiO)、氧化鋇鈦(BaTiO)、氧化鍶鈦(SrTiO)、氧化釔(YO)、氧化鋁(Al
2O
3)、氧化鉭(Ta
2O
3)以及氧化鉛鈧鉭(PbScTaO),但不限於此。
根據實施例,較低閘極介電層115D及較高閘極介電125D可在製造多堆疊半導體元件10中的同一時間形成,且因此可在多堆疊半導體元件10的通道長度方向上及通道寬度方向上的側處彼此連接,以形成一個單個閘極介電層,如圖1A的右側及圖1B至圖1C的左側中所繪示。
控制較低閘極結構115及較高閘極結構125的各別臨限電壓的較低功函數金屬層115F及較高功函數金屬層125F可各自由鈦、鉭(Ta)或其等化合物形成,所述化合物諸如:TiN、TiAl、TiAlN、TaN、TiC、TaC、TiAlC、TaCN、TaSiN,但不限於此。然而,當較低奈米片電晶體10L及較高奈米片電晶體10U將分別形成n型場效電晶體及p型場效電晶體時,較低功函數金屬層115F及較高功函數金屬層125F可由不同材料或材料化合物形成以控制較低閘極結構115及較高閘極結構125以具有不同臨限電壓。舉例而言,為了形成n型較低奈米片電晶體,TiN與TiC的組合可包含於較低功函數金屬層115F中,而無TiC或無碳的TiN可包含於較高功函數金屬層125F中以形成p型較高奈米片電晶體。然而,實施例不限於此。較低功函數金屬層115F可用於p型奈米片電晶體,而較高功函數金屬層125F可用於n型奈米片電晶體,或較低功函數金屬層115F及較高功函數金屬層125F兩者可為n型奈米片電晶體及p型奈米片電晶體中的一者。
較低閘極金屬圖案115M及較高閘極金屬圖案125M可各自包含鎢(W)、釕(Ru)、鉬(Mo)、鈷(Co)、鋁(Al)、銅(Cu)或其等化合物(但不限於此)以接收用於多堆疊半導體元件10或用於多堆疊半導體元件10至積體電路中的鄰近電路的內部路由的輸入電壓,所述積體電路包含多堆疊半導體元件10。根據實施例,較低閘極金屬圖案115M及較高閘極金屬圖案125M可藉由其間的較高功函數金屬層彼此連接,如圖1C中所繪示。
在下文中,描述根據實施例的多堆疊半導體元件10的較低閘極結構115及較高閘極結構125的結構性特徵。
參考圖1A,其上具有圍繞較低通道層110C的較低功函數金屬層115F的較低閘極介電層115D可在如上文所定義的重疊區處連接至其上具有圍繞較高通道層120C的較高功函數金屬層125F的較高閘極介電層125D。在此區處,其上具有較高功函數金屬層125F的較高閘極介電層125D可沿著較高源極/汲極區122上的ILD結構160的側壁進一步向上延伸至ILD結構160的頂部表面的層級,且亦可形成於ILD結構160的頂部表面上。
參考圖1A至圖1B,在如上文所定義的重疊區及非重疊區兩者處,較低閘極介電層115D亦可在其上具有較低功函數金屬層115F的較低通道結構110的下方形成於基底105上,且可橫向向外延伸至通道長度方向上的第一隔離結構150-1。第一隔離結構150-1可為在包含多堆疊半導體元件10的積體電路中將較低源極/汲極區112及較高源極/汲極區122與其他源極/汲極區隔離的擴散中斷結構。第一隔離結構150-1可包含氧化矽或氮化矽,但不限於此。其上具有較低功函數金屬層115F的橫向地延伸的較低閘極介電層115D可在第一隔離結構150-1的較低側壁上進一步向上延伸。
圖1A進一步繪示在重疊區處,第一隔離結構150-1的較低側壁上的較低閘極介電層115D及較低功函數金屬層115F可分別連接至在較低閘極金屬圖案115M的頂部表面的層級處形成於第一隔離結構150-1的較高側壁上的較高閘極介電層125D及較高功函數金屬層125F。在此區處,第一隔離結構150-1的較高側壁上的較高閘極介電層125D及較高功函數金屬層125F可向上延伸至第一隔離結構150-1的頂部表面的層級,且亦可形成於第一隔離結構150-1的頂部表面上。
然而,圖1B繪示,在非重疊區處,在第一隔離結構150-1的側壁上,較低閘極介電層115D可連接至較高閘極介電層125D,而較低功函數金屬層115F可不連接至較高功函數金屬層125F。在此非重疊區處,第一隔離結構150-1的較高側壁上的較高閘極介電層125D及較高功函數金屬層125F可向上延伸至第一隔離結構150-1的頂部表面的層級,且亦可形成於第一隔離結構150-1的頂部表面上。
圖1B進一步繪示在此非重疊區處,圍繞較低通道層110C的較低閘極介電層115D可連接至形成於較低源極/汲極區112上的ILD結構160的側壁上的較高閘極介電層125D,而較低功函數金屬層115F可不連接至較高功函數金屬層125F。此是因為,如稍後將描述,其中可包含替換金屬閘極(RMG)內部間隔200的第一凹槽G1至第六凹槽G6可形成於在此非重疊區處的較低閘極金屬圖案115M的頂部表面的層級下方的較低功函數金屬層115F上。第一凹槽G1至第六凹槽G6中的RMG內部間隔200的頂部表面可與較低閘極金屬圖案115M的頂部表面共面。其中具有RMG內部間隔200的第一凹槽G1至第六凹槽G6可在通道寬度方向上沿著第一隔離結構150-1延伸。在此區處,ILD結構160的側壁上的較高閘極介電層125D及較高功函數金屬層125F可向上延伸至ILD結構160的頂部表面的層級,且亦可形成於ILD結構160的頂部表面上。
圖1C繪示基底105上的其上具有較低功函數金屬層115F的較低通道結構110下方的較低閘極介電層115D可在通道寬度方向上橫向向外延伸至第二隔離結構150-2。第二隔離結構150-2可為在通道寬度方向上將較低閘極結構115及較高閘極結構125與其他閘極結構隔離的閘極切割隔離結構。第二隔離結構150-2可包含氧化矽或氮化矽,但不限於此。基底105上的較低通道結構110下的其上具有較低功函數金屬層115F的橫向地延伸的較低閘極介電層115D可進一步在第二隔離結構150-2的較低側壁上向上延伸。
圖1C繪示,在第二隔離結構150-2的側壁上,較低閘極介電層115D可連接至較高閘極介電層125D,而較低功函數金屬層115F可不連接至較高功函數金屬層125F。此是因為第七凹槽G7至第八凹槽G8(其亦可包含其中的RMG內部間隔200)可在此非重疊區處形成於較低閘極金屬圖案115M的頂部表面的層級下方的較低功函數金屬層115F上。如同第一凹槽G1至第六凹槽G6中的RMG內部間隔200,第七凹槽G7至第八凹槽G8中的RMG內部間隔200可具有可與較低閘極金屬圖案115M的頂部表面共面的頂部表面。
第七凹槽及第八凹槽可分別形成於較低閘極金屬圖案115M的在通道寬度方向上彼此相對的兩側處。其中具有RMG內部間隔200的第七凹槽G7及第八凹槽G8可在通道長度方向上沿著第二隔離結構150-2延伸。在第七凹槽G7及第八凹槽G8當中,第八凹槽G8可連接至在通道寬度方向上延伸的第三凹槽G3及第四凹槽G4,且因此其中的RMG內部間隔200亦可彼此連接。
此處,第二隔離結構150-2的較高側壁上的較高閘極介電層125D及較高功函數金屬層125F可向上延伸至第二隔離結構150-2的頂部表面的層級,且亦可形成於第二隔離結構150-2的頂部表面上。
根據實施例,當較低通道結構110及較高通道結構120具有相等通道寬度時,且因此多堆疊半導體元件10中可不存在非重疊區,第一凹槽G1至第六凹槽G6可不形成於多堆疊半導體元件10中,而第七凹槽及第八可仍形成於圖1C中所繪示的相同位置處。
包含於第一凹槽G1至第八凹槽G8中的RMG內部間隔200可用於保護在多堆疊半導體元件10中形成較高功函數金屬層125F並剩餘其中的步驟中的較低功函數金屬層115F,如將參考圖3A至圖3D以及圖7A至圖7D進一步描述。類似於較低內部間隔117及較高內部間隔127,RMG內部間隔200可由包含氮化矽、氧化矽、氮氧化矽、碳氧化矽、碳氮化矽硼、氧碳氮化矽等的一或多種材料形成,但不限於此。
參考圖1A至圖1C,較低閘極金屬圖案115M可在圍繞較低閘極介電層115D的較低功函數金屬層115F上圖案化以形成多堆疊半導體元件10的較低閘極結構115。較低閘極金屬圖案115M可覆蓋較低功函數金屬層115F的頂部表面及側表面,如圖1C中所繪示。因此,如圖1C中所繪示,基底105上的較低通道結構110下方的較低閘極介電層115D及其上的較低功函數金屬層115F可在通道寬度方向上向外延伸至較低閘極金屬圖案115M下的第二隔離結構150-2。然而,至少因為空間限制,較低閘極金屬圖案115M可不形成於較低通道結構110下方及較低通道層110C之間,而較低閘極介電層115D及其上的較低功函數金屬層115F可形成於較低通道層中。
圖1C進一步繪示在第二隔離結構150-2的較低側壁上的第七凹槽G7及第八凹槽G8中的各者中的較低閘極介電層115D、較低功函數金屬層115F以及RMG內部間隔200可橫向插入於較低閘極金屬圖案115M與第二隔離結構150-2的較低側壁之間。
返回參考圖1B,較低閘極金屬圖案115M亦可形成於其中具有RMG內部間隔200的鄰近第一凹槽與第二凹槽之間、其中具有RMG內部間隔200的鄰近第三凹槽與第四凹槽之間以及其中具有RMG內部間隔200的鄰近第五凹槽與第六凹槽之間。此是因為,如將參考圖3A至圖3D以及圖7A至圖7D進一步描述,歸因於較低功函數金屬層115F與較低閘極金屬圖案115M之間的蝕刻比率差異,第一凹槽至第六凹槽在非重疊區處在較低功函數金屬層115F上方的此等位置處形成於較低閘極金屬圖案115M的兩側處。
返回參考圖1A及圖1C,形成於較高通道結構120下方的較高功函數金屬層125F可橫向向外延伸以連接至第一隔離結構150-1及第二隔離結構150-2的較高側壁上的較高功函數金屬層125F。較高功函數金屬層125F的此橫向延伸部分可藉由在非重疊區處安置於較低閘極金屬圖案與較高閘極金屬圖案之間(如圖1C中所繪示)將較低閘極金屬圖案115M與較高閘極金屬圖案125M分離。然而,較高功函數金屬層125F的橫向延伸部分並不使較高閘極金屬圖案125M與較低閘極金屬圖案115M彼此隔離,且因此較高閘極結構125及較低閘極結構115可仍共用相同閘極輸入信號以形成作為CMOS元件的多堆疊半導體元件10。
至少因為空間限制,較高閘極金屬圖案125M可不形成於較高通道層120C之間,而較高閘極介電層125D及其上的較高功函數金屬層125F可形成於較高通道層中。
因此,根據上述實施例,圖1A至圖1E所繪示的多堆疊半導體元件10可由較低奈米片電晶體10L及較高奈米片電晶體10U形成,其中RMG內部間隔200在選定區處形成於各別閘極結構115及閘極結構124的較低功函數金屬層115F與較高功函數金屬層125F之間。
下文,根據實施例,將描述圖1A至圖1E中所繪示的一種製造對應於多堆疊半導體元件10的多堆疊半導體元件的方法。
圖2示出根據實施例的一種製造包含閘極結構的多堆疊半導體元件的方法的流程圖,所述閘極結構具有保護閘極結構的較低功函數金屬層的內部間隔。圖3A至圖3D以及圖7A至圖7D示出根據實施例的在製造多堆疊半導體元件的方法的各別步驟之後的中間多堆疊半導體元件。
圖3A至圖3D以及圖7A至圖7D中所繪示的中間多堆疊半導體元件可與圖1A至圖1E中所繪示的多堆疊半導體元件10相同或對應。因此,關於包含於中間多堆疊半導體元件中的結構或元件的材料及功能的描述可在其重複時在下文省略。當參考相同結構或元件時,可在下文使用用於描述圖1A至圖1E中的多堆疊半導體元件10的相同參考標號及參考字符。
在操作S10(圖2)中,為較低場效電晶體及較高場效電晶體提供可包含由閘極結構圍繞的較低通道結構及較高通道結構的中間多堆疊半導體元件,所述閘極結構包含第一閘極介電層、第一功函數金屬層以及第一閘極金屬圖案。
參考圖3A至圖3D,包含由第一閘極結構圍繞的較低通道結構110及較高通道結構120的中間多堆疊半導體元件10'可設置於基底105上,所述第一閘極結構包含較低閘極結構115'及較高閘極結構125'。較低通道結構110及較高通道結構120中的各者可由作為通道層的多個奈米片層形成。
圖3C至圖3D繪示,在中間多堆疊半導體元件10'中,較高通道結構120可具有比較低通道結構110更小的通道寬度。因此,自較高通道結構120生長的較高源極/汲極區122可具有比自較低通道結構110生長的較低源極/汲極區112更小的寬度。可提供此通道寬度差及源極/汲極區寬度差以促進較低源極/汲極區112的頂部表面上的源極/汲極接觸結構的連接,如上文參考圖1A至圖1E所描述。
圖3A至圖3C繪示中間多堆疊半導體元件10'的閘極結構可包含第一閘極介電層115D'、第一功函數金屬層115F'以及第一閘極金屬圖案115M'。其上具有第一功函數金屬層115F'的第一閘極介電層115D'可圍繞較低通道結構110及較高通道結構120的較低通道層及較高通道層兩者。第一閘極金屬圖案115M'可經圖案化以圍繞第一功函數金屬層115F'。
第一閘極介電層115D'及第一功函數金屬層115F'亦可形成於較低通道結構110下方,且在基底105上橫向地延伸至第一隔離結構150-1及第二隔離結構150-2。橫向延伸的第一閘極介電層115D'及第一功函數金屬層115F'亦可沿著兩個隔離結構150-1及隔離結構150-2的側壁向上延伸至所述隔離結構的頂部表面的層級,且亦可形成於所述頂部表面上。第一閘極介電層115D'及第一功函數金屬層115F'亦可沿著ILD結構160的側壁形成至所述ILD結構的頂部表面的層級,且亦可形成於所述頂部表面上。
在操作S20中(圖2),除形成於較高通道結構的較高通道層之間的第一功函數金屬層外,將第一閘極金屬圖案及第一功函數金屬層向下移除至較低通道結構與較高通道結構之間的層級,使得多個凹槽在選定區處形成於層級下方的第一功函數金屬層上的第一閘極金屬圖案的側處。
參考圖4A至圖4D,第一閘極金屬圖案115M'及第一功函數金屬層115F'可自較高通道結構120向下移除至除形成於較高通道結構120的較高通道層之間的第一功函數金屬層115F'外的較低通道結構110與較高通道結構120之間的層級。
此步驟中的移除操作可經由例如微影及乾式蝕刻(諸如反應性離子蝕刻(reactive ion etching;RIE))執行,以將第一閘極金屬圖案115M'及第一功函數金屬層115F'選擇性地移除至較低通道結構110與較高通道結構120之間的層級而不影響包含第一閘極介電層115D'的其他半導體元件。舉例而言,與氧氣混合的氟化氣體電漿可用於RIE蝕刻劑,但不限於此。儘管未繪示,但其上具有罩幕圖案的較高通道結構120可用作用於微影及乾式蝕刻操作的罩幕結構。因此,在此步驟中的移除操作之後,圍繞較高通道結構120的第一閘極介電層115D'可剩餘於中間多堆疊半導體元件10'中。歸因於乾式蝕刻,形成於較高通道結構120的較高通道層之間的第一功函數金屬層115'亦可剩餘於中間多堆疊半導體元件10'中。
此外,當在此步驟中應用具有比形成第一閘極金屬圖案115M'的材料更高的蝕刻速率的形成第一功函數金屬層115F'的材料的反應性離子蝕刻(RIE)時,第一閘極金屬圖案115M'可比第一功函數金屬層115F'進一步向下蝕刻。因此,包含第一凹槽G1至第八凹槽G8的多個凹槽可形成於剩餘於較低通道結構110與較高通道結構120之間的層級處或下方的第一閘極金屬圖案115M'的側處。凹槽可形成於在剩餘第一閘極金屬圖案115M'的頂部表面下方的剩餘第一功函數金屬層115F'上,且因此,凹槽的底部可為在彼位置處的剩餘第一功函數金屬層115F'的頂部表面。凹槽的高度可對應於第一閘極金屬圖案115M'的材料與第一功函數金屬層115F'的材料之間的蝕刻比率差。舉例而言,第一閘極金屬圖案115M'可包含鎢(W)、釕(Ru)、鉬(Mo)、鈷(Co)、鋁(Al)、銅(Cu)或其等化合物,且第一功函數金屬層115F'可包含鈦、鉭(Ta)或其等化合物,諸如TiN、TiAl、TiAlN、TaN、TiC、TaC、TiAlC、TaCN、TaSiN,但不限於此。
此處,第一凹槽G1至第六凹槽G6可形成於在如上文參考圖1A至圖1E所描述的非重疊區處的乾式蝕刻之後剩餘的第一功函數金屬層115F'上。第一凹槽G1至第六凹槽G6中的各者可藉由在乾式蝕刻之後剩餘的第一閘極金屬圖案115M'的一部分在通道寬度方向上延伸。第一閘極金屬圖案115M'的剩餘部分亦可在通道寬度方向上延伸。此外,可在通道長度方向上延伸的第七凹槽及第八凹槽可形成於剩餘第一閘極金屬圖案115M'與第二隔離結構150-2之間的剩餘第一功函數金屬層115F'上。
在第一凹槽G1至第八凹槽G8中,歸因於如上文所論述的較低通道結構110與較高通道結構120之間的通道寬度差,可形成第一凹槽G1至第六凹槽G6。因此,當較低通道結構110及較高通道結構120具有相等通道寬度時,且因此中間多堆疊半導體元件10'不具有非重疊區,第一凹槽G1至第六凹槽G6可不藉由此步驟中的微影及乾式蝕刻操作形成,而第七凹槽及第八可仍形成於圖4C中所繪示的相同位置處。
在操作S30中(圖2),RMG內部間隔可形成於凹槽中,且較高通道層之間的第一功函數金屬層可移除,同時內部間隔保護其下方的第一功函數金屬層。
參考圖5A至圖5D,RMG內部間隔200可形成於包含第一凹槽G1至第八凹槽G8的凹槽中,且先前步驟中的乾式蝕刻之後的較高通道結構120的較高通道層120C之間剩餘的第一功函數金屬層115F'可移除,同時內部間隔200保護其下方的第一功函數金屬層115F'。
RMG內部間隔200可經由(例如)諸如原子層沈積(atomic layer deposition;ALD)的薄膜沈積技術形成於凹槽中。RMG內部間隔200可包含氮化矽、氧化矽、氮氧化矽、碳氧化矽、碳氮化矽硼、氧碳氮化矽等的一或多種材料,但不限於此。儘管圖中未繪示,但RMG內部間隔200可藉由將上述內部間隔材料沈積於經由ALD暴露凹槽的中間多堆疊半導體元件10'上,且經由例如使用氫氟酸(HF)或氫氟酸與硝酸的混合物作為濕式蝕刻劑的濕式蝕刻夾斷形成於凹槽中的內部間隔材料而形成,但不限於此。此濕式蝕刻可選擇性地蝕刻形成RMG內部間隔200的材料。經由此沈積及蝕刻操作,可夾斷RMG內部間隔200以剩餘於凹槽中。由於夾斷RMG內部間隔200,因此凹槽中的RMG內部間隔200的頂部表面可與剩餘第一閘極金屬圖案115M'的頂部表面共平面。
雖然形成於非重疊區中的凹槽中的RMG內部間隔200覆蓋或保護其下的第一功函數金屬層115F',可經由(例如)使用包含(但不限於)過氧化氫的濕式蝕刻劑的濕式蝕刻來移除先前乾式蝕刻操作之後的較高通道結構120的較高通道層120C之間剩餘的第一功函數金屬層115F',所述濕蝕刻劑可選擇性地攻擊形成第一功函數金屬層115F'的材料(諸如TiN或TiC)而與形成第一閘極金屬圖案115M'的材料(諸如鎢(W))相抵。
除非形成凹槽且RMG內部間隔200形成於所述凹槽中,否則可存在風險:剩餘在較高通道層120C之間的用於移除第一功函數金屬層115F'的濕式蝕刻劑亦可攻擊圍繞較低通道結構110的較低閘極結構115'的第一功函數金屬層115F'。換言之,藉由在其中形成凹槽及RMG內部間隔200,當在此步驟中移除較高通道層120C之間剩餘的第一功函數金屬層115F'時,較低閘極結構115'的第一功函數金屬層115F'可被保護。
在操作中S40(圖2),不同於第一功函數金屬層,第二功函數金屬層可形成於圍繞較高通道結構的第一閘極介電層上且第一閘極金屬圖案剩餘在層級下方。
參考圖6A至圖6D,第二功函數金屬層125F'可形成於先前步驟中獲得的中間多堆疊半導體元件10'上,所述中間多堆疊半導體元件暴露剩餘第一閘極金屬圖案115M'的頂部表面、由第一閘極介電層115D'圍繞的較高通道結構120以及填充第一凹槽G1至第八凹槽G8的RMG內部間隔200。
可具有與第一功函數金屬層115F'不同的材料或材料化合物的第二功函數金屬層125F'可經由例如原子層沈積(ALD)形成,但不限於此。舉例而言,第二功函數金屬層125F'可包含TiN及TIC的組合以形成n型閘極結構,且第一功函數金屬層115F'可包含TiN而無TiC或無碳以形成p型閘極結構,或反之亦然。
第二功函數金屬層125F'可不僅形成於圍繞較高通道結構120的較高通道層120C的第一閘極介電層115D'上,且還形成於剩餘第一閘極金屬圖案115M'、第一凹槽G1至第八凹槽G8中的RMG內部間隔200、形成且曝露於第一隔離結構150-1、第二隔離結構150-2以及ILD結構160的側壁及頂部表面上的第一閘極介電層115D'上。
形成於剩餘第一閘極金屬圖案115M'上的第二功函數金屬層125F'可橫向地延伸以連接至形成於第二隔離結構150-2的側壁上的第一閘極介電層115D'上的第二功函數金屬層125F'。
在操作S50中(圖2),可形成第二閘極金屬圖案以圍繞第二功函數金屬層以獲得多堆疊半導體元件,所述多堆疊半導體元件中較低奈米片電晶體及較高奈米片電晶體分別具有不同的第一功函數金屬層及第二功函數金屬層。
參考圖7A至圖7D,第二閘極金屬圖案125M'可形成於先前步驟中形成的第二功函數金屬層125F'上,且經平坦化以修整較高閘極結構125。第二閘極金屬圖案125M'的形成可經由(例如)物理氣相沈積(physical vapor deposition;PVD)、化學氣相沈積(chemical vapor deposition;CVD)、電漿增強式化學氣相沈積(plasma enhanced chemical vapor deposition;PECVD)或其組合執行,但不限於此。平坦化可經由(例如)化學機械平坦化(chemical mechanical planarization;CMP)技術執行,但不限於此,使得第二閘極金屬圖案125M'的頂部表面可與形成於第一隔離結構150-1、第二隔離結構150-2以及ILD結構160的頂部表面上的第二功函數金屬層125F'共面。
第二閘極金屬圖案125M'可經由第二功函數金屬層125F'連接至剩餘第一閘極金屬圖案115M',所述第二功函數金屬層橫向地延伸以連接至先前步驟中的第二隔離結構150-2的側壁上的第一閘極介電115D'上的第二功函數金屬層125F'。
包含在剩餘第一閘極金屬圖案115M'的頂部表面下方的第一閘極介電層115D'、第一功函數金屬層115F'以及剩餘閘極金屬圖案115M'的較低閘極結構115'可為或對應於圖1A至圖1D中所繪示的包含第一閘極介電層115D、第一功函數金屬層115F以及剩餘閘極金屬圖案115M的較低閘極結構115。包含在剩餘第一閘極金屬圖案115M'的頂部表面上方的第一閘極介電層115D'、第二功函數金屬層125F'以及第二閘極金屬圖案125M'的較高閘極結構125'可為或對應於包含較高閘極介電層125D、較高功函數金屬層125F以及較高閘極金屬圖案125M的較高閘極結構125。因此,圖7A至圖7D中所繪示的中間多堆疊半導體元件10'可為或對應於圖1A至圖1E中所繪示的多堆疊半導體元件10。
圖7A至圖7D中所繪示的中間多堆疊半導體元件10'可仍包含凹槽中的RMG內部間隔200,所述RMG內部間隔用於在移除由第一閘極介電層115D'圍繞的較高通道層120C之間的第一功函數金屬層115F'的步驟中保護第一閘極金屬圖案115M'的頂部表面下方的第一功函數金屬層115F',如上文所描述。
迄今為止,實施例已針對由較低奈米片電晶體及較高奈米片電晶體形成的多堆疊半導體元件。然而,本發明不限於此,且亦可應用於根據實施例的包含鰭式場效電晶體(fin field-effect transistors;FinFET)作為較低電晶體及較高電晶體的多堆疊半導體元件。在此情況下,根據實施例,此等FinFET中的各者可具有一或多個豎直地突出的鰭結構作為通道層(通道結構),所述通道層的頂部及側表面由具有保護較低閘極結構的較低功函數金屬層的內部間隔的閘極結構圍繞。此外,在此實施例中,較高FinFET可具有比較低FinFET更小的通道寬度。
本發明可進一步應用於混合式多堆疊半導體元件,所述混合式多堆疊半導體元件分別包含奈米片電晶體及FinFET作為較低電晶體及較高電晶體。在此情況下,較低奈米片電晶體可為或對應於上文所描述的多堆疊半導體元件10的較低奈米片電晶體10L,且FinFET的通道寬度可小於奈米片電晶體。
圖8為示出根據示例性實施例的包含多堆疊半導體元件的電子元件的示意性方塊圖,所述多堆疊半導體元件包含具有保護閘極結構的較低功函數金屬層的內部間隔的閘極結構。
參考圖8,電子元件4000可包含至少一個應用程式處理器4100、通信模組4200、顯示器/觸控模組4300、儲存元件4400以及緩衝器RAM 4500。根據實施例,電子元件4000可為諸如智慧型手機或平板電腦的行動裝置(mobile device),但不限於此。
應用處理器4100可控制電子元件4000的操作。通信模組4200實施為與外部裝置執行無線通信或有線通信。顯示/觸控模組4300實施為顯示由應用處理器4100處理的資料及/或經由觸控面板接收資料。儲存元件4400實施為儲存使用者資料。儲存元件4400可為嵌入多媒體卡(embedded multimedia card;eMMC)、固態硬碟(solid state drive;SSD)或通用快閃儲存器(universal flash storage;UFS)元件等。儲存元件4400可執行如上所述的映射資料及使用者資料的緩存。
緩衝RAM 4500可臨時儲存用於處理電子元件4000的操作的資料。舉例而言,緩衝RAM 4500可為揮發性記憶體,諸如雙資料速率(double data rate;DDR)同步動態隨機存取記憶體(synchronous dynamic random access memory;SDRAM)、低功率雙資料速率(low power double data rate;LPDDR)SDRAM、圖形雙資料速率(graphics double data rate;GDDR)SDRAM、蘭巴斯動態隨機存取記憶體(Rambus dynamic random access memory;RDRAM)、等。
電子元件4000中的至少一個組件可包含上文參考圖1A至圖1E以及圖7A至圖7D所描述的多堆疊半導體元件。
前述內容說明例示性實施例,且不應解釋為限制本發明。儘管已描述幾個例示性實施例,但所屬技術領域中具有通常知識者將易於瞭解,在不實質上脫離本發明的情況下,以上實施例中的許多修改為可能的。
10:多堆疊半導體元件
10':中間多堆疊半導體元件
10L:較低奈米片電晶體
10U:較高奈米片電晶體
105:基底
106:淺溝渠隔離結構
110:較低通道結構
110C:較低通道層
112:較低源汲/汲極區
115':閘極結構
115:較低閘極結構
115D:較低閘極介電層
115D':第一閘極介電層
115F:較低功函數金屬層
115F':第一功函數金屬層
115M:較低閘極金屬圖案
115M':第一閘極金屬圖案
117:較低內部間隔
120:較高通道結構
120C:較高通道層
122:較高源汲/汲極區
125:較高閘極結構
125':閘極結構的較高部分
125D:較高閘極介電層
125D':第二閘極介電層
125F:較高功函數金屬層
125F':第二功函數金屬層
125M:較高閘極金屬圖案
125M':第二閘極金屬圖案
127:較高內部間隔
150-1:第一隔離結構
150-2:第二隔離結構
160:層間介電結構
200:替換金屬閘極內部間隔
4000:電子元件
4100:應用程式處理器
4200:通信模組
4300:顯示器/觸控模組
4400:儲存元件
4500:緩衝RAM
G1:第一凹槽
G2:第二凹槽
G3:第三凹槽
G4:第四凹槽
G5:第五凹槽
G6:第六凹槽
G7:第七凹槽
G8:第八凹槽
I-I'、II-II'、III-III'、IV-IV':線
S10、S20、S30、S40、S50:操作
自結合隨附圖式進行的以下詳細描述將更清楚地理解本發明概念的示例性實施例,在隨附圖式中:
圖1A至圖1E示出根據實施例的包含閘極結構的多堆疊半導體元件,所述閘極結構具有保護閘極結構的較低功函數金屬層的內部間隔。
圖2示出根據實施例的一種製造包含閘極結構的多堆疊半導體元件的方法的流程圖,所述閘極結構具有保護閘極結構的較低功函數金屬層的內部間隔。
圖3A至圖3D至圖7A至圖7D示出根據實施例的在製造包含閘極結構的多堆疊半導體元件的方法的各別步驟之後的中間多堆疊半導體元件,所述閘極結構具有保護閘極結構的較低功函數金屬層的內部間隔。
圖8為示出根據示例性實施例的包含多堆疊半導體元件的電子元件的示意性方塊圖,所述多堆疊半導體元件包含具有保護閘極結構的較低功函數金屬層的內部間隔的閘極結構。
10:多堆疊半導體元件
10L:較低奈米片電晶體
10U:較高奈米片電晶體
105:基底
106:淺溝渠隔離結構
110:較低通道結構
110C:較低通道層
112:較低源汲/汲極區
115:
115D:較低閘極介電層
115F:較低功函數金屬層
115M:較低閘極金屬圖案
120:較高通道結構
120C:較高通道層
122:較高源汲/汲極區
125:較高閘極結構
125D:較高閘極介電層
125F:較高功函數金屬層
125M:較高閘極金屬圖案
127:較高內部間隔
150-1:第一隔離結構
160:層間介電結構
Claims (20)
- 一種多堆疊半導體元件,包括: 基底; 較低場效電晶體,其中較低通道結構由較低閘極結構圍繞,所述較低閘極結構包括較低閘極介電層、較低功函數金屬層以及較低閘極金屬圖案;以及 較高場效電晶體,其中較高通道結構由較高閘極結構圍繞,所述較高閘極結構包括較高閘極介電層、較高功函數金屬層以及較高閘極金屬圖案, 其中所述較高通道結構的通道寬度小於所述較低通道結構的通道寬度,以及 其中替換金屬閘極(RMG)內部間隔在所述較低通道結構並不由所述較高通道結構豎直地重疊的選定區處形成於所述較低功函數金屬層與所述較高功函數金屬層之間。
- 如請求項1所述的多堆疊半導體元件,其中所述RMG內部間隔形成於其上的所述較低功函數金屬層的頂部表面低於所述較低閘極金屬圖案的頂部表面的層級。
- 如請求項2所述的多堆疊半導體元件,其中所述RMG內部間隔的頂部表面與所述較低閘極金屬圖案的所述頂部表面共面。
- 如請求項1所述的多堆疊半導體元件,其中所述RMG內部間隔形成於多個凹槽中,以及 其中所述較低閘極金屬圖案的一部分形成於所述多個凹槽中的兩個鄰近凹槽之間。
- 如請求項4所述的多堆疊半導體元件,其中所述兩個鄰近凹槽在通道寬度方向上延伸。
- 如請求項4所述的多堆疊半導體元件,其中所述多個凹槽中的兩個凹槽分別形成於所述較低閘極金屬圖案的兩側處。
- 如請求項1所述的多堆疊半導體元件,其中所述較高功函數金屬層的一部分在所述較低通道結構上方側向延伸,其中所述較低通道結構並不由所述較高通道結構重疊。
- 如請求項7所述的多堆疊半導體元件,其中所述RMG內部間隔形成於所述較高功函數金屬層的所述側向延伸部分的層級下方。
- 如請求項8所述的多堆疊半導體元件,其中所述較高功函數金屬層的所述側向延伸部分插入於所述較低閘極金屬圖案與所述較高閘極金屬圖案之間。
- 如請求項1所述的多堆疊半導體元件,其中擴散中斷結構或閘極切割隔離結構形成於所述多堆疊半導體元件的一側處,且所述較低功函數金屬層的一部分及所述較高功函數金屬層的一部分沿著所述擴散中斷結構或所述閘極切割隔離結構的側壁形成,以及 其中所述RMG內部間隔沿著所述側壁形成於所述較低功函數金屬層的所述部分與所述較高功函數金屬層的所述部分之間。
- 如請求項1所述的多堆疊半導體元件,其中至少所述較低場效電晶體為奈米片電晶體,且所述較低通道結構包括豎直地堆疊於所述基底上的多個奈米片層。
- 如請求項11所述的多堆疊半導體元件,其中所述RMG內部間隔形成於其上的所述較低功函數金屬層的頂部表面低於所述較低閘極金屬圖案的頂部表面的層級。
- 一種多堆疊半導體元件,包括: 基底; 較低場效電晶體,其中較低通道結構由較低閘極結構圍繞,所述較低閘極結構包括較低閘極介電層、較低功函數金屬層以及較低閘極金屬圖案;以及 較高場效電晶體,其中較高通道結構由較高閘極結構圍繞,所述較高閘極結構包括較高閘極介電層、較高功函數金屬層以及較高閘極金屬圖案, 其中替換金屬閘極(RMG)內部間隔在通道寬度方向上在所述較低閘極金屬圖案的一側處形成於所述較低功函數金屬層與所述較高功函數金屬層之間。
- 如請求項13所述的多堆疊半導體元件,其中所述RMG內部間隔形成於其上的所述較低功函數金屬層的頂部表面低於所述較低閘極金屬圖案的頂部表面的層級。
- 如請求項14所述的多堆疊半導體元件,其中所述RMG內部間隔形成於其上的所述較低功函數金屬層的頂部表面低於所述較低閘極金屬圖案的頂部表面的層級。
- 如請求項15所述的多堆疊半導體元件,其中至少所述較低場效電晶體為奈米片電晶體,且所述較低通道結構包括豎直地堆疊於所述基底上的多個奈米片層。
- 如請求項13所述的多堆疊半導體元件,其中所述RMG內部間隔形成於凹槽中,所述凹槽在所述通道寬度方向上在所述較低閘極金屬圖案的所述側處形成於所述較低功函數金屬層上,且在通道長度方向上延伸。
- 一種製造多堆疊半導體元件的方法,所述方法包括: 為各別較低場效電晶體及較高場效電晶體提供由閘極結構圍繞的較低通道結構及較高通道結構,所述閘極結構包括第一功函數金屬層及第一閘極金屬圖案; 除形成於所述較高通道結構的較高通道層之間的所述第一功函數金屬層外,將所述第一閘極金屬圖案及所述第一功函數金屬層向下移除至所述較低通道結構與所述較高通道結構之間的層級,使得多個凹槽在選定區處形成於所述層級下方的所述第一功函數金屬層上的所述第一閘極金屬圖案的側處; 在所述多個凹槽中形成替換金屬閘極(RMG)內部間隔,且移除所述較高通道層之間的所述第一功函數金屬層; 將包括不同於所述第一功函數金屬層的材料的第二功函數金屬層形成於所述較高通道結構上且所述第一閘極金屬圖案剩餘在所述層級下方;以及 將第二閘極金屬圖案形成於所述第二功函數金屬層上。
- 如請求項18所述的製造多堆疊半導體元件的方法,其中所述多個凹槽形成於其上的所述第一功函數金屬層的所述頂部表面低於所述第一閘極金屬圖案的頂部表面的層級。
- 如請求項19所述的製造多堆疊半導體元件的方法,其中,在所述選定區處,所述較低通道結構並不由所述較高通道結構豎直地重疊。
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US17/891,777 US20230343845A1 (en) | 2022-04-26 | 2022-08-19 | 3d-stacked semiconductor device including gate structure with rmg inner spacer protecting lower work-function metal layer |
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