TW202345302A - 一種具絕緣板之整合封裝 - Google Patents

一種具絕緣板之整合封裝 Download PDF

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TW202345302A
TW202345302A TW111117656A TW111117656A TW202345302A TW 202345302 A TW202345302 A TW 202345302A TW 111117656 A TW111117656 A TW 111117656A TW 111117656 A TW111117656 A TW 111117656A TW 202345302 A TW202345302 A TW 202345302A
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circuit
insulating plate
electronic component
package
integrated package
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TW111117656A
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TWI817496B (zh
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林俊榮
古瑞庭
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華東科技股份有限公司
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Priority to TW111117656A priority Critical patent/TWI817496B/zh
Priority to US17/893,341 priority patent/US20230369190A1/en
Priority to CN202211099713.9A priority patent/CN117096109A/zh
Priority to KR1020230013988A priority patent/KR20230158389A/ko
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Publication of TWI817496B publication Critical patent/TWI817496B/zh
Publication of TW202345302A publication Critical patent/TW202345302A/zh

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Abstract

本發明揭示一種具絕緣板之整合封裝，其主要特徵係為以絕緣板結構取代傳統封裝堆疊結構內之複數印刷電路板及封裝材料，其具有一基礎基板、一基礎電路及至少一電子零件，該基礎電路顯露於該基礎基板之上表面，該電子零件與該基礎電路電性連接，由一第一絕緣板熱壓覆蓋該基礎基板及該電子零件。

Description

一種具絕緣板之整合封裝
本發明係關於一種堆疊結構封裝，特別由絕緣板結構取代傳統封裝堆疊結構內之複數印刷電路板，並可替代封裝材料結構位置。
隨著電子產品的功能越趨複雜，導致上游零件的晶粒須具備較多的輸出/輸入連接，配合的封裝跟著需在限制空間內引出更多的連接點，同時對很流行的堆疊式封裝(Package on Package，POP)應用產生挑戰，需在更小的空間內布置更多的輸出/輸入點。
當今在積體電路之封裝技術中，一般會先將積體電路晶粒囊封於囊封材料中，爾後利用基板上之電路增加更多空間以用於增設更多輸出/輸入點。
關於堆疊封裝之文獻，多個專利如下：
WO2017111789A1揭示一嵌入式晶圓級球閘陣列(Wafer-Level Ball Grid Array,Ewlb)或嵌入式面板級球閘陣列(Embedded Wafer Level Ball Grid Array,ePLB)為基礎之堆疊式封裝(Package on Package，POP)裝置及用以形成此等裝置之方法；根據一實施例，此一裝置係可包括一嵌入一模層內之晶粒；一基材可直接地接觸模層的一表面；此外，本發明的實施例係可包括一經過模層所形成之通模導孔，通模導孔係電氣地耦接至一形成於正與模層接觸之基材的一表面上之接觸件。為了 形成此一裝置，實施例係可包括將一模製材料施配於位在一模載體上的一晶粒上方。其後，一基材可被壓入模製材料中。在將模製材料固化之後，係可形成一模層，模層係包封晶粒且黏著至基材。
TW I754839揭示包括形成具有補強結構的中介層，所述補強結構設置於所述中介層的核心層中。所述中介層可透過導電連接件連接至封裝裝置。補強結構為封裝裝置提供剛性和散熱性能。一些實施例可包括中介層，所述中介層在其上部核心層中具有開口至凹陷接合墊。一些實施例也可利用中介層和封裝裝置之間的連接件，其中連接至中介層的軟焊材料圍繞著連接至封裝裝置的金屬柱。
TW I628742揭示一種堆疊式封裝結構，包含第一板狀結構與第二板狀結構。第一板狀結構具有相對之第一面與第二面。第一板狀結構包含第一介電層與第一電子元件。第一電子元件設置於第一介電層中，其中第一電子元件具有第一主動面，且第一主動面形成第二面的一部份。第二板狀結構具有相對之第三面與第四面。第三面面對第二面，且第三面固定於第二面。第二板狀結構包含第二介電層與至少一第二電子元件。第二電子元件設置於第二介電層中，其中第二電子元件具有第二主動面，且第二主動面形成第三面的一部份。
然而，隨著先進製程的演進堆疊的層數及功能性亦趨於複雜，封裝後的厚度及產品運行溫度問題一一被放大，且電子設備更新週期越顯頻繁，整體成本的控制面臨巨大壓力。
有鑑於以上問題，本發明提供一種具絕緣板之整合封裝，主 要使用絕緣板結構取代傳統封裝堆疊結構內之複數印刷電路板，以達成大幅降低堆疊結構成本之作用。
因此，本發明之主要目的係在提供一種具絕緣板之整合封裝，將絕緣板結構以熱壓覆蓋基礎基板及零組件，達成封裝之功能。
本發明再一目的係在提供一種具絕緣板之整合封裝，以絕緣板結構取代印刷電路板及封裝結構，可使整體封裝厚度變薄。
本發明再一目的係在提供一種具絕緣板之整合封裝，可使絕緣板具有預設電路用做電路導通，提供各層所需之電路導通。
本發明再一目的係在提供一種具絕緣板之整合封裝，增設銅層於絕緣板結構，可賦予防電磁干擾之功效。
本發明再一目的係在提供一種具絕緣板之整合封裝，增設銅層於絕緣板結構，能被動將堆疊結構中廢熱導出。
為達成上述目地，本發明所使用的主要技術手段是採用以下技術方案來實現的。本發明為一種具絕緣板之整合封裝，其包含：一基礎基板、一基礎電路及至少一電子零件，該基礎電路顯露於該基礎基板之上表面，該電子零件與該基礎電路電性連接；一第一絕緣板熱壓覆蓋該基礎基板及該電子零件。
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。
前述的封裝，其中該第一絕緣板之上表面包含一第一電路，該第一電路與另一電子零件電性連接。
前述的封裝，其中該基礎基板之下表面具有複數資訊連結腳 及至少一接地腳。
前述的封裝，其中該電子零件可為主動元件、被動元件或記憶體。
前述的封裝，其中該第一絕緣板該表面具有一第一銅層。
前述的封裝，其中一第一下層導電孔貫通該第一絕緣板，該第一下層導電孔填充一第一導電材料與該基礎電路電性導通。
前述的封裝，其中一第二絕緣板熱壓覆蓋該第一電路及該電子零件。
前述的封裝，其中該第二絕緣板之上表面包含一第二電路，該第二電路與另一電子零件電性連接。
前述的封裝，其中第二絕緣板該表面具有一第二銅層。
前述的封裝，其中一第二下層導電孔貫通該第二絕緣板，該第二下層導電孔填充一第二導電材料與該第一電路電性導通。
相較於習知技術，本發明具有功效在於：(1)利用絕緣板結構以熱壓覆蓋基礎基板及零組件，達成封裝之功能；(2)使用絕緣板結構取代印刷電路板及封裝結構，可以降低設置成本及整體厚度；(3)增設銅層於絕緣板結構，可以降低整體溫度及提高防電磁干擾。
10:基礎基板
101:上表面
102:下表面
102A:資訊連結腳
102B:接地腳
11:基礎電路
12:電子零件
12’:電子零件
12”:電子零件
13:第一導電材料
20:絕緣板
201:上表面
21:第一電路
22:第一銅層
23:第一下層導電孔
24:第二導電材料
30:第二絕緣板
31:第二電路
32:第二銅層
33:第二下層導電孔
〔圖1a〕係本發明第一實施型態之第一封裝示意圖。
〔圖1b〕係本發明第一實施型態之第二封裝示意圖。
〔圖2〕係本發明第二實施型態之封裝示意圖。
〔圖3a〕係本發明第三實施型態之第一封裝示意圖。
〔圖3b〕係本發明第三實施型態之第二封裝示意圖。
〔圖3c〕係本發明第三實施型態之第三封裝示意圖。
〔圖3d〕係本發明第四實施型態之第四封裝示意圖。
〔圖4〕係本發明第四實施型態之封裝示意圖。
為了讓本發明之目的、特徵與功效更明顯易懂，以下特別列舉本發明之較佳實施型態：
如圖1a及圖1b所示，為本發明一種具絕緣板之整合封裝之第一實施型態；請先參考第1a圖所示，一種具絕緣板之整合封裝，其包含：一基礎基板(10)、一基礎電路(11)及至少一電子零件(12)，該基礎電路(11)顯露於該基礎基板(10)之上表面(101)，該電子零件(12)與該基礎電路(11)電性連接；一第一絕緣板(20)熱壓覆蓋該基礎基板(10)及該電子零件(12)。
具體而言，該基礎基板(10)通常為一線路基板(circuit board)，例如，基板係為一具有單層或多層線路之印刷電路板，此外，亦可為一導線架、一電路薄膜(Polyimide)、BT電路板或各種晶片載板，而該基礎基板(10)內部形成基礎電路(11)，該基礎電路(11)顯露於該基礎基板(10)之上表面(101)，可作為電性傳遞介面；其中，該電子零件(12)可為主動元件、被動元件或記憶體，該電子零件(12)與該基礎電路(11)電性連接。
另，該第一絕緣板(20)係為玻璃布(Woven glass)、環氧 樹脂所構成之絕緣材料板，具備加熱軟化特質，因此可熱壓覆蓋該基礎基板(10)及該電子零件(12)，等待冷卻後再次硬化即可保護該基礎基板(10)及該電子零件(12)。
為方便後續工序，可參考圖1b所示，其中該基礎基板(10)之下表面(102)具有複數資訊連結腳(102A)及至少一接地腳(102B)；該些資訊連結腳(102A)功效為提供各類電子零件與外界的電性連接，而該接地腳(102B)係為在電路設計時之地線，地線則被廣泛作為電位的參考點，為整個電路提供一個基準電位，以地線上電壓為0V，以統一整個電路電位。
請再參照圖2所示，為本發明一種具絕緣板之整合封裝之第二實施型態；第二實施型態與第一實施型態的主要差異在於本實施型態於該第一絕緣板(20)該表面具有一第一銅層(22)。
實務來說，該第一銅層(22)係為該第一絕緣板(20)之表面金屬塗層，其具有可防止外部及上下層之間的電磁干擾，且該第一銅層(22)可將廢熱導出，減低封裝內的電子零件溫度過高。
請再參照圖3a、3b、3c表示，為本發明一種具絕緣板之整合封裝之第三實施型態；第三實施型態與第一實施型態的主要差異在於本實施型態之該第一絕緣板(20)之上表面(201)包含一第一電路(21)，該第一電路(21)與另一電子零件(12’)電性連接。
詳細來說，該第一絕緣板(20)係為玻璃布(Woven glass)、環氧樹脂所構成之絕緣材料板，具備加熱軟化特質，因此可熱壓覆蓋該基礎電路(11)及該電子零件(12)，等待冷卻後再次硬化即可保護該基礎電 路(11)及該電子零件(12)，該第一絕緣板(20)係為一具有單層(如圖3a表示)或多層線路之印刷電路板，而該第一絕緣板(20)內部形成第一電路(21)，該第一電路(21)顯露於該第一絕緣板(20)之上表面(201)，可作為電性傳遞介面；其中，該電子零件(12’)可為主動元件、被動元件或記憶體，該電子零件(12’)與該第一電路(21)電性連接。
另，如為電性導通基礎電路(11)與第一電路(21)兩者或電子零件(12,12’)，必須將一第一下層導電孔(23)貫通該第一絕緣板(20)，該第一下層導電孔(22)填充一第一導電材料(13)與該基礎電路(11)電性導通。
實際而言，第一下層導電孔(23)如圖3b呈現，由第一電路(21)開始貫通第一絕緣板(20)，使基礎電路(11)顯露於外；其中，該第一導電材料(13)係具備固定物件及導電特性之膠狀物，在質變後呈固化狀，並維持固定物件及導電特性。
較佳者，如圖3c所示，由一第二絕緣板(30)熱壓覆蓋該第一電路(21)及該電子零件(12’)。
其中，該第二絕緣板(30)係為玻璃布(Woven glass)、環氧樹脂所構成之絕緣材料板，具備加熱軟化特質，因此可熱壓覆蓋第一電路(21)及該電子零件(12’)，等待冷卻後再次硬化即可保護該第一電路(21)及該電子零件(12’)。
再，如圖3d所示，其中第二絕緣板(30)該表面具有一第二銅層(32)。
具體而言，該第二銅層(32)係為該第二絕緣板(30)之表 面金屬塗層，其具有可防止外部及上下層之間的電磁干擾，且該第二銅層(32)可將廢熱導出，減低封裝內的電子零件溫度過高。
請再參照圖4所示，為本發明一種具絕緣板之整合封裝之第四實施型態；第四實施型態與第三實施型態的主要差異在於本實施型態之該第二絕緣板(30)之上表面(301)包含一第二電路(31)，該第二電路(31)與另一電子零件(12”)電性連接。
一般來說，該第二絕緣板(30)係為玻璃布(Woven glass)、環氧樹脂所構成之絕緣材料板，具備加熱軟化特質，因此可熱壓覆蓋該第二電路(31)及該電子零件(12”)，等待冷卻後再次硬化即可保護該第二電路(31)及該電子零件(12”)，該第一絕緣板(20)係為一具有單層(如圖3a表示)或多層線路之印刷電路板，而該第二絕緣板(30)內部形成第二電路(31)，該第二電路(31)顯露於該第二絕緣板(30)之上表面(301)，可作為電性傳遞介面；其中，該電子零件(12”)可為主動元件、被動元件或記憶體，該電子零件(12”)與該第二電路(31)電性連接。
另，如為電性導通基礎電路(11)、第一電路(21)與第二電路(31)三者或電子零件(12,12’,12”)，必須將一第二下層導電孔(33)貫通該第二絕緣板(30)，該第二下層導電孔(32)填充一第二導電材料(24)與該第一電路(21)電性導通。
實際而言，第二下層導電孔(33)如圖4呈現，由第二電路(31)開始貫通第二絕緣板(30)，使第一電路(21)顯露於外；其中，該第二導電材料(24)係具備固定物件及導電特性之膠狀物，在質變後呈固化狀，並維持固定物件及導電特性。
因此本發明之功效有別一般半導體封裝結構，此於半導體堆疊封裝當中實屬首創，符合發明專利要件，爰依法俱文提出申請。
惟，需再次重申，以上所述者僅為本發明之較佳實施型態，舉凡應用本發明說明書、申請專利範圍或圖式所為之等效變化，仍屬本發明所保護之技術範疇，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10:基礎基板
101:上表面
11:基礎電路
12:電子零件
20:絕緣板

Claims (10)

  1. 一種具絕緣板之整合封裝，其包含：一基礎基板、一基礎電路及至少一電子零件，該基礎電路顯露於該基礎基板之上表面，該電子零件與該基礎電路電性連接；一第一絕緣板熱壓覆蓋該基礎基板及該電子零件。
  2. 如請求項1之整合封裝，其中該第一絕緣板之上表面包含一第一電路，該第一電路與另一電子零件電性連接。
  3. 如請求項1之整合封裝，其中該基礎基板之下表面具有複數資訊連結腳及至少一接地腳。
  4. 如請求項1之整合封裝，其中該電子零件可為主動元件、被動元件或記憶體。
  5. 如請求項1之整合封裝，其中該第一絕緣板該表面具有一第一銅層。
  6. 如請求項2之整合封裝，其中一第一下層導電孔貫通該第一絕緣板，該第一下層導電孔填充一第一導電材料與該基礎電路電性導通。
  7. 如請求項6之整合封裝，其中一第二絕緣板熱壓覆蓋該第一電路及該電子零件。
  8. 如請求項7之整合封裝，其中該第二絕緣板之上表面包含一第二電路，該第二電路與另一電子零件電性連接。
  9. 如請求項7之整合封裝，其中第二絕緣板該表面具有一第二銅層。
  10. 如請求項8之整合封裝，其中一第二下層導電孔貫通該第二絕緣板，該第二下層導電孔填充一第二導電材料與該第一電路電性導通。
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CN202996814U (zh) * 2012-11-30 2013-06-12 华东科技股份有限公司 散热型半导体封装构造
TWI673839B (zh) * 2017-06-06 2019-10-01 華東科技股份有限公司 矩形半導體封裝及其方法
TWI714905B (zh) * 2018-11-08 2021-01-01 瑞昱半導體股份有限公司 電路裝置與電路設計及組裝方法

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