TW202312406A - 用於2.5維或3維積體電路之電源佈線 - Google Patents

用於2.5維或3維積體電路之電源佈線 Download PDF

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Publication number
TW202312406A
TW202312406A TW110138998A TW110138998A TW202312406A TW 202312406 A TW202312406 A TW 202312406A TW 110138998 A TW110138998 A TW 110138998A TW 110138998 A TW110138998 A TW 110138998A TW 202312406 A TW202312406 A TW 202312406A
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integrated circuit
interposer
circuit die
die
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TW110138998A
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錫偉 林
維克托 莫羅玆
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美商賽諾西斯公司
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Publication of TW202312406A publication Critical patent/TW202312406A/zh

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Abstract

實施例係關於一種電子電路，其使用一第一積體電路晶粒、一第二積體電路晶粒及將該第一積體電路晶粒連接至該第二積體電路晶粒之一中介層實施。該第一積體電路晶粒實施一第一電子電路。該第一積體電路晶粒包含一底面上之一第一組接點、一埋藏電源軌(BPR)及用於將該BPR連接至該第一組接點之複數個貫穿矽通路(TSV)。該中介層包含一第二組接點及一電源輸送網路(PDN)。該第二組接點之各接點對應於該第一積體電路晶粒之該第一組接點之一接點。該PDN經組態以將一電源供應電壓佈線傳送至該第二組接點。

Description

用於2.5維或3維積體電路之電源佈線
本發明係關於積體電路設計，且更具體而言，本發明係關於使實施積體電路之多個半導體晶粒互連。
三維(3D)積體電路(IC)封裝技術之進步已實現多功能小晶片或封裝之大規模異質積體，諸如一2.5D中介層上之邏輯晶粒及記憶體模組。例如，一封裝可包含一矽中介層及面向下與高頻寬記憶體(HBM)模組並排放置之一單晶片系統(SOC)邏輯晶粒，其等藉由微焊料凸塊(微凸塊)互連接合在一起。
SOC包含一電源輸送網路(PDN)以透過微凸塊接收電源供應及將電源供應佈線傳送至一組電源軌。然而，隨著技術特徵大小按比例縮小，歸因於用於在整個SOC中佈線傳送電源之導體之電壓降及佈線限制，自SOC之前側輸送電源變得越來越難。
實施例係關於一種電子電路，其使用一第一積體電路晶粒、一第二積體電路晶粒及將該第一積體電路晶粒連接至該第二積體電路晶粒之一中介層實施。該第一積體電路晶粒實施一第一電子電路。該第一積體電路晶粒包含一底面上之一第一組接點、一埋藏電源軌(BPR)及用於將該BPR連接至該第一組接點之複數個貫穿矽通路(TSV)。該中介層包含一第二組接點及一電源輸送網路(PDN)。該第二組接點之各接點對應於該第一積體電路晶粒之該第一組接點之一接點。該PDN經組態以將一電源供應電壓佈線傳送至該第二組接點。在一些實施例中，該第一積體電路晶粒接合至該中介層。例如，該積體電路晶粒之該底面接合至該中介層之頂面。此外，在一些實施例中，該中介層使用大於該第一積體電路晶粒之一技術節點製造。
圖及以下描述係關於僅供說明之較佳實施例。應注意，自以下討論，本文所揭示之結構及方法之替代實施例將易於辨識為可在不背離實施例之原理之情況下採用之可行替代。
現將詳細參考其實例在附圖中繪示之若干實施例。應注意，類似或相同元件符號可適當用於圖中且可指示類似或相同功能。圖描述實施例僅供說明。
本發明之態樣係關於用於2.5D或3D積體電路之電源及信號之佈線傳送。特定言之，本發明之態樣係關於在連接至一積體電路晶粒之一中介層中實施一電源輸送網路以將一電源供應電壓分配至積體電路晶粒之多個接點，各接點對應於連接至埋藏電源軌之一貫穿矽通路。
通常，電源供應之分配使用位於積體電路晶粒之前側上之金屬層中之互連件來實施。電源輸送網路用於將電源軌之各者連接至其各自供應電壓。例如，一積體電路晶粒可具有用於供應一第一供應電壓(例如Vdd)之一第一組電源軌及用於供應一第二供應電壓之一第二組電源軌。電源輸送網路包含用於將第一組電源軌中之各電源軌連接至第一供應電壓及用於將第二組電源軌中之各電源軌連接至第二供應電壓之互連件。此外，電源輸送網路包含用於將對應供應電壓提供至相同電源軌內之多個位置以減少歸因於電源軌之電阻率之一電壓降之影響之互連件。
然而，隨著積體電路之特徵大小變小，金屬互連件電阻增大，其可在相同電流流動通過金屬互連件時引起電源軌電壓降增大。為減輕電壓降增大，更多金屬互連件用於電源輸送網路以導致位於積體電路晶粒之前側上之擁擠金屬層。因而，設計與用於使電晶體彼此連接之互連件共用相同金屬層以形成在積體電路晶粒中實施之各種電路之一電源輸送網路變得越來越難。
為緩解此問題，用於積體電路晶粒之電源輸送網路在積體電路晶粒之後側上實施，或在經組態以透過積體電路晶粒之後側連接至積體電路晶粒之一中介層中實施。形成於積體電路晶粒之後側上或一中介層中之電源輸送網路使用連接至埋藏金屬互連件之貫穿矽通路來到達前側。在一些實施例中，電源軌藉由在積體電路晶粒之佈局內之主動組件(即，電晶體)下方之一層級處沿隔離區域運行埋藏金屬互連件來實施為埋藏電源軌。
藉由移動電源輸送網路遠離積體電路晶粒之前側，電源輸送網路及用於使電晶體彼此連接之互連件兩者之設計可簡化。此外，藉由將電源輸送網路自積體電路晶粒移動至中介層，製造積體電路晶粒之成本及良率可改良。 組態概述
圖1A繪示根據一或多個實施例之與一中介層110對準之多個積體電路晶粒120之一分解立視圖。圖1B繪示根據一或多個實施例之使用連接至一中介層110之多個積體電路晶粒(包含一第一積體電路晶粒120及一第二積體電路晶粒125)實施之一系統之一立視圖。在圖1A至圖1B之實例中，系統使用兩個積體電路晶粒120、125及一中介層110來實施。然而，其他實施例可使用不同數目個積體電路晶粒及不同數目個中介層。
在一些實施例中，第一積體電路晶粒120係一邏輯電路，且第二積體電路晶粒125係一高頻寬記憶體(HBM)。積體電路晶粒120及125之各者包含用於將在晶粒中實施之積體電路連接至中介層110之一組接點。在一些實施例中，積體電路晶粒120之接點係微焊料球或微焊料。替代地，積體電路晶粒120、125之接點係墊。此外，儘管圖1A中之接點繪示為正方形墊，但接點可具有任何其他幾何形狀(諸如六邊形、圓形或橢圓形)。
中介層將第一積體電路晶粒120連接至第二積體電路晶粒125。中介層具有對應於第一積體電路晶粒120之接點組之一第一組接點及對應於第二積體電路晶粒125之接點組之一第二組接點。另外，中介層110包含用於將一個接點連接至另一接點之一組互連件。例如，中介層110包含用於將對應於第一積體電路晶粒120之接點連接至對應於第二積體電路晶粒125之接點之一第一組互連件。
另外，中介層將第一積體電路晶粒120或第二積體電路晶粒125連接至一外部電路(諸如一封裝基板，其接著放置於一印刷電路板或PCB上)。中介層可包含連接至外部電路之一第三組接點。另外，中介層110可包含用於將對應於第一積體電路晶粒120之接點或對應於第二積體電路晶粒125之接點連接至對應於外部電路之接點(第三組接點之接點)之互連件。
在一些實施例中，中介層係一矽中介層。中介層可使用大於第一積體電路晶粒120及第二積體電路晶粒125之一製程或技術節點來製造。在一些實施例中，中介層110僅包含用於使接點彼此連接之導線。在其他實施例中，中介層110亦包含被動組件(諸如電阻器或電容器)或主動組件(諸如緩衝器、暫存器或放大器)。 具有一後側電源輸送網路之2.5D或3D IC架構
圖2A係繪示根據一或多個實施例之具有與一中介層110對準之多個積體電路晶粒(例如一第一積體電路晶粒120及一第二積體電路晶粒125)之一中介層架構的一方塊圖。圖2B繪示根據一或多個實施例之與一中介層110對準之多個積體電路晶粒之一剖面圖。在圖2A至圖2B之實例中，第一積體電路晶粒120A及第二積體電路晶粒125A透過中介層110A彼此連接。此外，第一積體電路晶粒120A及第二積體電路晶粒125B透過中介層110A連接至封裝基板290。
在一些實施例中，一蓋295放置於第一積體電路晶粒120A之上。蓋295可經組態以將第一積體電路晶粒120A之高度增大至實質上等於第二積體電路晶粒125A之高度。在一些實施例中，蓋295經組態以使第一積體電路晶粒能夠熱耦合至一散熱片(諸如一散熱器或一積體散熱片)。在此實施例中，蓋295透過一熱界面材料(TIM)附接至第一積體電路晶粒120A之上。
第一積體電路晶粒120A包含與中介層110A之接點對準之接點。接著，第一積體電路晶粒120A之接點電連接至中介層110A之接點以將第一積體電路晶粒120A之電組件連接至中介層110A之電組件。在一些實施例中，第一積體電路晶粒120A使用微焊料球或微焊料凸塊電連接至中介層110A。微焊料球或微焊料凸塊經熔化以引起焊料回流且附接至第一積體電路晶粒120A之接點及中介層晶粒110A之接點兩者。此外，除提供電連接之外，微焊料球或微焊料凸塊亦將第一積體電路晶粒120A機械附接至中介層晶粒110A。類似地，第二積體電路晶粒125A包含與中介層110A之接點對準且電連接至中介層110A之接點之接點。
圖2C繪示根據一或多個實施例之第一積體電路晶粒120A跨一第一方向之一剖面圖。圖2D繪示根據一或多個實施例之第一積體電路晶粒跨一第二方向之一剖面圖。第一積體電路晶粒120A包含其中實施一組主動組件222 (諸如電晶體)之主動層220。主動層220形成於基板230上。在一些實施例中，電晶體222藉由處理基板230之表面(例如藉由蝕刻基板之表面、藉由在基板之表面上沈積或生長層等等)來形成。
在一些實施例中，電晶體222係鰭式場效電晶體(FinFET)。FinFET藉由在基板230之頂部表面上形成半導體鰭片來製造。例如，鰭片藉由圖案化基板230之頂面來形成。在另一實例中，鰭片藉由在基板230之頂面上沈積或生長鰭片來形成。在一些實施例中，電晶體藉由隔離區域(例如，藉由淺溝槽隔離(STI)區域)彼此分離。
在主動層220上，在第一積體電路晶粒120A之前側210上形成一組互連件。互連件使主動層220中之主動組件彼此連接以形成一或多個電路。在一些實施例中，互連件藉由在主動區域220上沈積或生長層且圖案化所沈積或生長之層來形成。該組互連件包含一組金屬層212及一組通路214。該組通路214將一第一金屬層上之一第一金屬互連件連接至第一金屬層上方或下方之一第二金屬層上之一第二金屬互連件。
第一積體電路120A進一步包含具有一組埋藏電源軌(BPR) 232及一組貫穿矽通路(TSV) 234之一基板230。BPR 232經組態以將一供應電壓或一參考電壓提供至主動層220中之電晶體222。BPR 232可形成為在主動層220下方運行。在一些實施例中，BPR 232形成於第一積體電路120A之隔離區域內(例如，嵌入第一積體電路之淺溝槽隔離(STI)區域內)。在一些實施例中，BPR 232藉由在基板中蝕刻溝槽(例如，在STI內)且用一導電材料(諸如一金屬)填充溝槽來形成。此外，BPR藉由在形成BPR之後在基板上沈積一導電層且圖案化導電層來連接至電晶體。
在一些實施例中，基板230包含多個BPR 232。例如，基板包含用於提供一第一供應電壓(例如VDD)之一第一BPR及用於提供一第二供應電壓(例如VSS或GND)之一第二BPR。此外，在一些實施例中，基板230包含用於將第一供應電壓提供至電晶體之一第一子集之一第一BPR及用於將第一供應電壓提供至電晶體之一第二子集之一第三BPR。
TSV 234經組態以將BPR 232連接至電源輸送網路(PDN) 240。在一些實施例中，TSV 234係奈米TSV (nTSV)。例如，nTSV可具有30 nm至100 nm之間的一寬度及50 nm至200 nm之間的一高度。TSV嵌入基板230之一第一側(例如底側)與第一側對置之基板230之一第二側(例如一頂側)之間的第一積體電路晶粒120A之基板內。在一些實施例中，TSV 234容許在第一積體電路晶粒120A之後側240與積體電路晶粒120A之前側210之間佈線傳送電信號。
在一些實施例中，TSV 234之幾何形狀及節距由用於製造第一積體電路晶粒120A之製造技術節點約束。在一些實施例中，TSV 234藉由透過後側蝕刻基板230直至暴露BPR 232之部分且沈積一導電材料來形成。
在一些實施例中，一個BPR 232連接至多個TSV 234。具體而言，TSV 234使BPR 232能夠在多個位置連接至PDN 240以減少歸因於用於製造BPR 232之BPR導體之電阻率之跨BPR 232之電壓降之影響。例如，一TSV 234可至少每隔一BPR 232之設定長度添加至第一積體電路晶粒120A之佈局。在一些實施例中，一TSV 234添加至第一積體電路晶粒120A之佈局之頻率由對應於用於製造第一積體電路晶粒120A之製造技術節點之TSV之一最小節距大小約束。
在積體電路晶粒120A之後側240中，在基板230下面形成後側電源輸送網路(PDN) 250。在一些實施例中，一組輸入-輸出(I/O)節點255亦形成於積體電路晶粒120A之後側240中。在一些實施例中，PDN 250藉由在基板230之底面上沈積或生長層且圖案化所沈積或生長之層來形成。PDN 250包含一組後側金屬層242及一組後側通路244。該組後側通路244將一第一後側金屬層上之一第一金屬互連件連接至第一後側金屬層上方或下方之一第二後側金屬層上之一第二金屬互連件。此外，後側240包含金屬層242之間的絕緣層以將一金屬層與金屬層上方或下方之金屬層隔離。
在一些實施例中，PDN 250連接至中介層110及TSV 234。PDN 250接收一或多個電源供應電壓及參考電壓且將電源供應電壓及參考電壓佈線傳送至TSV 234。此外，TSV 234進一步將一或多個電源供應電壓及參考電壓佈線傳送至BPR 232。在一些實施例中，PDN 250使多個TSV彼此連接以將一供應電壓提供至多個BPR 232或相同BPR 232內之多個位置。例如，PDN 250使對應於用於將一第一供應電壓(例如Vdd)提供至電晶體222之BPR之TSV彼此連接，且使對應於用於將一第二供應電壓(例如Vss或接地)提供至電晶體222之BPR之TSV彼此連接。
I/O節點255經組態以連接至中介層110以自第二積體電路晶粒125A或封裝基板290接收一或多個輸入信號及將一或多個輸出信號發送至第二積體電路晶粒125A或封裝基板290。在一些實施例中，I/O節點255耦合至第一積體電路晶粒120A之前側210中之互連件。在一些實施例中，各I/O節點255包含形成於第一積體電路晶粒120A之基板230內之一埋藏導體252及一TSV 254及形成於第一積體電路晶粒120A之後側240中之一組後側金屬互連件256。在一些實施例中，埋藏導體252與BPR 232一起形成。此外，I/O節點255之TSV 254與連接至PDN 250之TSV 234一起形成。
PDN 250及I/O節點255連接至第一積體電路晶粒120A之底面處之接點248。在一些實施例中，接點248係微焊料球或微焊料凸塊。第一積體電路之接點248經組態以與中介層110A之接點對準且連接至中介層110A之接點。
圖2E繪示根據一或多個實施例之中介層110A之一剖面圖。中介層110A包含用於將中介層110A中之電路元件連接至第一積體電路晶粒120A之一第一組接點260。此外，中介層110A包含用於將中介層110A中之電路元件連接至第二積體電路晶粒125A之一第二組接點270。在一些實施例中，第一組接點260及第二組接點270中之接點係接觸墊。
此外，中介層110A包含用於將中介層110A中之電路元件連接至一外部電路290 (諸如一封裝基板)之一第三組接點280。在一些實施例中，第三組接點280之幾何形狀(例如大小及節距)大於第一組接點260及第二組接點270之幾何形狀。此外，第一組接點260及第二組接點270配置於中介層110A之一第一側(例如頂側)上，且第三組接點配置於與第一側對置之中介層110A之一第二側(例如底側)上。
另外，中介層110A包含一組互連件265。在一些實施例中，互連件之一第一子集經組態以將對應於第一積體電路晶粒120A之第一組接點260之一或多個接點連接至對應於第二積體電路晶粒120A之第二組接點270之一或多個接點。此等互連件使第一積體電路晶粒120A能夠發送或接收來自第二積體電路晶粒125A之信號且容許第二積體電路晶粒125B發送或接收來自第一積體電路晶粒120A之信號。
此外，互連件之一第二子集經組態以將對應於第一積體電路晶粒120A之第一組接點260之一或多個接點連接至第三組接點280之一或多個接點，且互連件之一第三子集經組態以將對應於第二積體電路晶粒125A之第二組接點270之一或多個接點連接至第三組接點280之一或多個接點。互連件之第二子集使第一積體電路120A能夠發送或接收來自外部源290之信號。互連件之第三子集使第二積體電路125A能夠發送或接收來自外部源290之信號。
在一些實施例中，中介層包含一組貫穿矽通路(TSV) 285。TSV 285經組態以將第三組接點280之各接點連接至一金屬互連件265。
圖3A至圖3E繪示根據一或多個實施例之第一積體電路晶粒120A之各種製造步驟之剖面圖。如圖3A中所展示，電晶體222形成於基板230之頂面310上。另外，BPR 232形成於基板230中。在形成電晶體220及BPR 232之後，形成前側互連件以導致圖3B中所展示之結構。
一旦前側處理完成，則使基板變薄以導致圖3C中所展示之結構。在一些實施例中，使用一化學機械拋光(CMP)程序使基板變薄。替代地，使用諸如乾式蝕刻或濕式蝕刻之其他程序。
在基板變薄至一設定厚度之後，形成TSV 234以導致圖3D中所展示之結構。在一些實施例中，TSV 234自變薄基板之底面320形成。例如，TSV 234藉由蝕刻基板直至暴露BPR 232之部分以在基板中形成開口且沈積一金屬以填充開口來形成。
最後，形成後側互連件以導致圖3E中所展示之結構。如上文所描述，後側互連件可藉由在基板之後側上沈積金屬層及絕緣層且圖案化金屬層及絕緣層來形成。 具有一中介層電源輸送網路之2.5D或3D IC架構
圖4A係繪示根據一或多個實施例之具有與具有一中介層電源輸送網路(iPDN) 450之一中介層110B對準之多個積體電路晶粒120之一中介層架構的一方塊圖。圖4B繪示根據一或多個實施例之與具有一iPDN 450之一中介層110B對準之多個積體電路晶粒(例如一第一積體電路晶粒120B及一第二積體電路晶粒125B)之一剖面圖。
第一積體電路晶粒120B包含與中介層110B之接點對準之接點。類似地，第二積體電路晶粒125B包含與中介層110B之接點對準之接點。在圖4B之實例中，第一積體電路晶粒120B接著接合至中介層110B且第二積體電路晶粒125B透過微焊料球連接至中介層110B。在一些實施例中，用於將第一積體電路晶粒120B接合至中介層110B之接合程序包含將第一積體電路晶粒120B之金屬接點接合至中介層110B之金屬接點之一熱程序。例如，第一積體電路晶粒120B及中介層110B可暴露於足以引起金屬相互擴散或熔化或部分熔化金屬接點之溫度。當第一積體電路120B及中介層110B冷卻時，金屬接點熔合在一起以在其等之間形成一永久連接。
在一些實施例中，第一積體電路晶粒120B之面接合至中介層110B之面。即，第一積體電路晶粒120B之底面接合至中介層110B之頂面。例如，使用一熱程序將第一積體電路晶粒120B接合至中介層110B，熱程序引起第一積體電路晶粒120B之底面上之氧化物或氮化物層熔合至中介層110B之頂面上之氧化物或氮化物層。在一些實施例中，一晶粒至晶圓接合程序用於將第一積體電路晶粒120B接合至中介層110B。
圖4C繪示根據一或多個實施例之經組態以連接至具有一iPDN 450之一中介層之第一積體電路晶粒120B跨一第一方向之一剖面圖。圖4D繪示根據一或多個實施例之經組態以連接至具有一iPDN 450之一中介層之第一積體電路晶粒120B跨一第二方向之一剖面圖。第一積體電路晶粒120B包含其中實施一組主動組件422之主動層420、其中形成一組互連件之主動層420上之前側410及具有一組BPR 432及一組TSV 434之基板430。各TSV 434具有兩端。各TSV之一第一端連接至一BPR 432，且各TSV 434之一第二端連接至第一積體電路120B之底面420處之一接點以容許TSV 434連接至在中介層110中實施之一電源輸送網路。在一些實施例中，用於將一TSV 434連接至中介層110B之接點係TSV 434之一暴露表面。
在一些實施例中，基板430另外包含I/O節點455。各I/O節點455包含一埋藏導體452及一TSV 454。埋藏導體452可與BPR 432一起形成。類似地，TSV 454可與TSV 434一起形成。在一些實施例中，I/O節點455圍繞第一積體電路晶粒120B之周邊形成。在其他實施例中，I/O節點455貫穿第一積體電路晶粒120B之底面420。
與圖2B至圖2D之積體電路晶粒120A不同，圖4B至圖4D之積體電路晶粒120B不具有一後側電源輸送網路。因而，積體電路晶粒120B之製造簡化以降低製造積體電路晶粒120B之成本且提高製程之良率。
圖4E繪示根據一或多個實施例之具有一iPDN 450之中介層110B之一剖面圖。中介層110B包含用於將中介層110B中之電路元件連接至第一積體電路晶粒120B之一第一組接點460、用於將中介層110B中之電路元件連接至第二積體電路晶粒125B之一第二組接點470及用於將中介層110B中之電路元件連接至一外部電路490 (諸如一封裝基板)之一第三組接點480。在一些實施例中，第三組接點480之幾何形狀(例如大小)及節距大於第一組接點460及第二組接點470之幾何形狀及節距。此外，第一組接點460及第二組接點470配置於中介層110B之一第一側(例如頂側)上，且第三組接點配置於與第一側對置之中介層110B之一第二側(例如底側)上。
中介層110B進一步包含一中介層電源輸送網路(iPDN) 450及一組I/O互連件465。第一組接點460之接點之至少一第一子集耦合至iPDN，且第一組接點460之接點之至少一第二子集耦合至I/O互連件465。
iPDN經組態以將電源供應電壓佈線傳送至第一組接點460之接點之第一子集。iPDN經組態以耦合至第一積體電路晶粒120B之TSV 434以將一或多個電源供應電壓(例如Vdd、Vss及接地)提供至TSV 434。iPDN 450亦可經組態以使多個TSV 434彼此連接以使TSV 434能夠將一供應電壓提供至一BPR 432中之多個點以減少歸因於用於製造BPR 432之導體之一電阻之跨BPR 432之一電壓降之影響。
iPDN 450包含用於將第一積體電路晶粒120B之一個TSV 434連接至第一積體電路晶粒120B之其他TSV 434且將TSV 434連接至一電源供應電壓(例如，由封裝基板490提供)之一組互連件。在一些實施例中，iPDN 450包含用於將一第一供應電壓(例如Vdd)提供至一第一組TSV 434之一第一組互連件及用於將一第二供應電壓(例如Vss或接地)提供至一第二組TSV 434之一第二組互連件。
I/O互連件465經組態以將對應於第一積體電路晶粒120B之第一組接點460之一接點連接至對應於第二積體電路晶粒125B之第二組接點470之一接點。因此，I/O互連件465在第一積體電路晶粒120B與第二積體電路晶粒125B之間佈線傳送信號。在一些實施例中，I/O互連件465另外將對應於第二積體電路晶粒125B之第二組接點470之一或多個接點連接至第三組接點480之一接點。因此，I/O互連件容許在第二積體電路晶粒120B與基板封裝490之間佈線傳送信號。
在一些實施例中，中介層110B使用大於第一積體電路120B之一技術節點來製造。因而，iPDN 450可更可靠地使用比圖2B至圖2D之第一積體電路晶粒之後側電源輸送網路250更便宜之一程序來製造。
圖5繪示根據一或多個實施例之與具有一iPDN 450之一中介層110C對準之多個積體電路晶粒(例如一第一積體電路晶粒120C及一第二積體電路晶粒125C)之一剖面圖。在圖5之實施例中，第一積體電路晶粒120C及第二積體電路晶粒125C兩者使用面對面接合來接合至中介層110C。在一些實施例中，第一積體電路晶粒120C及第二積體電路晶粒125C使用晶粒至晶圓接合來接合至中介層110C，使得無微焊料凸塊用於將中介層110C連接至第一積體電路晶粒120C及第二積體電路晶粒125C以導致更小電阻及電容且提高封裝之效能及功率。 額外組態考量
如本文所使用，對「一個實施例」或「一實施例」之任何參考意謂結合實施例描述之一特定元件、特徵、結構或特性包含於至少一個實施例中。出現於說明書之各個位置中之片語「在一個實施例中」未必全部係指相同實施例。
一些實施例可使用表達「耦合」及「連接」及其衍生詞來描述。例如，一些實施例可使用術語「耦合」來描述以指示兩個或更多個元件直接實體或電接觸。然而，術語「耦合」亦可意謂兩個或更多個元件彼此不直接接觸，但仍彼此合作或相互作用。實施例不受限於此內文。
如本文所使用，術語「包括」、「包含」、「具有」或任何其他其變型意欲涵蓋一非排他包含。例如，包括一元件清單之一程序、方法、物品或裝置未必僅限於該等元件，而是可包含未明確列出或此程序、方法、物品或裝置固有之其他元件。此外，除非另有明確相反說明，否則「或」係指一包含性「或」而非一排他性「或」。例如，一條件A或B由以下之任何者滿足：A為真(或存在)且B為假(或不存在)；A為假(或不存在)且B為真(或存在)；及A及B兩者為真(或存在)。
另外，「一」之使用用於描述本文實施例之元件及組件。此僅為了方便且給予本發明之一般意義。此描述應被解讀為包含一個或至少一個，且單數亦包含複數，除非其明顯另有含義。
在解讀本發明之後，一般技術者將透過實施例之所揭示原理來瞭解額外替代結構及功能設計。因此，儘管已繪示及描述特定實施例及應用，但應暸解，實施例不受限於本文所揭示之精確構造及組件，且可在不背離所附申請專利範圍中所界定之精神及範疇之情況下對本文所揭示之方法及裝置之配置、操作及細節進行熟習技術者將明白之各種修改、改變及變動。
110:中介層 110A:中介層 110B:中介層 110C:中介層 120:第一積體電路晶粒 120A:第一積體電路晶粒 120B:第一積體電路晶粒 120C:第一積體電路晶粒 125:第二積體電路晶粒 125A:第二積體電路晶粒 125B:第二積體電路晶粒 125C:第二積體電路晶粒 210:前側 212:金屬層 214:通路 220:主動層/主動區域 222:主動組件/電晶體 230:基板 232:埋藏電源軌(BPR) 234:貫穿矽通路(TSV) 240:電源輸送網路(PDN)/後側 242:金屬層 244:後側通路 248:接點 250:PDN 252:埋藏導體 254:TSV路 255:輸入-輸出(I/O)節點 256:後側金屬互連件 260:第一組接點 265:金屬互連件 270:第二組接點 280:第三組接點 285:TSV 290:封裝基板/外部電路/外部源 295:蓋 310:頂面 320:底面 410:前側 420:主動層/底面 422:主動組件 430:基板 432:BPR 434:TSV 450:中介層電源輸送網路(iPDN) 452:埋藏導體 454:TSV 455:I/O節點 460:第一組接點 465:I/O互連件 470:第二組接點 480:第三組接點 490:封裝基板/外部電路
可藉由結合附圖考量以下詳細描述來輕易理解實施例之教示。
圖1A繪示根據一或多個實施例之與一中介層對準之多個積體電路晶粒之一分解立視圖。
圖1B繪示根據一或多個實施例之使用連接至一中介層之多個積體電路晶粒實施之一系統之一立視圖。
圖2A係繪示根據一或多個實施例之具有與一中介層對準之多個積體電路晶粒(例如一第一積體電路晶粒及一第二積體電路晶粒)之一中介層架構的一方塊圖。
圖2B繪示根據一或多個實施例之與一中介層對準之多個積體電路晶粒之一剖面圖。
圖2C繪示根據一或多個實施例之第一積體電路晶粒跨一第一方向之一剖面圖。
圖2D繪示根據一或多個實施例之第一積體電路晶粒跨一第二方向之一剖面圖。
圖2E繪示根據一或多個實施例之中介層之一剖面圖。
圖3A至圖3E繪示根據一或多個實施例之第一積體電路晶粒之各種製造步驟之剖面圖。
圖4A係繪示根據一或多個實施例之具有與具有一中介層電源輸送網路(iPDN)之一中介層對準之多個積體電路晶粒之一中介層架構的一方塊圖。
圖4B繪示根據一或多個實施例之與具有一iPDN之一中介層對準之多個積體電路晶粒(例如一第一積體電路晶粒及一第二積體電路晶粒)之一剖面圖。
圖4C繪示根據一或多個實施例之經組態以連接至具有一iPDN之一中介層之第一積體電路晶粒之一剖面圖。
圖4D繪示根據一或多個實施例之經組態以連接至具有一iPDN之一中介層之第一積體電路晶粒120B跨一第二方向之一剖面圖。
圖4E繪示根據一或多個實施例之具有一iPDN之中介層之一剖面圖。
圖5繪示根據一或多個實施例之接合至一中介層之多個積體電路晶粒之一剖面圖。
110B:中介層
120B:第一積體電路晶粒
125B:第二積體電路晶粒
450:中介層電源輸送網路(iPDN)
490:封裝基板/外部電路

Claims (20)

  1. 一種電子電路，其包括： 一積體電路晶粒，其包括： 一第一組接點， 一埋藏電源軌(BPR)，其安置於該積體電路晶粒之一基板內，該BPR經組態以將一供應電壓提供至該積體電路晶粒之複數個電晶體， 複數個貫穿矽通路(TSV)，該複數個TSV之各TSV具有耦合至該BPR之一第一端及耦合至該第一組接點之一接點之一第二端，該複數個TSV經組態以將該供應電壓提供至該BPR內之多個位置；及 一中介層，其包括： 一第二組接點，該第二組接點之各接點對應於該第一組接點之一接點，及 一電源輸送網路(PDN)，該PDN耦合至該第二組接點，該PDN用於將該電源供應電壓佈線傳送至該第二組接點以將該電源供應提供至該積體電路晶粒之該等TSV之各者。
  2. 如請求項1之電子電路，其中該積體電路晶粒接合至該中介層。
  3. 如請求項2之電子電路，其中該積體電路晶粒之一底面接合至該中介層之一頂面。
  4. 如請求項1之電子電路，其中該積體電路晶粒使用一第一製程節點製造，且其中該中介層使用大於該第一製程節點之一第二製程節點製造。
  5. 如請求項1之電子電路，其中該BPR藉由以下來製造：蝕刻該積體電路晶粒之該基板以在該積體電路晶粒之該基板中形成一開口；及沈積一導電材料以填充該開口。
  6. 如請求項1之電子電路，其中該BPR安置於該積體電路晶粒之一隔離區域內，該隔離區域用於分離實施一積體電路之兩個或更多個電晶體。
  7. 如請求項6之電子電路，其中該隔離區域係一淺溝槽隔離(STI)區域。
  8. 如請求項6之電子電路，其中該BPR耦合至實施該積體電路之該兩個或更多個電晶體之至少一者。
  9. 如請求項1之電子電路，其中該中介層進一步包括： 一第三組接點，其經組態以連接至一外部系統，其中該PDN進一步耦合至該第三組接點。
  10. 如請求項9之電子電路，其中該第二組接點安置於該中介層之一第一表面上，且其中該第三組接點安置於與該第一表面對置之該中介層之一第二表面上。
  11. 如請求項1之電子電路，其中該PDN包括用於使該第二組接點彼此連接之複數個互連件。
  12. 如請求項1之電子電路，其中該複數個TSV沿該BPR之一長度週期性安置。
  13. 如請求項1之電子電路，其中該複數個TSV藉由以下來製造： 使該積體電路晶粒之該基板變薄， 蝕刻該積體電路晶粒之一底面之區域以形成複數個開口，其中該積體電路晶粒之該底面之該等區域被一直蝕刻至暴露該BPR，及 用一導電材料填充該複數個開口。
  14. 一種中介層，其包括： 一第一組接點，該第一組接點對應於一積體電路晶粒之一第二組接點；及 一電源輸送網路，該電源輸送網路用於將一電源供應電壓佈線傳送至該第一組接點之各者。
  15. 如請求項14之中介層，其中該中介層之一頂面經組態以接合至該積體電路晶粒之一底面。
  16. 如請求項14之中介層，其中該積體電路晶粒使用一第一製程節點製造，且其中該中介層使用大於該第一製程節點之一第二製程節點製造。
  17. 如請求項14之中介層，其進一步包括： 一第三組接點，其經組態以連接至一外部系統，其中該PDN進一步經組態以將該第三組接點之一或多個接點耦合至該第二組接點。
  18. 如請求項14之中介層，其中該第一組接點安置於該中介層之一第一表面上，且其中該第三組接點安置於與該第一表面對置之該中介層之一第二表面上。
  19. 如請求項14之中介層，其中該PDN包括用於使該第一組接點彼此連接之複數個互連件。
  20. 如請求項14之中介層，其中該第一組接點週期性配置於該中介層之一頂面上。
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