TW202040777A - 積體電路封裝及其形成方法 - Google Patents
積體電路封裝及其形成方法 Download PDFInfo
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- TW202040777A TW202040777A TW108125689A TW108125689A TW202040777A TW 202040777 A TW202040777 A TW 202040777A TW 108125689 A TW108125689 A TW 108125689A TW 108125689 A TW108125689 A TW 108125689A TW 202040777 A TW202040777 A TW 202040777A
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Abstract
本發明實施例提供積體電路封裝及其形成方法。一種積體電路封裝包括積體電路結構、第一晶粒堆疊及虛設晶粒。第一晶粒堆疊包括多個第一晶粒結構且在第一晶粒堆疊的第一側處接合到積體電路結構。虛設晶粒包括多個基底穿孔,位於第一晶粒堆疊旁邊且在第一晶粒堆疊的第一側處電連接到積體電路結構。在一些實施例中,虛設晶粒的基底穿孔的高度與第一晶粒堆疊的高度相同。
Description
本發明實施例是有關於積體電路封裝及其形成方法。
近年來,由於各種電子元件(例如,電晶體、二極體、電阻器、電容器等)的集成密度持續提高,半導體行業已經歷了快速成長。在很大程度上來說,集成密度的這種提高歸因於最小特徵大小(minimum feature size)的連續減小,這使得能夠在給定區域中集成有更多元件。
這些較小的電子元件也需要與先前的封裝相比佔用較小面積的較小的封裝。半導體的封裝類型的實例包括四方扁平封裝(quad flat pack,QFP)、引腳柵陣列(pin grid array,PGA)、球柵陣列(ball grid array,BGA)、倒裝晶片(flip chip,FC)、三維積體電路(three-dimensional integrated circuit,3DIC)封裝、晶圓級封裝(wafer level package,WLP)以及疊層封裝(package on package,PoP)裝置。一些3DIC是通過在半導體晶圓級上在晶片之上放置晶片製備而成。3DIC提供提高的集成密度及其他優點,例如更快的速度及更高的頻寬,這是因為堆疊的晶片之間的內連線的長度減小。然而,存在許多與3DIC相關的挑戰。
根據本公開的一些實施例,一種積體電路封裝包括積體電路結構、第一晶粒堆疊及虛設晶粒。第一晶粒堆疊包括多個第一晶粒結構且在第一晶粒堆疊的第一側處接合到積體電路結構。虛設晶粒包括多個基底穿孔,位於第一晶粒堆疊旁邊且在第一晶粒堆疊的第一側處電連接到積體電路結構。在一些實施例中,虛設晶粒的基底穿孔的高度與第一晶粒堆疊的高度相同。
根據本公開的替代實施例,一種積體電路封裝包括插板結構、第一晶粒堆疊及第二晶粒堆疊。第一晶粒堆疊包括多個第一晶粒結構且通過包括金屬對金屬接合及介電質對介電質接合的混合接合而接合到插板結構。第二晶粒堆疊包括多個第二晶粒結構且通過包括金屬對金屬接合及介電質對介電質接合的混合接合而接合到插板結構。
根據本公開的又一些替代實施例,一種形成積體電路封裝的方法包括以下操作。提供具有毯覆接合結構的插板結構。提供具有第一接合結構的第一晶粒堆疊、具有第二接合結構的第二晶粒堆疊及具有第三接合結構的積體電路結構。通過包括金屬對金屬接合及介電質對介電質接合的混合接合將第一晶粒堆疊、第二晶粒堆疊及積體電路結構接合到插板結構,其中將第一晶粒堆疊的第一接合結構、第二晶粒堆疊的第二接合結構及積體電路結構的第三接合結構接合到插板結構的毯覆接合結構。移除插板結構的矽部分。
以下公開內容提供用於實施所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及排列的具體實例是為了以簡化方式傳達本公開。當然,這些僅為實例而非旨在進行限制。舉例來說,在以下說明中,在第一特徵之上或第一特徵上形成第二特徵可包括其中第二特徵與第一特徵被形成為直接接觸的實施例,且也可包括其中第二特徵與第一特徵之間可形成附加特徵從而使得第二特徵與第一特徵可不直接接觸的實施例。另外,在本公開的各種實例中可使用相同的參考編號和/或字母來指代相同或相似的部件。參考編號的此種重複使用是為了簡明及清晰起見,且自身並不表示所討論的各個實施例和/或配置之間的關係。
此外,本文中可能使用例如「在……之下」、「 在……下方」、 「 下部的」、 「 在……上」、 「 在……之上」、 「 上覆在……上」、 「在……上方」、 「 上部的」等空間相對性用語來便於闡述圖中所示一個元件或特徵與另一個(其他)元件或特徵的關係。除圖中所繪示的取向以外,所述空間相對性用語還旨在囊括裝置在使用或操作中的不同取向。設備可具有另外的取向(旋轉90度或處於其他取向),且本文所使用的空間相對性描述語可同樣相應地作出解釋。
圖1是根據一些實施例的積體電路封裝的剖視圖。據理解,本公開不受以下所述結構所限制。可在所述結構中添加附加特徵且可替換或去除以下所述特徵中的一些特徵,以得到所述結構的附加實施例。
參照圖1,積體電路封裝1包括積體電路結構IC、第一晶粒堆疊100、可選的第二晶粒堆疊200以及虛設晶粒300。積體電路結構IC可包括一個或多個功能性裝置,例如主動元件和/或被動元件。在一些實施例中,積體電路結構IC可包括邏輯晶粒、記憶體晶粒、中央處理器(central processing unit,CPU)、圖形處理單元(graphics processing unit,GPU)、xPU、微機電系統(micro electro-mechanical system,MEMS)晶粒、系統晶片(system on chip,SoC)晶粒等。在一些實施例中,積體電路結構IC包括半導體基底S、內連線結構IS及接合結構BS。
半導體基底S包括例如矽、鍺等元素半導體和/或例如矽鍺、碳化矽、砷化鎵、砷化銦、氮化鎵或磷化銦等化合物半導體。半導體基底S可包括含矽材料。舉例來說,半導體基底S是絕緣體上矽(silicon-on-insulator,SOI)基底或矽基底。在各種實施例中,半導體基底S可採用平面基底、具有多個鰭(fin)的基底、奈米線的形式或所屬領域中的普通技術人員已知的其他形式。視設計要求而定,半導體基底S可為P型基底或N型基底且在半導體基底S中可具有摻雜區。所述摻雜區可被配置用於N型裝置或P型裝置。在一些實施例中,根據製程要求,半導體基底S可具有一個或多個基底穿孔(through substrate via)(例如,矽穿孔)。半導體基底S包括界定至少一個主動區域的隔離結構,且在主動區域上/主動區域中設置有至少一個裝置。在一些實施例中,所述裝置包括閘極介電層、閘極電極、源極/汲極區、間隙壁等。
內連線結構IS可設置在半導體基底S的第一側(例如,前側)之上。具體來說,內連線結構IS可設置在裝置之上且電連接到裝置。在一些實施例中,內連線結構IS包括金屬間介電層IMD及嵌入在金屬間介電層IMD中的金屬特徵。金屬間介電層IMD可包含氧化矽、氮氧化矽、氮化矽、介電常數(dielectric constant)小於3的低介電常數(低k)材料或其組合等。金屬特徵可包含Cu、Ti、Ta、W、Ru、Co、Ni、其組合等。在一些實施例中,在每一金屬特徵與對應的金屬間介電層IMD之間可設置有晶種層和/或阻障層。晶種層可包含Ti/Cu。阻障層可包含Ta、TaN、Ti、TiN、CoW或其組合。在一些實施例中,金屬特徵包括被配置成與不同元件電連接的頂部金屬墊MPa、MPb及MPc。在一些實施例中,頂部金屬墊MPc的寬度可不同於(例如,大於)頂部金屬墊MPa或MPb的寬度。在替代實施例中,頂部金屬墊MPc的寬度可與頂部金屬墊MPa或MPb的寬度相同。
接合結構BS可設置在半導體基底S的第一側(例如,前側)之上。具體來說,接合結構BS可設置在內連線結構IS之上且電連接到內連線結構IS。在一些實施例中,接合結構BS包括至少一個接合介電層BDL及嵌入在接合介電層BDL中的接合金屬特徵。在一些實施例中,接合介電層BDL包含氧化矽、氮化矽、聚合物或其組合。在一些實施例中,接合金屬特徵包括接合墊BPa、BPb及BPc以及接合通孔BVa、BVb及BVc。具體來說,如圖1中所示,接合墊BPa及接合通孔BVa電連接到第一晶粒堆疊100,接合墊BPb及接合通孔BVb電連接到第二晶粒堆疊200,且接合墊BPc及接合通孔BVc電連接到虛設晶粒300。接合金屬特徵可包含Cu、Ti、Ta、W、Ru、Co、Ni、其組合等。在一些實施例中,在每一接合金屬特徵與接合介電層BDL之間可設置有晶種層和/或阻障層。晶種層可包含Ti/Cu。阻障層可包含Ta、TaN、Ti、TiN、CoW或其組合。
參照圖1,第一晶粒堆疊100在第一晶粒堆疊100的第一側(例如,前側)處接合到積體電路結構IC。在一些實施例中,如圖1中所示,第一晶粒堆疊100以面對面配置(face-to-face configuration)接合到積體電路結構IC。然而,本公開並不限於此,且可應用另一種面對背配置(face-to-back configuration)或背對背配置(back-to-back configuration)。
第一晶粒堆疊100包括垂直堆疊的多個第一晶粒結構C1。第一晶粒結構C1中的每一者可包括一個或多個功能性裝置,例如主動元件和/或被動元件。在一些實施例中,第一晶粒結構C1中的每一者可包括邏輯晶粒、記憶體晶粒、CPU、GPU、xPU、MEMS晶粒、SoC晶粒等。在一些實施例中,第一晶粒結構C1中的每一者包括半導體基底S1、內連線結構IS1及至少一個接合結構。
半導體基底S1可相似於半導體基底S,因此其材料及配置可參考半導體基底S的材料及配置。在一些實施例中,半導體基底S1包括界定至少一個主動區域的隔離結構,且在主動區域上/主動區域中設置有至少一個裝置。在一些實施例中,半導體基底S1可具有一個或多個基底穿孔(例如,矽穿孔)TSV1。基底穿孔TSV1可包含Cu、Ti、Ta、W、Ru、Co、Ni、其組合等。在一些實施例中,在每一基底穿孔TSV1與半導體基底S1之間可設置有晶種層和/或阻障層。晶種層可包含Ti/Cu。阻障層可包含Ta、TaN、Ti、TiN、CoW或其組合。在一些實施例中,基底穿孔TSV1的頂部部分延伸到內連線結構IS1中,且基底穿孔TSV1的底部部分被絕緣層IL1環繞。絕緣層IL1可包含氧化矽或合適的介電材料。
內連線結構IS1可相似於內連線結構IS,因此其材料及配置可參考內連線結構IS的材料及配置。在一些實施例中,內連線結構IS1可設置在半導體基底S1的第一側(例如,前側)之上。具體來說,內連線結構IS1設置在裝置之上且電連接到裝置。在一些實施例中,內連線結構IS1包括金屬間介電層IMD1及嵌入在金屬間介電層IMD1中的金屬特徵。在一些實施例中,金屬特徵包括上部墊UP1及下部墊LP1,上部墊UP1被配置成接合到接合結構BS11,下部墊LP1被配置用於在上面搭接基底穿孔TSV1。
接合結構BS11可相似於接合結構BS,因此其材料及配置可參考接合結構BS的材料及配置。在一些實施例中,接合結構BS11可設置在半導體基底S1的第一側(例如,前側)之上。具體來說,接合結構BS11可設置在內連線結構IS1之上且電連接到內連線結構IS1。在一些實施例中,接合結構BS11包括至少一個接合介電層BDL11及嵌入在接合介電層BDL11中的至少一個接合金屬特徵。在一些實施例中,所述至少一個接合金屬特徵包括接合墊BP11及接合通孔BV11。具體來說,如圖1中所示,一個第一晶粒結構C1的接合墊BP11及接合通孔BV11電連接到積體電路結構IC的接合結構BS或另一個第一晶粒結構C1的接合結構BS12。
在一些實施例中,第一晶粒結構C1可選地包括設置在半導體基底S1的第二側(例如,背側)之上的接合結構BS12。在一些實施例中,接合結構BS12包括至少一個接合介電層BDL12及嵌入在接合介電層BDL12中的至少一個接合金屬特徵。在一些實施例中,接合金屬特徵包括接合墊BP12。具體來說,如圖1中所示,一個第一晶粒結構C1的接合墊BP12電連接到另一個第一晶粒結構C1的接合結構BS11。
在一些實施例中,第一晶粒堆疊100通過包括金屬對金屬接合(metal-to-metal bonding)及介電質對介電質接合(dielectric-to-dielectric bonding)的混合接合(hybrid bonding)而接合到積體電路結構IC。具體來說,第一晶粒堆疊100的接合墊BP11接合到積體電路結構IC的接合墊BPa,且第一晶粒堆疊100的接合介電層BDL11接合到積體電路結構IC的接合介電層BDL。
如圖1中所示,在第一晶粒堆疊100中,第一晶粒結構C1以面對背配置進行堆疊。然而,本公開並不限於此,且可應用另一種面對面配置和/或背對背配置。此外,其中第一晶粒堆疊100具有兩個晶粒結構的實施例是出於例示目的而提供,且不被解釋為限制本公開。第一晶粒堆疊100的晶粒結構的數目不受本公開所限制。
在一些實施例中,兩個相鄰第一晶粒結構C1通過包括金屬對金屬接合及介電質對介電質接合的混合接合而彼此接合。具體來說,一個第一晶粒結構C1的接合墊BP11接合到另一個第一晶粒結構C1的接合墊BP12,且一個第一晶粒結構C1的接合介電層BDL11接合到另一個第一晶粒結構C1的接合介電層BDL12。
在一些實施例中,第一晶粒堆疊100的靠近積體電路結構IC的最上第一晶粒結構C1在其前側及背側處具有兩個接合結構BS11及BS12,且第一晶粒堆疊100的遠離積體電路結構IC的最下第一晶粒結構C1在其前側處具有一個接合結構BS11。在第一晶粒堆疊100中,最上第一晶粒結構C1與最下第一晶粒結構C1之間的中間第一晶粒結構(如果有的話)在其前側及背側處具有兩個接合結構BS11及BS12。
參照圖1,第二晶粒堆疊200在第一晶粒堆疊100的第一側(例如,前側)處接合到積體電路結構IC。在一些實施例中,如圖1中所示,第二晶粒堆疊200以面對面配置接合到積體電路結構IC。然而,本公開並不限於此,且可應用另一種面對背配置或背對背配置。
第二晶粒堆疊200可相似於第一晶粒堆疊100,且其材料及配置可參考第一晶粒堆疊100的材料及配置。第二晶粒堆疊200包括垂直堆疊的多個第二晶粒結構C2。第二晶粒結構C2中的每一者可包括一個或多個功能性裝置,例如主動元件和/或被動元件。在一些實施例中,第二晶粒結構C2中的每一者可包括邏輯晶粒、記憶體晶粒、CPU、GPU、xPU、MEMS晶粒、SoC晶粒等。第二晶粒結構C2可相似於第一晶粒結構C1,且其材料及配置可參考第一晶粒結構C1的材料及配置。在一些實施例中,第二晶粒結構C2中的每一者包括半導體基底S2、內連線結構IS2及至少一個接合結構。
第二晶粒堆疊200和/或第二晶粒結構C2的功能可不同於第一晶粒堆疊100和/或第一晶粒結構C1的功能。舉例來說,第一晶粒堆疊及第二晶粒堆疊中的一者是邏輯堆疊,而第一晶粒堆疊及第二晶粒堆疊中的另一者是記憶體堆疊。視需要,第一晶粒堆疊與第二晶粒堆疊可具有相似的功能。此外,根據製程要求,第二晶粒堆疊200和/或第二晶粒結構C2的尺寸可相似於或不同於第一晶粒堆疊100和/或第一晶粒結構C1的尺寸。尺寸可為高度、寬度、大小、俯視面積或其組合。
半導體基底S2可相似於半導體基底S1,因此其材料及配置可參考半導體基底S1的材料及配置。在一些實施例中,半導體基底S2包括界定至少一個主動區域的隔離結構,且在主動區域上/主動區域中設置有至少一個裝置。在一些實施例中,半導體基底S2可具有一個或多個基底穿孔(例如,矽穿孔)TSV2。在一些實施例中,基底穿孔TSV2的頂部部分延伸到內連線結構IS2中,且基底穿孔TSV2的底部部分被絕緣層IL2環繞。絕緣層IL2可包含氧化矽或合適的介電材料。
內連線結構IS2可相似於內連線結構IS1,因此其材料及配置可參考內連線結構IS1的材料及配置。在一些實施例中,內連線結構IS2可設置在半導體基底S2的第一側(例如,前側)之上。具體來說,內連線結構IS2設置在裝置之上且電連接到裝置。在一些實施例中,內連線結構IS2包括金屬間介電層IMD2及嵌入在金屬間介電層IMD2中的金屬特徵。在一些實施例中,金屬特徵包括上部墊UP2及下部墊LP2,上部墊UP2被配置成接合到接合結構BS21,下部墊LP2被配置用於在上面搭接基底穿孔TSV2。
接合結構BS21可相似於接合結構BS11,因此其材料及配置可參考接合結構BS11的材料及配置。在一些實施例中,接合結構BS21可設置在半導體基底S2的第一側(例如,前側)之上。具體來說,接合結構BS21可設置在內連線結構IS2之上且電連接到內連線結構IS2。在一些實施例中,接合結構BS21包括至少一個接合介電層BDL21及嵌入在接合介電層BDL21中的至少一個接合金屬特徵。在一些實施例中,所述至少一個接合金屬特徵包括接合墊BP21及接合通孔BV21。具體來說,如圖1中所示,一個第二晶粒結構C2的接合墊BP21及接合通孔BV21電連接到積體電路結構IC的接合結構BS或另一個第二晶粒結構C2的接合結構BS22。
在一些實施例中,第二晶粒結構C2可選地包括設置在半導體基底S2的第二側(例如,背側)之上的接合結構BS22。在一些實施例中,接合結構BS22包括至少一個接合介電層BDL22及嵌入在接合介電層BDL22中的至少一個接合金屬特徵。在一些實施例中,接合金屬特徵包括接合墊BP22。具體來說,如圖1中所示,一個第二晶粒結構C2的接合墊BP22電連接到另一個第二晶粒結構C2的接合結構BS21。
在一些實施例中,第二晶粒堆疊200通過包括金屬對金屬接合及介電質對介電質接合的混合接合而接合到積體電路結構IC。具體來說,第二晶粒堆疊200的接合墊BP21接合到積體電路結構IC的接合墊BPb,且第二晶粒堆疊200的接合介電層BDL21接合到積體電路結構IC的接合介電層BDL。
如圖1中所示,在第二晶粒堆疊200中,第二晶粒結構C2以面對背配置進行堆疊。然而,本公開並不限於此,且可應用另一種面對面配置和/或背對背配置。此外,其中第二晶粒堆疊200具有兩個晶粒結構的實施例是出於例示目的而提供,且不被解釋為限制本公開。第二晶粒堆疊200的晶粒結構的數目不受本公開所限制。
在一些實施例中,兩個相鄰第二晶粒結構C2通過包括金屬對金屬接合及介電質對介電質接合的混合接合而彼此接合。具體來說,一個第二晶粒結構C2的接合墊BP21接合到另一個第二晶粒結構C2的接合墊BP22,且一個第二晶粒結構C2的接合介電層BDL21接合到另一個第二晶粒結構C2的接合介電層BDL22。
在一些實施例中,第二晶粒堆疊200的靠近積體電路結構IC的最上第二晶粒結構C2在其前側及背側處具有兩個接合結構BS21及BS22,且第二晶粒堆疊200的遠離積體電路結構IC的最下第二晶粒結構C2在其前側處具有一個接合結構BS21。在第二晶粒堆疊200中,最上第二晶粒結構C2與最下第二晶粒結構C2之間的中間第二晶粒結構(如果有的話)在其前側及背側處具有兩個接合結構BS21及BS22。
參照圖1,虛設晶粒300位於第一晶粒堆疊100和/或第二晶粒堆疊200旁邊,且在第一晶粒堆疊100的第一側(例如,前側)處電連接到積體電路結構IC。
此處,虛設晶粒表示不操作的晶粒(non-operating die)、被配置成不使用(non-use)的晶粒、其中不具備裝置的晶粒或僅用於將晶粒堆疊中的兩個其它晶粒電耦合在一起的晶粒。在一些實施例中,虛設晶粒實質上無任何主動裝置或功能性裝置,例如電晶體、電容器、電阻器、二極體、光電二極體、熔絲裝置和/或其它相似裝置。在一些實施例中,虛設晶粒可被構造成不具備主動組件、不具備被動組件或既不具備主動組件也不具備被動組件。在一些實施例中,在說明書通篇中,將虛設晶粒稱為「無裝置晶粒(device-free die)」。然而,虛設晶粒可包括與相鄰晶粒電連接的至少一個導電特徵。在一些實施例中,所述至少一個導電特徵包括基底穿孔、金屬線、金屬插塞、金屬墊或其組合。具體來說,虛設晶粒可在相鄰晶粒之間起到電連接器(electrical connector)的作用。在一些實施例中,本公開的虛設晶粒可用於將封裝硬化並保護封裝免於發生變形。在一些實施例中,本公開的虛設晶粒可被配置成減少熱膨脹係數(coefficient of thermal expansion,CTE)失配並改善所得封裝的翹曲輪廓。
在一些實施例中,虛設晶粒300包括半導體基底S3以及一個或多個基底穿孔TSV3。在一些實施例中,當半導體基底S3包含矽時,基底穿孔TSV3可稱為矽穿孔。在一些實施例中,半導體基底S3包含與半導體基底S2或半導體基底S1的材料相似的材料,以便減輕第一晶粒堆疊100與第二晶粒堆疊200之間的CTE失配。在一些實施例中,半導體基底S3實質上無摻雜區或隔離結構。半導體基底S3比半導體基底S2或半導體基底S1厚得多。舉例來說,半導體基底S3的高度是半導體基底S2或半導體基底S1的高度的至少3倍,以便有效地減輕晶粒堆疊之間的CTE失配。
基底穿孔TSV3貫穿半導體基底S3。基底穿孔TSV3可電連接到積體電路結構IC的接合墊BPc及接合通孔BVc。基底穿孔TSV3可包含Cu、Ti、Ta、W、Ru、Co、Ni、其組合等。在一些實施例中,在基底穿孔TSV3與半導體基底S3之間可設置有連續的晶種層和/或連續的阻障層。連續的晶種層可包含Ti/Cu。連續的阻障層可包含Ta、TaN、Ti、TiN、CoW或其組合。在基底穿孔TSV3與連續的晶種層或連續的阻障層之間可設置有絕緣襯層(insulating liner)。基底穿孔TSV3可具有平滑傾斜的側壁。然而,本公開並不限於此。在一些實施例中,基底穿孔TSV3可具有實質上垂直的側壁。
在一些實施例中,虛設晶粒300的基底穿孔TSV3的高度與第一晶粒堆疊100和/或第二晶粒堆疊200的高度相同。具體來說,虛設晶粒300的基底穿孔TSV3的頂表面及底表面分別與第一晶粒堆疊100和/或第二晶粒堆疊200的頂表面及底表面實質上共面。
在一些實施例中,虛設晶粒300更包括分別環繞基底穿孔TSV3的頂部部分及底部部分的兩個絕緣層IL3。絕緣層IL3可包含氧化矽或合適的介電材料。
在一些實施例中,基底穿孔TSV3的寬度是基底穿孔TSV1或基底穿孔TSV2的寬度的約5至50倍(例如,10倍至30倍)。在一些實施例中,基底穿孔TSV3的寬度介於約10 μm至15 μm範圍內,且基底穿孔TSV3的深度介於約20 μm至100 μm範圍內。
參照圖1,積體電路封裝1中更包括重佈線層結構RDL。重佈線層結構RDL形成在第一晶粒堆疊100及第二晶粒堆疊200的第二側(例如,背側)之上。所述第二側與第一晶粒堆疊100或第二晶粒堆疊200的第一側相對。重佈線層結構RDL包括至少一個聚合物層PM及由聚合物層PM嵌入的導電特徵。導電特徵包括被配置成與不同元件電連接的金屬墊MP1、MP2及MP3。在一些實施例中,金屬墊MP1電連接到第一晶粒堆疊100的基底穿孔TSV1,金屬墊MP2電連接到第二晶粒堆疊200的基底穿孔TSV2,且金屬墊MP3電連接到虛設晶粒300的基底穿孔TSV3。在一些實施例中,聚合物層PM可包含例如聚苯並惡唑(polybenzoxazole,PBO)、聚醯亞胺(polyimide)、苯並環丁烯(benzocyclobutene,BCB)、其組合等感光性材料。重佈線層結構RDL的聚合物層可視需要以介電層或絕緣層來替換。在一些實施例中,金屬墊MP1、MP2及MP3可包含Cu、Ti、Ta、W、Ru、Co、Ni、其組合等。在一些實施例中,在每一金屬墊與聚合物層PM之間可設置有晶種層和/或阻障層。晶種層可包含Ti/Cu。阻障層可包含Ta、TaN、Ti、TiN、CoW或其組合。
參照圖1,積體電路封裝1中更包括凸塊下金屬化墊UBM。凸塊下金屬化墊UBM設置在重佈線層結構RDL之上且電連接到重佈線層結構RDL。凸塊下金屬化墊UBM可包含Cu、Ti、Ta、W、Ru、Co、Ni、其組合等。在一些實施例中,在每一凸塊下金屬化墊與聚合物層之間可設置有晶種層和/或阻障層。晶種層可包含Ti/Cu。阻障層可包含Ta、TaN、Ti、TiN、CoW或其組合。
在一些實施例中,積體電路封裝1中更包括凸塊B。凸塊B設置在凸塊下金屬化墊UBM之上且電連接到凸塊下金屬化墊UBM,且因此電連接到重佈線層結構RDL。在一些實施例中,凸塊B包含銅、焊料、鎳或其組合。在一些實施例中,凸塊B可為焊球、受控塌陷晶片連接(controlled collapse chip connection,C4)凸塊、球柵陣列(BGA)球、微凸塊(micro bump)、化學鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold technique,ENEPIG)形成的凸塊、銅柱、混合接合凸塊等。
在一些實施例中,如圖1中所示,積體電路封裝1中更包括介電包封體E。介電包封體E形成在第一晶粒堆疊100、第二晶粒堆疊200及虛設晶粒300周圍。具體來說,介電包封體E填充第一晶粒堆疊100、第二晶粒堆疊200及虛設晶粒300中的任意兩者之間的間隙。在一些實施例中,介電包封體E包含模製化合物、模製底部填充膠(molding underfill)、樹脂等。在一些實施例中,介電包封體E包含例如聚苯並惡唑(PBO)、聚醯亞胺、苯並環丁烯(BCB)、其組合等聚合物材料。在替代實施例中,介電包封體E包含氧化矽、氮化矽或其組合。在一些實施例中,第一晶粒堆疊100、第二晶粒堆疊200及虛設晶粒300中的任意兩者之間的間隙介於10 μm至70 μm範圍內。
其中第一晶粒堆疊100、第二晶粒堆疊200及虛設晶粒300中的任意兩者之間的間隙填充有介電包封體E的以上實施例是出於例示目的而提供,且不被解釋為限制本公開。在替代實施例中,如圖1中所示,第一晶粒堆疊100、第二晶粒堆疊200及虛設晶粒300中的任意兩者之間的間隙可填充有空氣A。所述空氣可為乾燥空氣。所述空氣可以乾燥惰性氣體(例如氬氣)、乾燥非活性氣體(例如氮氣)或任何合適的氣體來替換。
圖2A至圖2E是根據一些實施例的形成積體電路封裝的方法的簡化剖視圖。為使例示簡單及清晰,在圖2A至圖2E所示剖視圖中示出僅幾個元件。據理解,本公開不受以下所述方法所限制。可在所述方法之前、期間和/或之後提供附加操作且可替換或去除以下所述操作中的一些操作,以獲得所述方法的附加實施例。
參照圖2A至圖2B,堆疊多個第一晶粒結構C1以形成第一晶粒堆疊100或第一立方體。具體來說,將第一晶粒結構C1逐一地堆疊在載體基底CS上。載體基底CS可為玻璃載體。在一些實施例中,在堆疊第一晶粒結構C1的操作期間,堆疊多個第二晶粒結構C2以形成第二晶粒堆疊200或第二立方體。具體來說,將第二晶粒結構C2逐一地堆疊在載體基底CS上。此後,如圖2B中所示,移除載體基底CS。
參照圖2C,將第一晶粒堆疊100堆疊在積體電路結構IC或基礎結構上。在一些實施例中,在將第一晶粒堆疊100堆疊在積體電路結構IC上的操作期間,將第二晶粒堆疊200堆疊在積體電路結構IC上。在一些實施例中,積體電路結構IC被稱為層級1結構,最靠近積體電路結構IC的第一晶粒結構C1及第二晶粒結構C2被稱為層級2結構,位於層級2結構之上的第一晶粒結構C1及第二晶粒結構C2被稱為層級3結構,等等。
參照圖2D,將具有多個基底穿孔TSV3的虛設晶粒300堆疊在積體電路結構IC上及第一晶粒堆疊100及第二晶粒堆疊200旁邊。
參照圖2E,將上面具有第一晶粒堆疊100、第二晶粒堆疊200及虛設晶粒300的積體電路結構IC上下翻轉。此後,在第一晶粒堆疊100、第二晶粒堆疊200及虛設晶粒300上形成重佈線層結構RDL。之後,在重佈線層結構RDL之上形成凸塊B。
在本公開中,提供具有矽穿孔的單個塊狀虛設晶粒來替換傳統的疊層介電質穿孔(tier-by-tier through dielectric via)。本公開的虛設晶粒有益於簡化製程,減少CTE失配並改善所得封裝的翹曲輪廓。
圖3是根據替代實施例的積體電路封裝的剖視圖。據理解,本公開不受以下所述結構所限制。可在所述結構中添加附加特徵且可替換或去除以下所述特徵中的一些特徵,以獲得所述結構的附加實施例。
參照圖3,積體電路封裝10包括插板(interposer)結構I、第一晶粒堆疊101、第二晶粒堆疊201及可選的積體電路結構IC1。
各種實施例包括與插板結構接合的一個或多個晶粒堆疊。插板結構在晶粒堆疊之間提供電佈線。插板結構可包括設置在半導體基底上的重佈線層結構。重佈線層結構提供往來於晶粒堆疊中的一個或多個晶粒結構的電佈線。在一些實施例中,基底穿孔可延伸穿過半導體基底且電連接到重佈線層結構的導電特徵。在一些實施例中,在重佈線層結構上設置有凸塊,以提供用於與各種元件接合的電連接件。在一些實施例中,為實現小的封裝輪廓,可在製造期間薄化或移除插板結構的半導體基底,且因此,提供無矽基底(無矽)或無矽的插板結構。在替代實施例中,在製造期間可保留插板結構的半導體基底。
在一些實施例中,插板結構I包括重佈線層結構RDLi及毯覆接合結構BSi。在一些實施例中,插板結構I是無矽插板結構。
重佈線層結構RDLi包括至少一個聚合物層及由聚合物層嵌入的導電特徵。導電特徵包括被配置成與不同元件電連接的金屬墊、金屬線和/或金屬通孔。在一些實施例中,聚合物層可包含例如聚苯並惡唑(PBO)、聚醯亞胺(PI)、苯並環丁烯(BCB)、其組合等感光性材料。重佈線層結構RDLi的聚合物層可視需要以介電層或絕緣層來替換。在一些實施例中,導電特徵可包含Cu、Ti、Ta、W、Ru、Co、Ni、其組合等。在一些實施例中,在每一金屬特徵與聚合物層之間可設置有晶種層和/或阻障層。晶種層可包含Ti/Cu。阻障層可包含Ta、TaN、Ti、TiN、CoW或其組合。
毯覆接合結構BSi可設置在重佈線層結構RDLi的第一側之上且電連接到重佈線層結構RDLi的第一側。在一些實施例中,毯覆接合結構BSi包括至少一個接合介電層及嵌入在接合介電層中的接合金屬特徵。在一些實施例中,接合介電層包含氧化矽、氮化矽、聚合物或其組合。在一些實施例中,接合金屬特徵包括接合墊BPia、BPib及BPic以及接合通孔BVia、BVib及BVic。具體來說,如圖3中所示,接合墊BPia及接合通孔BVia電連接到第一晶粒堆疊101,接合墊BPib及接合通孔BVib電連接到第二晶粒堆疊201,且接合墊BPic及接合通孔BVic電連接到積體電路結構IC1。接合金屬特徵可包含Cu、Ti、Ta、W、Ru、Co、Ni、其組合等。在一些實施例中,在每一接合金屬特徵與接合介電層BDLi之間可設置有晶種層和/或阻障層。晶種層可包含Ti/Cu。阻障層可包含Ta、TaN、Ti、TiN、CoW或其組合。
參照圖3,插板結構I中更包括凸塊下金屬化墊UBMi。凸塊下金屬化墊UBMi設置在重佈線層結構RDLi的第二側之上並電連接到重佈線層結構RDLi的第二側。所述第二側與重佈線層結構RDLi的第一側相對。凸塊下金屬化墊UBMi可包含Cu、Ti、Ta、W、Ru、Co、Ni、其組合等。在一些實施例中,在每一凸塊下金屬化墊與聚合物層之間可設置有晶種層和/或阻障層。晶種層可包含Ti/Cu。阻障層可包含Ta、TaN、Ti、TiN、CoW或其組合。
在一些實施例中,插板結構I中更包括凸塊Bi。凸塊Bi設置在凸塊下金屬化墊UBMi之上且電連接到凸塊下金屬化墊UBMi,且因此電連接到重佈線層結構RDLi。在一些實施例中,凸塊Bi包含銅、焊料、鎳或其組合。在一些實施例中,凸塊Bi可為焊球、受控塌陷晶片連接(C4)凸塊、球柵陣列(BGA)球、微凸塊、化學鍍鎳鈀浸金技術(ENEPIG)形成的凸塊、銅柱、混合接合凸塊等。
參照圖3,第一晶粒堆疊101接合到插板結構I。在一些實施例中,第一晶粒堆疊100包括垂直堆疊的多個第一晶粒結構C1。第一晶粒結構C1中的每一者可包括一個或多個功能性裝置,例如主動元件和/或被動元件。在一些實施例中,第一晶粒結構C1中的每一者可包括邏輯晶粒、記憶體晶粒、CPU、GPU、xPU、MEMS晶粒、SoC晶粒等。圖3中的第一晶粒結構C1可相似於圖1中的第一晶粒結構C1,且其材料及配置可參考圖1中的第一晶粒結構C1的材料及配置。在一些實施例中,第一晶粒結構C1中的每一者包括半導體基底S1、內連線結構IS1及至少一個接合結構。
圖3中的半導體基底S1可相似於圖1中的半導體基底S1,因此其材料及配置可參考圖1中的半導體基底S1的材料及配置。在一些實施例中,半導體基底S1包括界定至少一個主動區域的隔離結構,且在主動區域上/主動區域中設置有至少一個裝置。在一些實施例中,半導體基底S1可具有一個或多個基底穿孔(例如,矽穿孔)。在一些實施例中,基底穿孔的頂部部分延伸到內連線結構IS1中,且基底穿孔的底部部分被絕緣層環繞。
圖3中的內連線結構IS1可相似於圖1中的內連線結構IS1,因此其材料及配置可參考圖1中的內連線結構IS1的材料及配置。在一些實施例中,內連線結構IS1可設置在半導體基底S1的第一側(例如,前側)之上。具體來說,內連線結構IS1設置在裝置之上且電連接到裝置。在一些實施例中,內連線結構IS1包括金屬間介電層及嵌入在金屬間介電層中的金屬特徵。
圖3中的接合結構BS11可相似於圖1中的接合結構BS11,因此其材料及配置可參考圖1中的接合結構BS11的材料及配置。在一些實施例中,接合結構BS11可設置在半導體基底S1的第一側(例如,前側)之上。具體來說,接合結構BS11可設置在內連線結構IS1之上且電連接到內連線結構IS1。在一些實施例中,接合結構BS11包括至少一個接合介電層BDL11及嵌入在接合介電層BDL11中的至少一個接合金屬特徵。在一些實施例中,所述至少一個接合金屬特徵包括接合墊BP11及接合通孔BV11。具體來說,如圖3中所示,一個第一晶粒結構C1的接合墊BP11及接合通孔BV11電連接到插板結構I的接合結構BSi或另一個第一晶粒結構C1的接合結構BS12。
在一些實施例中,第一晶粒結構C1可選地包括設置在半導體基底S1的第二側(例如,背側)之上的接合結構BS12。在一些實施例中,接合結構BS12包括至少一個接合介電層BDL12及嵌入在接合介電層BDL12中的至少一個接合金屬特徵。在一些實施例中,所述至少一個接合金屬特徵包括接合墊BP12及接合通孔BV12。具體來說,如圖3中所示,一個第一晶粒結構C1的接合墊BP12及接合通孔BV12電連接到另一個第一晶粒結構C1的接合結構BS11。
在一些實施例中,第一晶粒堆疊101通過包括金屬對金屬接合及介電質對介電質接合的混合接合而接合到插板結構I。具體來說,第一晶粒堆疊101的接合墊BP11接合到插板結構I的接合墊BPia,且第一晶粒堆疊101的接合介電層BDL11接合到插板結構I的接合介電層BDLi。
如圖3中所示,在第一晶粒堆疊101中,第一晶粒結構C1以面對背配置進行堆疊。然而,本公開並不限於此,且可應用另一種面對面配置和/或背對背配置。此外,其中第一晶粒堆疊101具有三個晶粒結構的實施例是出於例示目的而提供,且不被解釋為限制本公開。第一晶粒堆疊101的晶粒結構的數目不受本公開所限制。
在一些實施例中,所述兩個相鄰第一晶粒結構C1通過包括金屬對金屬接合及介電質對介電質接合的混合接合而彼此接合。具體來說,一個第一晶粒結構C1的接合墊BP11接合到另一個第一晶粒結構C1的接合墊BP12,且一個第一晶粒結構C1的接合介電層BDL11接合到另一個第一晶粒結構C1的接合介電層BDL12。
在一些實施例中,第一晶粒堆疊101的靠近插板結構I的最下第一晶粒結構C1在其前側及背側處具有兩個接合結構BS11及BS12,且第一晶粒堆疊101的遠離插板結構I的最上第一晶粒結構C1在其前側處具有一個接合結構BS11。在第一晶粒堆疊101中,最上第一晶粒結構C1與最下第一晶粒結構C1之間的中間第一晶粒結構C在其前側及背側處具有兩個接合結構BS11及BS12。
參照圖3,第二晶粒堆疊201在第一晶粒堆疊101旁邊接合到插板結構I。第二晶粒堆疊201可相似於第一晶粒堆疊101,且其材料及配置可參考第一晶粒堆疊101的材料及配置。第二晶粒堆疊201包括垂直堆疊的多個第二晶粒結構C2。第二晶粒結構C2中的每一者可包括一個或多個功能性裝置,例如主動元件和/或被動元件。在一些實施例中,第二晶粒結構C2中的每一者可包括邏輯晶粒、記憶體晶粒、CPU、GPU、xPU、MEMS晶粒、SoC晶粒等。第二晶粒結構C2可相似於第一晶粒結構C1,且其材料及配置可參考第一晶粒結構C1的材料及配置。在一些實施例中,第二晶粒結構C2包括半導體基底S2、內連線結構IS2及至少一個接合結構。
第二晶粒堆疊201和/或第二晶粒結構C2的功能可與第一晶粒堆疊101和/或第一晶粒結構C1的功能相同。舉例來說,第一晶粒堆疊與第二晶粒堆疊二者都是記憶體堆疊,例如高頻寬記憶體(High Bandwidth Memory,HBM)立方體。視需要,第一晶粒堆疊與第二晶粒堆疊可具有不同的功能。此外,根據製程要求,第二晶粒堆疊201和/或第二晶粒結構C2的尺寸可相似於或不同於第一晶粒堆疊101和/或第一晶粒結構C1的尺寸。尺寸可為高度、寬度、大小、俯視面積或其組合。
半導體基底S2可相似於半導體基底S1,因此其材料及配置可參考半導體基底S的材料及配置。在一些實施例中,半導體基底S2包括界定至少一個主動區域的隔離結構,且在主動區域上/主動區域中設置有至少一個裝置。在一些實施例中,半導體基底S2可具有一個或多個基底穿孔(例如,矽穿孔)。在一些實施例中,基底穿孔的頂部部分延伸到內連線結構IS2中,且基底穿孔TSV2的底部部分被絕緣層環繞。
內連線結構IS2可相似於內連線結構IS1,因此其材料及配置可參考內連線結構IS1的材料及配置。在一些實施例中,內連線結構IS2可設置在半導體基底S2的第一側(例如,前側)之上。具體來說,內連線結構IS2設置在裝置之上且電連接到裝置。在一些實施例中,內連線結構IS2包括金屬間介電層及嵌入在金屬間介電層中的金屬特徵。
接合結構BS21可相似於接合結構BS11,因此其材料及配置可參考接合結構BS11的材料及配置。在一些實施例中,接合結構BS21可設置在半導體基底S2的第一側(例如,前側)之上。具體來說,接合結構BS21可設置在內連線結構IS2之上且電連接到內連線結構IS2。在一些實施例中,接合結構BS21包括至少一個接合介電層BDL21及嵌入在接合介電層BDL21中的至少一個接合金屬特徵。在一些實施例中,所述至少一個接合金屬特徵包括接合墊BP21及接合通孔BV21。具體來說,如圖3中所示,一個第二晶粒結構C2的接合墊BP21及接合通孔BV21電連接到插板結構I的接合結構BSi或另一個第二晶粒結構C2的接合結構BS22。
在一些實施例中,第二晶粒結構C2可選地包括設置在半導體基底S2的第二側(例如,背側)之上的接合結構BS22。在一些實施例中,接合結構BS22包括至少一個接合介電層BDL22及嵌入在接合介電層BDL22中的至少一個接合金屬特徵。在一些實施例中,所述至少一個接合金屬特徵包括接合墊BP22及接合通孔BV22。具體來說,如圖3中所示,一個第二晶粒結構C2的接合墊BP22及接合通孔BV22電連接到另一個第二晶粒結構C2的接合結構BS21。
在一些實施例中,第二晶粒堆疊201通過包括金屬對金屬接合及介電質對介電質接合的混合接合而接合到插板結構I。具體來說,第二晶粒堆疊201的接合墊BP21接合到插板結構I的接合墊BPib,且第二晶粒堆疊201的接合介電層BDL21接合到插板結構I的接合介電層BDLi。
如圖3中所示,在第二晶粒堆疊201中,第二晶粒結構C2以面對背配置進行堆疊。然而,本公開並不限於此,且可應用另一種面對面配置和/或背對背配置。此外,其中第二晶粒堆疊201具有三個晶粒結構的實施例是出於例示目的而提供,且不被解釋為限制本公開。第二晶粒堆疊201的晶粒結構的數目不受本公開所限制。
在一些實施例中,所述兩個相鄰第二晶粒結構C2通過包括金屬對金屬接合及介電質對介電質接合的混合接合而彼此接合。具體來說,一個第二晶粒結構C2的接合墊BP21接合到另一個第二晶粒結構C2的接合墊BP22,且一個第二晶粒結構C2的接合介電層BDL21接合到另一個第二晶粒結構C2的接合介電層BDL22。
在一些實施例中,第二晶粒堆疊201的靠近插板結構I的最下第二晶粒結構C2在其前側及背側處具有兩個接合結構BS21及BS22,且第二晶粒堆疊200的遠離插板結構I的最上第二晶粒結構C2在其前側處具有一個接合結構BS21。在第二晶粒堆疊201中,最上第二晶粒結構C2與最下第二晶粒結構C2之間的中間第二晶粒結構C2在其前側及背側處具有兩個接合結構BS21及BS22。
參照圖3,積體電路結構IC1在第一晶粒堆疊101及第二晶粒堆疊201旁邊接合到插板結構I。積體電路結構IC1可包括一個或多個功能性裝置,例如主動元件和/或被動元件。在一些實施例中,積體電路結構IC1可包括邏輯晶粒、記憶體晶粒、CPU、GPU、xPU、MEMS晶粒、SoC晶粒等。
積體電路結構IC1的功能可不同於第一晶粒堆疊101和/或第二晶粒堆疊201的功能。舉例來說,第一晶粒堆疊及第二晶粒堆疊中的兩者是記憶體堆疊,而積體電路結構IC1是邏輯堆疊。視需要,積體電路結構IC1可具有與第一晶粒堆疊101和/或第二晶粒堆疊201的功能相同的功能。此外,根據製程要求,積體電路結構IC1的尺寸可相似於或不同於第一晶粒堆疊101和/或第二晶粒堆疊201的尺寸。尺寸可為高度、寬度、大小、俯視面積或其組合。
在一些實施例中,積體電路結構IC1是單個晶粒結構。圖3中的積體電路結構IC1可相似於圖1中的積體電路結構IC,且其材料及配置可參考圖1中的積體電路結構IC的材料及配置。在一些實施例中,積體電路結構IC包括半導體基底S3、內連線結構IS3及接合結構BS31。
圖3中的半導體基底S3及內連線結構IS3可相似於圖1中的半導體基底S及內連線結構IS,因此其材料及配置可參考圖1中的半導體基底S及內連線結構IS的材料及配置。
接合結構BS31可相似於接合結構BS11,因此其材料及配置可參考接合結構BS11的材料及配置。在一些實施例中,接合結構BS31可設置在半導體基底S3的第一側(例如,前側)之上。具體來說,接合結構BS31可設置在內連線結構IS3之上且電連接到內連線結構IS3。在一些實施例中,接合結構BS31包括至少一個接合介電層BDL31及嵌入在接合介電層BDL31中的至少一個接合金屬特徵。在一些實施例中,所述至少一個接合金屬特徵包括接合墊BP31及接合通孔BV31。具體來說,如圖3中所示,積體電路結構IC1的接合墊BP31及接合通孔BV31電連接到插板結構I的接合結構BSi。
在一些實施例中,積體電路結構IC1通過包括金屬對金屬接合及介電質對介電質接合的混合接合而接合到插板結構I。具體來說,積體電路結構IC1的接合墊BP31接合到插板結構I的接合墊BPic,且積體電路結構IC1的接合介電層BDL31接合到插板結構I的接合介電層BDLi。
參照圖3,積體電路封裝10中更包括蓋體構件400。蓋體構件400設置在第一晶粒堆疊101、第二晶粒堆疊201及積體電路結構IC1之上。在一些實施例中,蓋體構件400可為包含半導體材料、無機材料、絕緣材料或其組合的基底。舉例來說,蓋體構件400包含矽、陶瓷、石英等。在一些實施例中,蓋體構件400是無裝置構件,但本公開並不限於此。在替代實施例中,蓋體構件400可為含裝置構件。
在一些實施例中,在蓋體構件400與第一晶粒堆疊101之間進一步設置有黏合層AL1,在蓋體構件400與第二晶粒堆疊201之間進一步設置有黏合層AL2,且在蓋體構件400與積體電路結構IC1之間進一步設置有黏合層AL3。黏合層AL1、AL2及AL3可包括氧化物層、晶粒貼合膠帶(die attach tape,DAF)或合適的黏合劑。
參照圖3,積體電路封裝10中更包括介電包封體E。介電包封體E形成在第一晶粒堆疊101、第二晶粒堆疊201及積體電路結構IC1周圍。具體來說,介電包封體E填充第一晶粒堆疊101、第二晶粒堆疊201及積體電路結構IC1中的任意兩者之間的間隙。在一些實施例中,介電包封體E包含模製化合物、模製底部填充膠、樹脂等。在一些實施例中,介電包封體E包含例如聚苯並惡唑(PBO)、聚醯亞胺、苯並環丁烯(BCB)、其組合等聚合物材料。在替代實施例中,介電包封體E包含氧化矽、氮化矽或其組合。在一些實施例中,第一晶粒堆疊101、第二晶粒堆疊201及積體電路結構IC1中的任意兩者之間的間隙介於10 μm至70 μm範圍內。
其中第一晶粒堆疊101、第二晶粒堆疊201及積體電路結構IC1中的任意兩者之間的間隙填充有介電包封體E的以上實施例是出於例示目的而提供,且不被解釋為限制本公開。在替代實施例中,如圖3中所示,第一晶粒堆疊101、第二晶粒堆疊201及積體電路結構IC1中的任意兩者之間的間隙可填充有空氣A。所述空氣可為乾燥空氣。所述空氣可以乾燥惰性氣體(例如氬氣)、乾燥非活性氣體(例如氮氣)或任何合適的氣體來替換。
圖4至圖8所示積體電路封裝11至15是圖3所示積體電路封裝10的經修改結構,因此以下示出其之間的不同之處,且本文中不再對相似之處予以贅述。
圖4所示積體電路封裝11可相似於圖3所示積體電路封裝10,且其之間的不同之處在於,圖3中的積體電路結構IC1是單個晶粒結構,而圖4中的積體電路結構IC2是包括多個第三晶粒結構C3的第三晶粒堆疊。在一些實施例中,第三晶粒結構C3中的每一者包括半導體基底S3、內連線結構IS3、接合結構BS31及可選的接合結構BS32。
如圖4中所示,在積體電路結構IC2中,第三晶粒結構C3以面對背配置進行堆疊。然而,本公開並不限於此,且可應用另一種面對面配置和/或背對背配置。此外,其中積體電路結構IC2具有三個晶粒結構的實施例是出於例示目的而提供,且不被解釋為限制本公開。積體電路結構IC2的晶粒結構的數目不受本公開所限制。
在一些實施例中,兩個相鄰第三晶粒結構C3通過包括金屬對金屬接合及介電質對介電質接合的混合接合而彼此接合。具體來說,一個第三晶粒結構C3的接合墊接合到另一個第三晶粒結構C3的另一個接合墊,且一個第三晶粒結構C3的接合介電層接合到另一個第三晶粒結構C3的另一個接合介電層。
圖5所示積體電路封裝12可相似於圖3所示積體電路封裝10,且其之間的不同之處在於,圖3中的第一/第二晶粒堆疊101/201中的第一/第二晶粒結構C1/C2通過混合接合而接合,而圖5中的第一/第二晶粒堆疊102/202中的第一/第二晶粒結構C1/C2通過焊料接頭(solder joint)而接合。
在一些實施例中,第一晶粒結構C1中的每一者包括半導體基底S1、內連線結構IS1、接合墊P1及凸塊B1以及可選的接合結構BS11。接合墊P1可為凸塊下金屬化墊。凸塊B1設置在墊P1之上且電連接到墊P1,且因此電連接到內連線結構IS1。在一些實施例中,凸塊B1包含銅、焊料、鎳或其組合。在一些實施例中,凸塊B1可為焊球、微凸塊受控塌陷晶片連接(C4)凸塊、球柵陣列(BGA)球、微凸塊、化學鍍鎳鈀浸金技術(ENEPIG)形成的凸塊、銅柱、混合接合凸塊等。在一些實施例中,凸塊B1的尺寸小於凸塊Bi的尺寸。舉例來說,凸塊Bi的尺寸是凸塊B1的尺寸的約5至15倍。
在一些實施例中,第一晶粒堆疊102的靠近插板結構I的最下第一晶粒結構C1在其前側處具有接合結構BS11且在其背側處具有焊料凸塊B1,且第一晶粒堆疊102的遠離插板結構I的最上第一晶粒結構C1在其前側處具有焊料凸塊B1。在第一晶粒堆疊102中,最上第一晶粒結構C1與最下第一晶粒結構C1之間的中間第一晶粒結構C1在其前側及背側處具有焊料凸塊B1。
在一些實施例中,第一晶粒堆疊102中更包括底部填充層UF1。底部填充層UF1被形成為環繞凸塊B1且填充所述兩個相鄰第一晶粒結構C1之間的空間。在一些實施例中,底部填充層UF1包含例如環氧樹脂等模製化合物。
在一些實施例中,第二晶粒結構C2中的每一者包括半導體基底S2、內連線結構IS2、接合墊P2及凸塊B2以及可選的接合結構BS21。接合墊P2可為凸塊下金屬化墊。凸塊B2設置在墊P2之上且電連接到墊P2,且因此電連接到內連線結構IS2。在一些實施例中,凸塊B2包含銅、焊料、鎳或其組合。在一些實施例中,凸塊B2可為焊球、微凸塊受控塌陷晶片連接(C4)凸塊、球柵陣列(BGA)球、微凸塊、化學鍍鎳鈀浸金技術(ENEPIG)形成的凸塊、銅柱、混合接合凸塊等。在一些實施例中,凸塊B2的尺寸小於凸塊Bi的尺寸。舉例來說,凸塊Bi的尺寸是凸塊B2的尺寸的約5至15倍。
在一些實施例中,第二晶粒堆疊202的靠近插板結構I的最下第二晶粒結構C2在其前側處具有接合結構BS21且在其背側處具有焊料凸塊B2,且第二晶粒堆疊202的遠離插板結構I的最上第二晶粒結構C2在其前側處具有焊料凸塊B2。在第二晶粒堆疊202中,最上第二晶粒結構C2與最下第二晶粒結構C2之間的中間第二晶粒結構C2在其前側及背側處具有焊料凸塊B2。
在一些實施例中,第二晶粒堆疊202中更包括底部填充層UF2。底部填充層UF2被形成為環繞凸塊B2且填充所述兩個相鄰第二晶粒結構C2之間的空間。在一些實施例中,底部填充層UF2包含例如環氧樹脂等模製化合物。
圖6至圖8所示積體電路封裝13至15可相似於圖3至圖5所示積體電路封裝10至12,且其之間的不同之處在於,圖3至圖5所示積體電路封裝10至12中的每一者設置有蓋體構件400,而圖6至圖8所示積體電路封裝13至15中的每一者不設置有蓋體構件400。在圖6至圖8所示積體電路封裝13至15中的每一者中,第一晶粒堆疊101/102、第二晶粒堆疊201/202及積體電路結構IC1/IC2中的任意兩者之間的間隙填充有介電包封體E,以有效地保護封裝免於損傷。
圖9A至圖9D是根據替代實施例的形成積體電路封裝的方法的簡化剖視圖。為使例示簡單及清晰,在圖9A至圖9D所示剖視圖中示出僅幾個元件。據理解,本公開不受以下所述方法所限制。可在所述方法之前、期間和/或之後提供附加操作且可替換或去除以下所述操作中的一些操作,以獲得所述方法的附加實施例。
參照圖9A,提供插板結構I。在一些實施例中,插板結構I包括半導體基底Si、位於半導體基底Si之上的重佈線層結構RDLi及位於重佈線層結構RDLi之上的毯覆接合結構BSi。
此後,在插板結構I之上提供具有接合結構B11的第一晶粒堆疊101/102、具有接合結構BS21的第二晶粒堆疊201/202及具有接合結構BS31的積體電路結構IC1/IC2。在一些實施例中,可首先執行與圖2A至圖2B中的操作相似的操作,以形成第一晶粒堆疊101/102及第二晶粒堆疊201/202。具體來說,將第一晶粒結構C1逐一地堆疊在載體基底上以形成第一晶粒堆疊101/102,將第二晶粒結構C2逐一地堆疊在載體基底上以形成第二晶粒堆疊201/202,並移除載體基底。在一些實施例中,當提供積體電路結構IC1/IC2作為晶粒堆疊時,可在堆疊第一晶粒結構C1及第二晶粒結構C2的操作期間形成積體電路結構IC1/IC2。
參照圖9B,通過包括金屬對金屬接合及介電質對介電質接合的混合接合將第一晶粒堆疊101/102、第二晶粒堆疊201/202及積體電路結構IC1/IC2接合到插板結構I。在一些實施例中,將第一晶粒堆疊101/102、第二晶粒堆疊201/202及積體電路結構IC1/IC2的相應接合結構BS11、BS21及BS31接合到插板結構I的毯覆接合結構BSi。
參照圖9C,移除插板結構I的矽部分。在一些實施例中,插板結構I的半導體基底Si被完全移除。
參照圖9D,形成凸塊Bi以電連接到重佈線層結構RDLi。因此,提供一種具有無矽插板結構的積體電路封裝。在一些實施例中,可選地形成蓋體構件400以覆蓋第一晶粒堆疊101/102的頂部、第二晶粒堆疊201/202的頂部及積體電路結構IC1/IC2的頂部。
由於矽基底是半導電的,因此其可能負面地影響形成在其中及形成在其上的電路及連接的性能。舉例來說,矽基底可能造成信號劣化(signal degradation)。在本公開的一些實施例中,提供一種無矽插板結構,且這種無矽插板結構有益於減小封裝大小,降低信號劣化並改善封裝性能。在一些實施例中,不再使用傳統的焊料接頭,而是通過混合接合將兩個或更多個晶粒堆疊接合到插板結構,因此封裝大小可進一步減小。
圖10至圖15是根據又一些替代實施例的各種積體電路封裝的剖視圖。
圖10至圖15所示積體電路封裝20至25相似於圖3至圖8所示積體電路封裝10至15,其之間的不同之處在於,圖3至圖8所示積體電路封裝10至15中的每一者的插板結構I是無矽插板,而圖10至圖15所示積體電路封裝20至25中的每一者的插板結構I是含矽插板。在一些實施例中,圖10至圖15所示積體電路封裝20至25中的每一者的插板結構I包括半導體基底Si、基底穿孔TSVi、重佈線層結構RDLi及毯覆接合結構BSi。在一些實施例中,基底穿孔TSVi延伸到重佈線層結構RDLi中且搭接在重佈線層結構RDLi的金屬墊上。
在一些實施例中,圖10至圖15所示積體電路封裝20至25中的每一者的插板結構I中更包括凸塊下金屬化墊UBMi及凸塊Bi。凸塊下金屬化墊UBMi及凸塊Bi電連接到重佈線層結構RDLi。
圖16A至圖16C是根據又一些替代實施例的形成積體電路封裝的方法的簡化剖視圖。為使例示簡單及清晰,在圖16A至圖16C所示剖視圖中示出僅幾個元件。據理解,本公開不受以下所述方法所限制。可在所述方法之前、期間和/或之後提供附加操作且可替換或去除以下所述操作中的一些操作,以獲得所述方法的附加實施例。
參照圖16A,提供插板結構I。在一些實施例中,插板結構I包括半導體基底Si、位於半導體基底Si之上的重佈線層結構RDLi及位於重佈線層結構RDLi之上的毯覆接合結構BSi。在一些實施例中,半導體基底Si包括基底穿孔TSVi(例如,矽穿孔)。
此後,在插板結構I之上提供具有接合結構B11的第一晶粒堆疊101/102、具有接合結構BS21的第二晶粒堆疊201/202及具有接合結構BS31的積體電路結構IC1/IC2。
參照圖16B,通過包括金屬對金屬接合及介電質對介電質接合的混合接合將第一晶粒堆疊101/102、第二晶粒堆疊201/202及積體電路結構IC1/IC2接合到插板結構I。在一些實施例中,將第一晶粒堆疊101/201、第二晶粒堆疊201/202及積體電路結構IC1/IC2的相應接合結構BS11、BS21及BS31接合到插板結構I的毯覆接合結構BSi。
參照圖16C,形成凸塊Bi以電連接到基底穿孔TSVi,且因此電連接到重佈線層結構RDLi。因此,提供一種具有含矽插板結構的積體電路封裝。在一些實施例中,可選地形成蓋體構件400以覆蓋第一晶粒堆疊101/102的頂部、第二晶粒堆疊201/202的頂部及積體電路結構IC1/IC2的頂部。
在一些實施例中,不再使用傳統的焊料接頭,而是通過混合接合將兩個或更多個晶粒堆疊接合到插板結構,因此封裝大小可進一步減小。
本公開考慮到以上實例的許多變型。據理解,不同的實施例可具有不同的優點,且所有實施例未必需要特定優點。
根據本公開的一些實施例,一種積體電路封裝包括積體電路結構、第一晶粒堆疊及虛設晶粒。第一晶粒堆疊包括多個第一晶粒結構且在第一晶粒堆疊的第一側處接合到積體電路結構。虛設晶粒包括多個基底穿孔,位於第一晶粒堆疊旁邊且在第一晶粒堆疊的第一側處電連接到積體電路結構。在一些實施例中,虛設晶粒的基底穿孔的高度與第一晶粒堆疊的高度相同。
在一些實施例中,所述積體電路封裝,更包括:重佈線層結構,在所述第一晶粒堆疊的第二側處電連接到所述第一晶粒堆疊,其中所述第二側與所述第一晶粒堆疊的所述第一側相對;以及多個凸塊,電連接到所述重佈線層結構。在一些實施例中,所述第一晶粒堆疊通過包括金屬對金屬接合及介電質對介電質接合的混合接合而接合到所述積體電路結構。在一些實施例中,所述第一晶粒堆疊與所述虛設晶粒之間的間隙填充有介電包封體。在一些實施例中,所述第一晶粒堆疊與所述虛設晶粒之間的間隙填充有空氣。在一些實施例中,所述第一晶粒堆疊中的兩個相鄰第一晶粒結構通過包括金屬對金屬接合及介電質對介電質接合的混合接合而接合。在一些實施例中,所述積體電路封裝更包括:第二晶粒堆疊,包括多個第二晶粒結構且在所述第一晶粒堆疊的所述第一側處接合到所述積體電路結構,其中所述虛設晶粒的所述基底穿孔的所述高度與所述第二晶粒堆疊的高度相同。
根據本公開的替代實施例,一種積體電路封裝包括插板結構、第一晶粒堆疊及第二晶粒堆疊。第一晶粒堆疊包括多個第一晶粒結構且通過包括金屬對金屬接合及介電質對介電質接合的混合接合而接合到插板結構。第二晶粒堆疊包括多個第二晶粒結構且通過包括金屬對金屬接合及介電質對介電質接合的混合接合而接合到插板結構。
在一些實施例中,所述插板結構是無矽插板結構。在一些實施例中,所述積體電路結構位於所述第一晶粒堆疊與所述第二晶粒堆疊之間且通過包括金屬對金屬接合及介電質對介電質接合的混合接合而接合到所述插板結構。在一些實施例中,所述積體電路結構是單個晶粒結構。在一些實施例中,所述積體電路結構是包括多個第三晶粒結構的第三晶粒堆疊。在一些實施例中,所述第一晶粒堆疊、所述第二晶粒堆疊及所述積體電路結構中的任意兩者之間的間隙填充有介電包封體。在一些實施例中,所述蓋體構件位於所述第一晶粒堆疊及所述第二晶粒堆疊之上。在一些實施例中,所述第一晶粒堆疊與所述第二晶粒堆疊之間的間隙填充有介電包封體或空氣。在一些實施例中,所述第一晶粒堆疊中的兩個相鄰第一晶粒結構通過包括金屬對金屬接合及介電質對介電質接合的混合接合而接合,且所述第二晶粒堆疊中的兩個相鄰第二晶粒結構通過包括金屬對金屬接合及介電質對介電質接合的混合接合而接合。在一些實施例中,所述第一晶粒堆疊中的兩個相鄰第一晶粒結構通過焊料接頭而接合,且所述第二晶粒堆疊中的兩個相鄰第二晶粒結構通過焊料接頭而接合。
根據本公開的又一些替代實施例,一種形成積體電路封裝的方法包括以下操作。提供具有毯覆接合結構的插板結構。提供具有第一接合結構的第一晶粒堆疊、具有第二接合結構的第二晶粒堆疊及具有第三接合結構的積體電路結構。通過包括金屬對金屬接合及介電質對介電質接合的混合接合將第一晶粒堆疊、第二晶粒堆疊及積體電路結構接合到插板結構,其中將第一晶粒堆疊的第一接合結構、第二晶粒堆疊的第二接合結構及積體電路結構的第三接合結構接合到插板結構的毯覆接合結構。移除插板結構的矽部分。
在一些實施例中,所述第一晶粒堆疊及所述第二晶粒堆疊是通過包括以下的方法形成:將第一晶粒結構逐一地堆疊在載體基底上,以形成所述第一晶粒堆疊;將第二晶粒結構逐一地堆疊在所述載體基底上,以形成所述第二晶粒堆疊;以及移除所述載體基底。在一些實施例中,所述形成積體電路封裝的方法更包括在所述第一晶粒堆疊、所述第二晶粒堆疊及所述積體電路結構之上形成蓋體構件。
也可包括其他特徵及製程。舉例來說,可包括測試結構,以説明對三維(three-dimensional,3D)封裝或3DIC裝置進行驗證測試。所述測試結構可例如包括在重佈線層中或在基底上形成的測試墊,以使得能夠對3D封裝或3DIC進行測試、對探針和/或探針卡(probe card)進行使用等。可對中間結構以及最終結構執行驗證測試。另外,本文中所公開的結構及方法可接合包括對已知良好晶粒(known good die)進行中間驗證的測試方法來使用,以提高良率並降低成本。
以上概述了若干實施例的特徵,以使所屬領域中的技術人員可更好地理解本公開的方面。所屬領域中的技術人員應理解,其可容易地使用本公開作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的和/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到,這些等效構造並不背離本公開的精神及範圍,而且他們可在不背離本公開的精神及範圍的條件下對其作出各種改變、代替及變更。
1、10、11、12、13、14、15、20、21、22、23、24、25:積體電路封裝
100、101、102:第一晶粒堆疊
200、201、202:第二晶粒堆疊
300:虛設晶粒
400:蓋體構件
A:空氣
AL1、AL2、AL3:黏合層
B、Bi:凸塊
B1、B2:凸塊
BDL、BDL11、BDL12、BDL21、BDL22、BDL31、BDLi:接合介電層
BP11、BP12、BP21、BP22、BP31、BPa、BPb、BPc、BPia、BPib、BPic:接合墊
BS、BS11、BS12、BS21、BS22、BS31、BS32:接合結構
BSi:接合結構
BV11、BV12、BV21、BV22、BV31、BVa、BVb、BVc、BVia、BVib、BVic:接合通孔
C1:第一晶粒結構
C2:第二晶粒結構
C3:第三晶粒結構
CS:載體基底
E:介電包封體
I:插板結構
IC、IC1、IC2:積體電路結構
IL1、IL2、IL3:絕緣層
IMD、IMD1、IMD2:金屬間介電層
IS、IS1、IS2、IS3:內連線結構
LP1、LP2:下部墊
MP1、MP2、MP3:金屬墊
Mpa、MPb、MPc:頂部金屬墊
P1、P2:墊
PM:聚合物層
RDL、RDLi:重佈線層結構
S、S1、S2、S3、Si:半導體基底
TSV1、TSV2、TSV3:基底穿孔
TSVi:基底穿孔
UBM、UBMi:凸塊下金屬化墊
UF1、UF2:底部填充層
UP1、UP2:上部墊
圖1是根據一些實施例的積體電路封裝的剖視圖。
圖2A至圖2E是根據一些實施例的形成積體電路封裝的方法的簡化剖視圖。
圖3至圖8是根據替代實施例的各種積體電路封裝的剖視圖。
圖9A至圖9D是根據替代實施例的形成積體電路封裝的方法的簡化剖視圖。
圖10至圖15是根據又一些替代實施例的各種積體電路封裝的剖視圖。
圖16A至圖16C是根據又一些替代實施例的形成積體電路封裝的方法的簡化剖視圖。
1:積體電路封裝
100:第一晶粒堆疊
200:第二晶粒堆疊
300:虛設晶粒
A:空氣
B:凸塊
BDL、BDL11、BDL12、BDL21、BDL22:接合介電層
BP11、BP12、BP21、BP22、BPa、BPb、BPc:接合墊
BS、BS11、BS12、BS21、BS22:接合結構
BV11、BV12、BV21、BV22、BVa、BVb、BVc:接合通孔
C1:第一晶粒結構
C2:第二晶粒結構
E:介電包封體
IC:積體電路結構
IL1、IL2、IL3:絕緣層
IMD、IMD1、IMD2:金屬間介電層
IS、IS1、IS2:內連線結構
LP1、LP2:下部墊
MP1、MP2、MP3:金屬墊
Mpa、MPb、MPc:頂部金屬墊
PM:聚合物層
RDL:重佈線層結構
S、S1、S2、S3:半導體基底
TSV1、TSV2、TSV3:基底穿孔
UP1、UP2:上部墊
Claims (1)
- 一種積體電路封裝,包括: 積體電路結構; 第一晶粒堆疊,包括多個第一晶粒結構且在所述第一晶粒堆疊的第一側處接合到所述積體電路結構;以及 虛設晶粒,包括多個基底穿孔,位於所述第一晶粒堆疊旁邊且在所述第一晶粒堆疊的所述第一側處電連接到所述積體電路結構,其中所述虛設晶粒的所述基底穿孔的高度與所述第一晶粒堆疊的高度相同。
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US16/398,159 US11562982B2 (en) | 2019-04-29 | 2019-04-29 | Integrated circuit packages and methods of forming the same |
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CN (1) | CN111863801A (zh) |
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- 2019-07-19 TW TW108125689A patent/TW202040777A/zh unknown
-
2022
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US20220359462A1 (en) | 2022-11-10 |
US20200343218A1 (en) | 2020-10-29 |
US11562982B2 (en) | 2023-01-24 |
US20230113285A1 (en) | 2023-04-13 |
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