CN111863801A - 集成电路封装及其形成方法 - Google Patents
集成电路封装及其形成方法 Download PDFInfo
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- CN111863801A CN111863801A CN201910588978.7A CN201910588978A CN111863801A CN 111863801 A CN111863801 A CN 111863801A CN 201910588978 A CN201910588978 A CN 201910588978A CN 111863801 A CN111863801 A CN 111863801A
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Abstract
本发明实施例提供集成电路封装及其形成方法。一种集成电路封装包括集成电路结构、第一管芯堆叠及虚设管芯。第一管芯堆叠包括多个第一管芯结构且在第一管芯堆叠的第一侧处结合到集成电路结构。虚设管芯包括多个衬底穿孔,位于第一管芯堆叠旁边且在第一管芯堆叠的第一侧处电连接到集成电路结构。在一些实施例中,虚设管芯的衬底穿孔的高度与第一管芯堆叠的高度相同。
Description
技术领域
本发明实施例是涉及集成电路封装及其形成方法。
背景技术
近年来,由于各种电子组件(例如,晶体管、二极管、电阻器、电容器等)的集成密度持续提高,半导体行业已经历了快速成长。在很大程度上来说,集成密度的这种提高归因于最小特征大小(minimum feature size)的连续减小,这使得能够在给定区域中集成有更多组件。
这些较小的电子组件也需要与先前的封装相比占用较小面积的较小的封装。半导体的封装类型的实例包括四方扁平封装(quad flat pack,QFP)、引脚栅阵列(pin gridarray,PGA)、球栅阵列(ball grid array,BGA)、倒装芯片(flip chip,FC)、三维集成电路(three-dimensional integrated circuit,3DIC)封装、晶片级封装(wafer levelpackage,WLP)以及叠层封装(package on package,PoP)器件。一些3DIC是通过在半导体晶片级上在芯片之上放置芯片制备而成。3DIC提供提高的集成密度及其他优点,例如更快的速度及更高的带宽,这是因为堆叠的芯片之间的内连线的长度减小。然而,存在许多与3DIC相关的挑战。
发明内容
根据本公开的一些实施例,一种集成电路封装包括集成电路结构、第一管芯堆叠及虚设管芯。第一管芯堆叠包括多个第一管芯结构且在第一管芯堆叠的第一侧处结合到集成电路结构。虚设管芯包括多个衬底穿孔,位于第一管芯堆叠旁边且在第一管芯堆叠的第一侧处电连接到集成电路结构。在一些实施例中,虚设管芯的衬底穿孔的高度与第一管芯堆叠的高度相同。
附图说明
图1是根据一些实施例的集成电路封装的剖视图。
图2A至图2E是根据一些实施例的形成集成电路封装的方法的简化剖视图。
图3至图8是根据替代实施例的各种集成电路封装的剖视图。
图9A至图9D是根据替代实施例的形成集成电路封装的方法的简化剖视图。
图10至图15是根据又一些替代实施例的各种集成电路封装的剖视图。
图16A至图16C是根据又一些替代实施例的形成集成电路封装的方法的简化剖视图。
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例是为了以简化方式传达本公开。当然,这些仅为实例而非旨在进行限制。举例来说,在以下说明中,在第一特征之上或第一特征上形成第二特征可包括其中第二特征与第一特征被形成为直接接触的实施例,且也可包括其中第二特征与第一特征之间可形成附加特征从而使得第二特征与第一特征可不直接接触的实施例。另外,在本公开的各种实例中可使用相同的参考编号和/或字母来指代相同或相似的部件。参考编号的此种重复使用是为了简明及清晰起见,且自身并不表示所讨论的各个实施例和/或配置之间的关系。
此外,本文中可能使用例如“在……之下”、“在……下方”、“下部的”、“在……上”、“在……之上”、“上覆在……上”、“在……上方”、“上部的”等空间相对性用语来便于阐述图中所示一个元件或特征与另一个(其他)元件或特征的关系。除图中所绘示的取向以外,所述空间相对性用语还旨在囊括器件在使用或操作中的不同取向。装置可具有另外的取向(旋转90度或处于其他取向),且本文所使用的空间相对性描述语可同样相应地作出解释。
图1是根据一些实施例的集成电路封装的剖视图。据理解,本公开不受以下所述结构所限制。可在所述结构中添加附加特征且可替换或去除以下所述特征中的一些特征,以得到所述结构的附加实施例。
参照图1,集成电路封装1包括集成电路结构IC、第一管芯堆叠100、可选的第二管芯堆叠200以及虚设管芯300。集成电路结构IC可包括一个或多个功能性器件,例如有源组件和/或无源组件。在一些实施例中,集成电路结构IC可包括逻辑管芯、存储器管芯、中央处理器(central processing unit,CPU)、图形处理单元(graphics processing unit,GPU)、xPU、微机电系统(micro electro-mechanical system,MEMS)管芯、系统芯片(system onchip,SoC)管芯等。在一些实施例中,集成电路结构IC包括半导体衬底S、内连线结构IS及结合结构BS。
半导体衬底S包括例如硅、锗等元素半导体和/或例如硅锗、碳化硅、砷化镓、砷化铟、氮化镓或磷化铟等化合物半导体。半导体衬底S可包括含硅材料。举例来说,半导体衬底S是绝缘体上硅(silicon-on-insulator,SOI)衬底或硅衬底。在各种实施例中,半导体衬底S可采用平面衬底、具有多个鳍(fin)的衬底、纳米线的形式或所属领域中的普通技术人员已知的其他形式。视设计要求而定,半导体衬底S可为P型衬底或N型衬底且在半导体衬底S中可具有掺杂区。所述掺杂区可被配置用于N型器件或P型器件。在一些实施例中,根据工艺要求,半导体衬底S可具有一个或多个衬底穿孔(through substrate via)(例如,硅穿孔)。半导体衬底S包括界定至少一个有源区域的隔离结构,且在有源区域上/有源区域中设置有至少一个器件。在一些实施例中,所述器件包括栅极介电层、栅极电极、源极/漏极区、间隔壁等。
内连线结构IS可设置在半导体衬底S的第一侧(例如,前侧)之上。具体来说,内连线结构IS可设置在器件之上且电连接到器件。在一些实施例中,内连线结构IS包括金属间介电层IMD及嵌入在金属间介电层IMD中的金属特征。金属间介电层IMD可包含氧化硅、氮氧化硅、氮化硅、介电常数(dielectric constant)小于3的低介电常数(低k)材料或其组合等。金属特征可包含Cu、Ti、Ta、W、Ru、Co、Ni、其组合等。在一些实施例中,在每一金属特征与对应的金属间介电层IMD之间可设置有晶种层和/或障壁层。晶种层可包含Ti/Cu。障壁层可包含Ta、TaN、Ti、TiN、CoW或其组合。在一些实施例中,金属特征包括被配置成与不同组件电连接的顶部金属垫MPa、MPb及MPc。在一些实施例中,顶部金属垫MPc的宽度可不同于(例如,大于)顶部金属垫MPa或MPb的宽度。在替代实施例中,顶部金属垫MPc的宽度可与顶部金属垫MPa或MPb的宽度相同。
结合结构BS可设置在半导体衬底S的第一侧(例如,前侧)之上。具体来说,结合结构BS可设置在内连线结构IS之上且电连接到内连线结构IS。在一些实施例中,结合结构BS包括至少一个结合介电层BDL及嵌入在结合介电层BDL中的结合金属特征。在一些实施例中,结合介电层BDL包含氧化硅、氮化硅、聚合物或其组合。在一些实施例中,结合金属特征包括结合垫BPa、BPb及BPc以及结合通孔BVa、BVb及BVc。具体来说,如图1中所示,结合垫BPa及结合通孔BVa电连接到第一管芯堆叠100,结合垫BPb及结合通孔BVb电连接到第二管芯堆叠200,且结合垫BPc及结合通孔BVc电连接到虚设管芯300。结合金属特征可包含Cu、Ti、Ta、W、Ru、Co、Ni、其组合等。在一些实施例中,在每一结合金属特征与结合介电层BDL之间可设置有晶种层和/或障壁层。晶种层可包含Ti/Cu。障壁层可包含Ta、TaN、Ti、TiN、CoW或其组合。
参照图1,第一管芯堆叠100在第一管芯堆叠100的第一侧(例如,前侧)处结合到集成电路结构IC。在一些实施例中,如图1中所示,第一管芯堆叠100以面对面配置(face-to-face configuration)结合到集成电路结构IC。然而,本公开并不限于此,且可应用另一种面对背配置(face-to-back configuration)或背对背配置(back-to-backconfiguration)。
第一管芯堆叠100包括垂直堆叠的多个第一管芯结构C1。第一管芯结构C1中的每一者可包括一个或多个功能性器件,例如有源组件和/或无源组件。在一些实施例中,第一管芯结构C1中的每一者可包括逻辑管芯、存储器管芯、CPU、GPU、xPU、MEMS管芯、SoC管芯等。在一些实施例中,第一管芯结构C1中的每一者包括半导体衬底S1、内连线结构IS1及至少一个结合结构。
半导体衬底S1可相似于半导体衬底S,因此其材料及配置可参考半导体衬底S的材料及配置。在一些实施例中,半导体衬底S1包括界定至少一个有源区域的隔离结构,且在有源区域上/有源区域中设置有至少一个器件。在一些实施例中,半导体衬底S1可具有一个或多个衬底穿孔(例如,硅穿孔)TSV1。衬底穿孔TSV1可包含Cu、Ti、Ta、W、Ru、Co、Ni、其组合等。在一些实施例中,在每一衬底穿孔TSV1与半导体衬底S1之间可设置有晶种层和/或障壁层。晶种层可包含Ti/Cu。障壁层可包含Ta、TaN、Ti、TiN、CoW或其组合。在一些实施例中,衬底穿孔TSV1的顶部部分延伸到内连线结构IS1中,且衬底穿孔TSV1的底部部分被绝缘层IL1环绕。绝缘层IL1可包含氧化硅或合适的介电材料。
内连线结构IS1可相似于内连线结构IS,因此其材料及配置可参考内连线结构IS的材料及配置。在一些实施例中,内连线结构IS1可设置在半导体衬底S1的第一侧(例如,前侧)之上。具体来说,内连线结构IS1设置在器件之上且电连接到器件。在一些实施例中,内连线结构IS1包括金属间介电层IMD1及嵌入在金属间介电层IMD1中的金属特征。在一些实施例中,金属特征包括上部垫UP1及下部垫LP1,上部垫UP1被配置成结合到结合结构BS11,下部垫LP1被配置用于在上面搭接衬底穿孔TSV1。
结合结构BS11可相似于结合结构BS,因此其材料及配置可参考结合结构BS的材料及配置。在一些实施例中,结合结构BS11可设置在半导体衬底S1的第一侧(例如,前侧)之上。具体来说,结合结构BS11可设置在内连线结构IS1之上且电连接到内连线结构IS1。在一些实施例中,结合结构BS11包括至少一个结合介电层BDL11及嵌入在结合介电层BDL11中的至少一个结合金属特征。在一些实施例中,所述至少一个结合金属特征包括结合垫BP11及结合通孔BV11。具体来说,如图1中所示,一个第一管芯结构C1的结合垫BP11及结合通孔BV11电连接到集成电路结构IC的结合结构BS或另一个第一管芯结构C1的结合结构BS12。
在一些实施例中,第一管芯结构C1可选地包括设置在半导体衬底S1的第二侧(例如,背侧)之上的结合结构BS12。在一些实施例中,结合结构BS12包括至少一个结合介电层BDL12及嵌入在结合介电层BDL12中的至少一个结合金属特征。在一些实施例中,结合金属特征包括结合垫BP12。具体来说,如图1中所示,一个第一管芯结构C1的结合垫BP12电连接到另一个第一管芯结构C1的结合结构BS11。
在一些实施例中,第一管芯堆叠100通过包括金属对金属结合(metal-to-metalbonding)及介电质对介电质结合(dielectric-to-dielectric bonding)的混合结合(hybrid bonding)而结合到集成电路结构IC。具体来说,第一管芯堆叠100的结合垫BP11结合到集成电路结构IC的结合垫BPa,且第一管芯堆叠100的结合介电层BDL11结合到集成电路结构IC的结合介电层BDL。
如图1中所示,在第一管芯堆叠100中,第一管芯结构C1以面对背配置进行堆叠。然而,本公开并不限于此,且可应用另一种面对面配置和/或背对背配置。此外,其中第一管芯堆叠100具有两个管芯结构的实施例是出于例示目的而提供,且不被解释为限制本公开。第一管芯堆叠100的管芯结构的数目不受本公开所限制。
在一些实施例中,两个相邻第一管芯结构C1通过包括金属对金属结合及介电质对介电质结合的混合结合而彼此结合。具体来说,一个第一管芯结构C1的结合垫BP11结合到另一个第一管芯结构C1的结合垫BP12,且一个第一管芯结构C1的结合介电层BDL11结合到另一个第一管芯结构C1的结合介电层BDL12。
在一些实施例中,第一管芯堆叠100的靠近集成电路结构IC的最上第一管芯结构C1在其前侧及背侧处具有两个结合结构BS11及BS12,且第一管芯堆叠100的远离集成电路结构IC的最下第一管芯结构C1在其前侧处具有一个结合结构BS11。在第一管芯堆叠100中,最上第一管芯结构C1与最下第一管芯结构C1之间的中间第一管芯结构(如果有的话)在其前侧及背侧处具有两个结合结构BS11及BS12。
参照图1,第二管芯堆叠200在第一管芯堆叠100的第一侧(例如,前侧)处结合到集成电路结构IC。在一些实施例中,如图1中所示,第二管芯堆叠200以面对面配置结合到集成电路结构IC。然而,本公开并不限于此,且可应用另一种面对背配置或背对背配置。
第二管芯堆叠200可相似于第一管芯堆叠100,且其材料及配置可参考第一管芯堆叠100的材料及配置。第二管芯堆叠200包括垂直堆叠的多个第二管芯结构C2。第二管芯结构C2中的每一者可包括一个或多个功能性器件,例如有源组件和/或无源组件。在一些实施例中,第二管芯结构C2中的每一者可包括逻辑管芯、存储器管芯、CPU、GPU、xPU、MEMS管芯、SoC管芯等。第二管芯结构C2可相似于第一管芯结构C1,且其材料及配置可参考第一管芯结构C1的材料及配置。在一些实施例中,第二管芯结构C2中的每一者包括半导体衬底S2、内连线结构IS2及至少一个结合结构。
第二管芯堆叠200和/或第二管芯结构C2的功能可不同于第一管芯堆叠100和/或第一管芯结构C1的功能。举例来说,第一管芯堆叠及第二管芯堆叠中的一者是逻辑堆叠,而第一管芯堆叠及第二管芯堆叠中的另一者是存储器堆叠。视需要,第一管芯堆叠与第二管芯堆叠可具有相似的功能。此外,根据工艺要求,第二管芯堆叠200和/或第二管芯结构C2的尺寸可相似于或不同于第一管芯堆叠100和/或第一管芯结构C1的尺寸。尺寸可为高度、宽度、大小、俯视面积或其组合。
半导体衬底S2可相似于半导体衬底S1,因此其材料及配置可参考半导体衬底S1的材料及配置。在一些实施例中,半导体衬底S2包括界定至少一个有源区域的隔离结构,且在有源区域上/有源区域中设置有至少一个器件。在一些实施例中,半导体衬底S2可具有一个或多个衬底穿孔(例如,硅穿孔)TSV2。在一些实施例中,衬底穿孔TSV2的顶部部分延伸到内连线结构IS2中,且衬底穿孔TSV2的底部部分被绝缘层IL2环绕。绝缘层IL2可包含氧化硅或合适的介电材料。
内连线结构IS2可相似于内连线结构IS1,因此其材料及配置可参考内连线结构IS1的材料及配置。在一些实施例中,内连线结构IS2可设置在半导体衬底S2的第一侧(例如,前侧)之上。具体来说,内连线结构IS2设置在器件之上且电连接到器件。在一些实施例中,内连线结构IS2包括金属间介电层IMD2及嵌入在金属间介电层IMD2中的金属特征。在一些实施例中,金属特征包括上部垫UP2及下部垫LP2,上部垫UP2被配置成结合到结合结构BS21,下部垫LP2被配置用于在上面搭接衬底穿孔TSV2。
结合结构BS21可相似于结合结构BS11,因此其材料及配置可参考结合结构BS11的材料及配置。在一些实施例中,结合结构BS21可设置在半导体衬底S2的第一侧(例如,前侧)之上。具体来说,结合结构BS21可设置在内连线结构IS2之上且电连接到内连线结构IS2。在一些实施例中,结合结构BS21包括至少一个结合介电层BDL21及嵌入在结合介电层BDL21中的至少一个结合金属特征。在一些实施例中,所述至少一个结合金属特征包括结合垫BP21及结合通孔BV21。具体来说,如图1中所示,一个第二管芯结构C2的结合垫BP21及结合通孔BV21电连接到集成电路结构IC的结合结构BS或另一个第二管芯结构C2的结合结构BS22。
在一些实施例中,第二管芯结构C2可选地包括设置在半导体衬底S2的第二侧(例如,背侧)之上的结合结构BS22。在一些实施例中,结合结构BS22包括至少一个结合介电层BDL22及嵌入在结合介电层BDL22中的至少一个结合金属特征。在一些实施例中,结合金属特征包括结合垫BP22。具体来说,如图1中所示,一个第二管芯结构C2的结合垫BP22电连接到另一个第二管芯结构C2的结合结构BS21。
在一些实施例中,第二管芯堆叠200通过包括金属对金属结合及介电质对介电质结合的混合结合而结合到集成电路结构IC。具体来说,第二管芯堆叠200的结合垫BP21结合到集成电路结构IC的结合垫BPb,且第二管芯堆叠200的结合介电层BDL21结合到集成电路结构IC的结合介电层BDL。
如图1中所示,在第二管芯堆叠200中,第二管芯结构C2以面对背配置进行堆叠。然而,本公开并不限于此,且可应用另一种面对面配置和/或背对背配置。此外,其中第二管芯堆叠200具有两个管芯结构的实施例是出于例示目的而提供,且不被解释为限制本公开。第二管芯堆叠200的管芯结构的数目不受本公开所限制。
在一些实施例中,两个相邻第二管芯结构C2通过包括金属对金属结合及介电质对介电质结合的混合结合而彼此结合。具体来说,一个第二管芯结构C2的结合垫BP21结合到另一个第二管芯结构C2的结合垫BP22,且一个第二管芯结构C2的结合介电层BDL21结合到另一个第二管芯结构C2的结合介电层BDL22。
在一些实施例中,第二管芯堆叠200的靠近集成电路结构IC的最上第二管芯结构C2在其前侧及背侧处具有两个结合结构BS21及BS22,且第二管芯堆叠200的远离集成电路结构IC的最下第二管芯结构C2在其前侧处具有一个结合结构BS21。在第二管芯堆叠200中,最上第二管芯结构C2与最下第二管芯结构C2之间的中间第二管芯结构(如果有的话)在其前侧及背侧处具有两个结合结构BS21及BS22。
参照图1,虚设管芯300位于第一管芯堆叠100和/或第二管芯堆叠200旁边,且在第一管芯堆叠100的第一侧(例如,前侧)处电连接到集成电路结构IC。
此处,虚设管芯表示不操作的管芯(non-operating die)、被配置成不使用(non-use)的管芯、其中不具备器件的管芯或仅用于将管芯堆叠中的两个其它管芯电耦合在一起的管芯。在一些实施例中,虚设管芯实质上无任何有源器件或功能性器件,例如晶体管、电容器、电阻器、二极管、光电二极管、熔丝器件和/或其它相似器件。在一些实施例中,虚设管芯可被构造成不具备有源组件、不具备无源组件或既不具备有源组件也不具备无源组件。在一些实施例中,在说明书通篇中,将虚设管芯称为“无器件管芯(device-free die)”。然而,虚设管芯可包括与相邻管芯电连接的至少一个导电特征。在一些实施例中,所述至少一个导电特征包括衬底穿孔、金属线、金属插塞、金属垫或其组合。具体来说,虚设管芯可在相邻管芯之间起到电连接器(electrical connector)的作用。在一些实施例中,本公开的虚设管芯可用于将封装硬化并保护封装免于发生变形。在一些实施例中,本公开的虚设管芯可被配置成减少热膨胀系数(coefficient of thermal expansion,CTE)失配并改善所得封装的翘曲轮廓。
在一些实施例中,虚设管芯300包括半导体衬底S3以及一个或多个衬底穿孔TSV3。在一些实施例中,当半导体衬底S3包含硅时,衬底穿孔TSV3可称为硅穿孔。在一些实施例中,半导体衬底S3包含与半导体衬底S2或半导体衬底S1的材料相似的材料,以便减轻第一管芯堆叠100与第二管芯堆叠200之间的CTE失配。在一些实施例中,半导体衬底S3实质上无掺杂区或隔离结构。半导体衬底S3比半导体衬底S2或半导体衬底S1厚得多。举例来说,半导体衬底S3的高度是半导体衬底S2或半导体衬底S1的高度的至少3倍,以便有效地减轻管芯堆叠之间的CTE失配。
衬底穿孔TSV3贯穿半导体衬底S3。衬底穿孔TSV3可电连接到集成电路结构IC的结合垫BPc及结合通孔BVc。衬底穿孔TSV3可包含Cu、Ti、Ta、W、Ru、Co、Ni、其组合等。在一些实施例中,在衬底穿孔TSV3与半导体衬底S3之间可设置有连续的晶种层和/或连续的障壁层。连续的晶种层可包含Ti/Cu。连续的障壁层可包含Ta、TaN、Ti、TiN、CoW或其组合。在衬底穿孔TSV3与连续的晶种层或连续的障壁层之间可设置有绝缘衬层(insulating liner)。衬底穿孔TSV3可具有平滑倾斜的侧壁。然而,本公开并不限于此。在一些实施例中,衬底穿孔TSV3可具有实质上垂直的侧壁。
在一些实施例中,虚设管芯300的衬底穿孔TSV3的高度与第一管芯堆叠100和/或第二管芯堆叠200的高度相同。具体来说,虚设管芯300的衬底穿孔TSV3的顶表面及底表面分别与第一管芯堆叠100和/或第二管芯堆叠200的顶表面及底表面实质上共面。
在一些实施例中,虚设管芯300进一步包括分别环绕衬底穿孔TSV3的顶部部分及底部部分的两个绝缘层IL3。绝缘层IL3可包含氧化硅或合适的介电材料。
在一些实施例中,衬底穿孔TSV3的宽度是衬底穿孔TSV1或衬底穿孔TSV2的宽度的约5至50倍(例如,10倍至30倍)。在一些实施例中,衬底穿孔TSV3的宽度介于约10μm至15μm范围内,且衬底穿孔TSV3的深度介于约20μm至100μm范围内。
参照图1,集成电路封装1中进一步包括重布线层结构RDL。重布线层结构RDL形成在第一管芯堆叠100及第二管芯堆叠200的第二侧(例如,背侧)之上。所述第二侧与第一管芯堆叠100或第二管芯堆叠200的第一侧相对。重布线层结构RDL包括至少一个聚合物层PM及由聚合物层PM嵌入的导电特征。导电特征包括被配置成与不同组件电连接的金属垫MP1、MP2及MP3。在一些实施例中,金属垫MP1电连接到第一管芯堆叠100的衬底穿孔TSV1,金属垫MP2电连接到第二管芯堆叠200的衬底穿孔TSV2,且金属垫MP3电连接到虚设管芯300的衬底穿孔TSV3。在一些实施例中,聚合物层PM可包含例如聚苯并恶唑(polybenzoxazole,PBO)、聚酰亚胺(polyimide)、苯并环丁烯(benzocyclobutene,BCB)、其组合等感光性材料。重布线层结构RDL的聚合物层可视需要以介电层或绝缘层来替换。在一些实施例中,金属垫MP1、MP2及MP3可包含Cu、Ti、Ta、W、Ru、Co、Ni、其组合等。在一些实施例中,在每一金属垫与聚合物层PM之间可设置有晶种层和/或障壁层。晶种层可包含Ti/Cu。障壁层可包含Ta、TaN、Ti、TiN、CoW或其组合。
参照图1,集成电路封装1中进一步包括凸块下金属化垫UBM。凸块下金属化垫UBM设置在重布线层结构RDL之上且电连接到重布线层结构RDL。凸块下金属化垫UBM可包含Cu、Ti、Ta、W、Ru、Co、Ni、其组合等。在一些实施例中,在每一凸块下金属化垫与聚合物层之间可设置有晶种层和/或障壁层。晶种层可包含Ti/Cu。障壁层可包含Ta、TaN、Ti、TiN、CoW或其组合。
在一些实施例中,集成电路封装1中进一步包括凸块B。凸块B设置在凸块下金属化垫UBM之上且电连接到凸块下金属化垫UBM,且因此电连接到重布线层结构RDL。在一些实施例中,凸块B包含铜、焊料、镍或其组合。在一些实施例中,凸块B可为焊球、受控塌陷芯片连接(controlled collapse chip connection,C4)凸块、球栅阵列(BGA)球、微凸块(microbump)、化学镀镍钯浸金技术(electroless nickel-electroless palladium-immersiongold technique,ENEPIG)形成的凸块、铜柱、混合结合凸块等。
在一些实施例中,如图1中所示,集成电路封装1中进一步包括介电包封体E。介电包封体E形成在第一管芯堆叠100、第二管芯堆叠200及虚设管芯300周围。具体来说,介电包封体E填充第一管芯堆叠100、第二管芯堆叠200及虚设管芯300中的任意两者之间的间隙。在一些实施例中,介电包封体E包含模制化合物、模制底部填充胶(molding underfill)、树脂等。在一些实施例中,介电包封体E包含例如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)、其组合等聚合物材料。在替代实施例中,介电包封体E包含氧化硅、氮化硅或其组合。在一些实施例中,第一管芯堆叠100、第二管芯堆叠200及虚设管芯300中的任意两者之间的间隙介于10μm至70μm范围内。
其中第一管芯堆叠100、第二管芯堆叠200及虚设管芯300中的任意两者之间的间隙填充有介电包封体E的以上实施例是出于例示目的而提供,且不被解释为限制本公开。在替代实施例中,如图1中所示,第一管芯堆叠100、第二管芯堆叠200及虚设管芯300中的任意两者之间的间隙可填充有空气A。所述空气可为干燥空气。所述空气可以干燥惰性气体(例如氩气)、干燥非活性气体(例如氮气)或任何合适的气体来替换。
图2A至图2E是根据一些实施例的形成集成电路封装的方法的简化剖视图。为使例示简单及清晰,在图2A至图2E所示剖视图中示出仅几个元件。据理解,本公开不受以下所述方法所限制。可在所述方法之前、期间和/或之后提供附加操作且可替换或去除以下所述操作中的一些操作,以获得所述方法的附加实施例。
参照图2A至图2B,堆叠多个第一管芯结构C1以形成第一管芯堆叠100或第一立方体。具体来说,将第一管芯结构C1逐一地堆叠在载体衬底CS上。载体衬底CS可为玻璃载体。在一些实施例中,在堆叠第一管芯结构C1的操作期间,堆叠多个第二管芯结构C2以形成第二管芯堆叠200或第二立方体。具体来说,将第二管芯结构C2逐一地堆叠在载体衬底CS上。此后,如图2B中所示,移除载体衬底CS。
参照图2C,将第一管芯堆叠100堆叠在集成电路结构IC或基础结构上。在一些实施例中,在将第一管芯堆叠100堆叠在集成电路结构IC上的操作期间,将第二管芯堆叠200堆叠在集成电路结构IC上。在一些实施例中,集成电路结构IC被称为层级1结构,最靠近集成电路结构IC的第一管芯结构C1及第二管芯结构C2被称为层级2结构,位于层级2结构之上的第一管芯结构C1及第二管芯结构C2被称为层级3结构,等等。
参照图2D,将具有多个衬底穿孔TSV3的虚设管芯300堆叠在集成电路结构IC上及第一管芯堆叠100及第二管芯堆叠200旁边。
参照图2E,将上面具有第一管芯堆叠100、第二管芯堆叠200及虚设管芯300的集成电路结构IC上下翻转。此后,在第一管芯堆叠100、第二管芯堆叠200及虚设管芯300上形成重布线层结构RDL。之后,在重布线层结构RDL之上形成凸块B。
在本公开中,提供具有硅穿孔的单个块状虚设管芯来替换传统的叠层介电质穿孔(tier-by-tier through dielectric via)。本公开的虚设管芯有益于简化工艺,减少CTE失配并改善所得封装的翘曲轮廓。
图3是根据替代实施例的集成电路封装的剖视图。据理解,本公开不受以下所述结构所限制。可在所述结构中添加附加特征且可替换或去除以下所述特征中的一些特征,以获得所述结构的附加实施例。
参照图3,集成电路封装10包括插板(interposer)结构I、第一管芯堆叠101、第二管芯堆叠201及可选的集成电路结构IC1。
各种实施例包括与插板结构结合的一个或多个管芯堆叠。插板结构在管芯堆叠之间提供电布线。插板结构可包括设置在半导体衬底上的重布线层结构。重布线层结构提供往来于管芯堆叠中的一个或多个管芯结构的电布线。在一些实施例中,衬底穿孔可延伸穿过半导体衬底且电连接到重布线层结构的导电特征。在一些实施例中,在重布线层结构上设置有凸块,以提供用于与各种组件结合的电连接件。在一些实施例中,为实现小的封装轮廓,可在制造期间薄化或移除插板结构的半导体衬底,且因此,提供无硅衬底(无硅)或无硅的插板结构。在替代实施例中,在制造期间可保留插板结构的半导体衬底。
在一些实施例中,插板结构I包括重布线层结构RDLi及毯覆结合结构BSi。在一些实施例中,插板结构I是无硅插板结构。
重布线层结构RDLi包括至少一个聚合物层及由聚合物层嵌入的导电特征。导电特征包括被配置成与不同组件电连接的金属垫、金属线和/或金属通孔。在一些实施例中,聚合物层可包含例如聚苯并恶唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)、其组合等感光性材料。重布线层结构RDLi的聚合物层可视需要以介电层或绝缘层来替换。在一些实施例中,导电特征可包含Cu、Ti、Ta、W、Ru、Co、Ni、其组合等。在一些实施例中,在每一金属特征与聚合物层之间可设置有晶种层和/或障壁层。晶种层可包含Ti/Cu。障壁层可包含Ta、TaN、Ti、TiN、CoW或其组合。
毯覆结合结构BSi可设置在重布线层结构RDLi的第一侧之上且电连接到重布线层结构RDLi的第一侧。在一些实施例中,毯覆结合结构BSi包括至少一个结合介电层及嵌入在结合介电层中的结合金属特征。在一些实施例中,结合介电层包含氧化硅、氮化硅、聚合物或其组合。在一些实施例中,结合金属特征包括结合垫BPia、BPib及BPic以及结合通孔BVia、BVib及BVic。具体来说,如图3中所示,结合垫BPia及结合通孔BVia电连接到第一管芯堆叠101,结合垫BPib及结合通孔BVib电连接到第二管芯堆叠201,且结合垫BPic及结合通孔BVic电连接到集成电路结构IC1。结合金属特征可包含Cu、Ti、Ta、W、Ru、Co、Ni、其组合等。在一些实施例中,在每一结合金属特征与结合介电层BDLi之间可设置有晶种层和/或障壁层。晶种层可包含Ti/Cu。障壁层可包含Ta、TaN、Ti、TiN、CoW或其组合。
参照图3,插板结构I中进一步包括凸块下金属化垫UBMi。凸块下金属化垫UBMi设置在重布线层结构RDLi的第二侧之上并电连接到重布线层结构RDLi的第二侧。所述第二侧与重布线层结构RDLi的第一侧相对。凸块下金属化垫UBMi可包含Cu、Ti、Ta、W、Ru、Co、Ni、其组合等。在一些实施例中,在每一凸块下金属化垫与聚合物层之间可设置有晶种层和/或障壁层。晶种层可包含Ti/Cu。障壁层可包含Ta、TaN、Ti、TiN、CoW或其组合。
在一些实施例中,插板结构I中进一步包括凸块Bi。凸块Bi设置在凸块下金属化垫UBMi之上且电连接到凸块下金属化垫UBMi,且因此电连接到重布线层结构RDLi。在一些实施例中,凸块Bi包含铜、焊料、镍或其组合。在一些实施例中,凸块Bi可为焊球、受控塌陷芯片连接(C4)凸块、球栅阵列(BGA)球、微凸块、化学镀镍钯浸金技术(ENEPIG)形成的凸块、铜柱、混合结合凸块等。
参照图3,第一管芯堆叠101结合到插板结构I。在一些实施例中,第一管芯堆叠100包括垂直堆叠的多个第一管芯结构C1。第一管芯结构C1中的每一者可包括一个或多个功能性器件,例如有源组件和/或无源组件。在一些实施例中,第一管芯结构C1中的每一者可包括逻辑管芯、存储器管芯、CPU、GPU、xPU、MEMS管芯、SoC管芯等。图3中的第一管芯结构C1可相似于图1中的第一管芯结构C1,且其材料及配置可参考图1中的第一管芯结构C1的材料及配置。在一些实施例中,第一管芯结构C1中的每一者包括半导体衬底S1、内连线结构IS1及至少一个结合结构。
图3中的半导体衬底S1可相似于图1中的半导体衬底S1,因此其材料及配置可参考图1中的半导体衬底S1的材料及配置。在一些实施例中,半导体衬底S1包括界定至少一个有源区域的隔离结构,且在有源区域上/有源区域中设置有至少一个器件。在一些实施例中,半导体衬底S1可具有一个或多个衬底穿孔(例如,硅穿孔)。在一些实施例中,衬底穿孔的顶部部分延伸到内连线结构IS1中,且衬底穿孔的底部部分被绝缘层环绕。
图3中的内连线结构IS1可相似于图1中的内连线结构IS1,因此其材料及配置可参考图1中的内连线结构IS1的材料及配置。在一些实施例中,内连线结构IS1可设置在半导体衬底S1的第一侧(例如,前侧)之上。具体来说,内连线结构IS1设置在器件之上且电连接到器件。在一些实施例中,内连线结构IS1包括金属间介电层及嵌入在金属间介电层中的金属特征。
图3中的结合结构BS11可相似于图1中的结合结构BS11,因此其材料及配置可参考图1中的结合结构BS11的材料及配置。在一些实施例中,结合结构BS11可设置在半导体衬底S1的第一侧(例如,前侧)之上。具体来说,结合结构BS11可设置在内连线结构IS1之上且电连接到内连线结构IS1。在一些实施例中,结合结构BS11包括至少一个结合介电层BDL11及嵌入在结合介电层BDL11中的至少一个结合金属特征。在一些实施例中,所述至少一个结合金属特征包括结合垫BP11及结合通孔BV11。具体来说,如图3中所示,一个第一管芯结构C1的结合垫BP11及结合通孔BV11电连接到插板结构I的结合结构BSi或另一个第一管芯结构C1的结合结构BS12。
在一些实施例中,第一管芯结构C1可选地包括设置在半导体衬底S1的第二侧(例如,背侧)之上的结合结构BS12。在一些实施例中,结合结构BS12包括至少一个结合介电层BDL12及嵌入在结合介电层BDL12中的至少一个结合金属特征。在一些实施例中,所述至少一个结合金属特征包括结合垫BP12及结合通孔BV12。具体来说,如图3中所示,一个第一管芯结构C1的结合垫BP12及结合通孔BV12电连接到另一个第一管芯结构C1的结合结构BS11。
在一些实施例中,第一管芯堆叠101通过包括金属对金属结合及介电质对介电质结合的混合结合而结合到插板结构I。具体来说,第一管芯堆叠101的结合垫BP11结合到插板结构I的结合垫BPia,且第一管芯堆叠101的结合介电层BDL11结合到插板结构I的结合介电层BDLi。
如图3中所示,在第一管芯堆叠101中,第一管芯结构C1以面对背配置进行堆叠。然而,本公开并不限于此,且可应用另一种面对面配置和/或背对背配置。此外,其中第一管芯堆叠101具有三个管芯结构的实施例是出于例示目的而提供,且不被解释为限制本公开。第一管芯堆叠101的管芯结构的数目不受本公开所限制。
在一些实施例中,所述两个相邻第一管芯结构C1通过包括金属对金属结合及介电质对介电质结合的混合结合而彼此结合。具体来说,一个第一管芯结构C1的结合垫BP11结合到另一个第一管芯结构C1的结合垫BP12,且一个第一管芯结构C1的结合介电层BDL11结合到另一个第一管芯结构C1的结合介电层BDL12。
在一些实施例中,第一管芯堆叠101的靠近插板结构I的最下第一管芯结构C1在其前侧及背侧处具有两个结合结构BS11及BS12,且第一管芯堆叠101的远离插板结构I的最上第一管芯结构C1在其前侧处具有一个结合结构BS11。在第一管芯堆叠101中,最上第一管芯结构C1与最下第一管芯结构C1之间的中间第一管芯结构C在其前侧及背侧处具有两个结合结构BS11及BS12。
参照图3,第二管芯堆叠201在第一管芯堆叠101旁边结合到插板结构I。第二管芯堆叠201可相似于第一管芯堆叠101,且其材料及配置可参考第一管芯堆叠101的材料及配置。第二管芯堆叠201包括垂直堆叠的多个第二管芯结构C2。第二管芯结构C2中的每一者可包括一个或多个功能性器件,例如有源组件和/或无源组件。在一些实施例中,第二管芯结构C2中的每一者可包括逻辑管芯、存储器管芯、CPU、GPU、xPU、MEMS管芯、SoC管芯等。第二管芯结构C2可相似于第一管芯结构C1,且其材料及配置可参考第一管芯结构C1的材料及配置。在一些实施例中,第二管芯结构C2包括半导体衬底S2、内连线结构IS2及至少一个结合结构。
第二管芯堆叠201和/或第二管芯结构C2的功能可与第一管芯堆叠101和/或第一管芯结构C1的功能相同。举例来说,第一管芯堆叠与第二管芯堆叠二者都是存储器堆叠,例如高带宽存储器(High Bandwidth Memory,HBM)立方体。视需要,第一管芯堆叠与第二管芯堆叠可具有不同的功能。此外,根据工艺要求,第二管芯堆叠201和/或第二管芯结构C2的尺寸可相似于或不同于第一管芯堆叠101和/或第一管芯结构C1的尺寸。尺寸可为高度、宽度、大小、俯视面积或其组合。
半导体衬底S2可相似于半导体衬底S1,因此其材料及配置可参考半导体衬底S的材料及配置。在一些实施例中,半导体衬底S2包括界定至少一个有源区域的隔离结构,且在有源区域上/有源区域中设置有至少一个器件。在一些实施例中,半导体衬底S2可具有一个或多个衬底穿孔(例如,硅穿孔)。在一些实施例中,衬底穿孔的顶部部分延伸到内连线结构IS2中,且衬底穿孔TSV2的底部部分被绝缘层环绕。
内连线结构IS2可相似于内连线结构IS1,因此其材料及配置可参考内连线结构IS1的材料及配置。在一些实施例中,内连线结构IS2可设置在半导体衬底S2的第一侧(例如,前侧)之上。具体来说,内连线结构IS2设置在器件之上且电连接到器件。在一些实施例中,内连线结构IS2包括金属间介电层及嵌入在金属间介电层中的金属特征。
结合结构BS21可相似于结合结构BS11,因此其材料及配置可参考结合结构BS11的材料及配置。在一些实施例中,结合结构BS21可设置在半导体衬底S2的第一侧(例如,前侧)之上。具体来说,结合结构BS21可设置在内连线结构IS2之上且电连接到内连线结构IS2。在一些实施例中,结合结构BS21包括至少一个结合介电层BDL21及嵌入在结合介电层BDL21中的至少一个结合金属特征。在一些实施例中,所述至少一个结合金属特征包括结合垫BP21及结合通孔BV21。具体来说,如图3中所示,一个第二管芯结构C2的结合垫BP21及结合通孔BV21电连接到插板结构I的结合结构BSi或另一个第二管芯结构C2的结合结构BS22。
在一些实施例中,第二管芯结构C2可选地包括设置在半导体衬底S2的第二侧(例如,背侧)之上的结合结构BS22。在一些实施例中,结合结构BS22包括至少一个结合介电层BDL22及嵌入在结合介电层BDL22中的至少一个结合金属特征。在一些实施例中,所述至少一个结合金属特征包括结合垫BP22及结合通孔BV22。具体来说,如图3中所示,一个第二管芯结构C2的结合垫BP22及结合通孔BV22电连接到另一个第二管芯结构C2的结合结构BS21。
在一些实施例中,第二管芯堆叠201通过包括金属对金属结合及介电质对介电质结合的混合结合而结合到插板结构I。具体来说,第二管芯堆叠201的结合垫BP21结合到插板结构I的结合垫BPib,且第二管芯堆叠201的结合介电层BDL21结合到插板结构I的结合介电层BDLi。
如图3中所示,在第二管芯堆叠201中,第二管芯结构C2以面对背配置进行堆叠。然而,本公开并不限于此,且可应用另一种面对面配置和/或背对背配置。此外,其中第二管芯堆叠201具有三个管芯结构的实施例是出于例示目的而提供,且不被解释为限制本公开。第二管芯堆叠201的管芯结构的数目不受本公开所限制。
在一些实施例中,所述两个相邻第二管芯结构C2通过包括金属对金属结合及介电质对介电质结合的混合结合而彼此结合。具体来说,一个第二管芯结构C2的结合垫BP21结合到另一个第二管芯结构C2的结合垫BP22,且一个第二管芯结构C2的结合介电层BDL21结合到另一个第二管芯结构C2的结合介电层BDL22。
在一些实施例中,第二管芯堆叠201的靠近插板结构I的最下第二管芯结构C2在其前侧及背侧处具有两个结合结构BS21及BS22,且第二管芯堆叠200的远离插板结构I的最上第二管芯结构C2在其前侧处具有一个结合结构BS21。在第二管芯堆叠201中,最上第二管芯结构C2与最下第二管芯结构C2之间的中间第二管芯结构C2在其前侧及背侧处具有两个结合结构BS21及BS22。
参照图3,集成电路结构IC1在第一管芯堆叠101及第二管芯堆叠201旁边结合到插板结构I。集成电路结构IC1可包括一个或多个功能性器件,例如有源组件和/或无源组件。在一些实施例中,集成电路结构IC1可包括逻辑管芯、存储器管芯、CPU、GPU、xPU、MEMS管芯、SoC管芯等。
集成电路结构IC1的功能可不同于第一管芯堆叠101和/或第二管芯堆叠201的功能。举例来说,第一管芯堆叠及第二管芯堆叠中的两者是存储器堆叠,而集成电路结构IC1是逻辑堆叠。视需要,集成电路结构IC1可具有与第一管芯堆叠101和/或第二管芯堆叠201的功能相同的功能。此外,根据工艺要求,集成电路结构IC1的尺寸可相似于或不同于第一管芯堆叠101和/或第二管芯堆叠201的尺寸。尺寸可为高度、宽度、大小、俯视面积或其组合。
在一些实施例中,集成电路结构IC1是单个管芯结构。图3中的集成电路结构IC1可相似于图1中的集成电路结构IC,且其材料及配置可参考图1中的集成电路结构IC的材料及配置。在一些实施例中,集成电路结构IC包括半导体衬底S3、内连线结构IS3及结合结构BS31。
图3中的半导体衬底S3及内连线结构IS3可相似于图1中的半导体衬底S及内连线结构IS,因此其材料及配置可参考图1中的半导体衬底S及内连线结构IS的材料及配置。
结合结构BS31可相似于结合结构BS11,因此其材料及配置可参考结合结构BS11的材料及配置。在一些实施例中,结合结构BS31可设置在半导体衬底S3的第一侧(例如,前侧)之上。具体来说,结合结构BS31可设置在内连线结构IS3之上且电连接到内连线结构IS3。在一些实施例中,结合结构BS31包括至少一个结合介电层BDL31及嵌入在结合介电层BDL31中的至少一个结合金属特征。在一些实施例中,所述至少一个结合金属特征包括结合垫BP31及结合通孔BV31。具体来说,如图3中所示,集成电路结构IC1的结合垫BP31及结合通孔BV31电连接到插板结构I的结合结构BSi。
在一些实施例中,集成电路结构IC1通过包括金属对金属结合及介电质对介电质结合的混合结合而结合到插板结构I。具体来说,集成电路结构IC1的结合垫BP31结合到插板结构I的结合垫BPic,且集成电路结构IC1的结合介电层BDL31结合到插板结构I的结合介电层BDLi。
参照图3,集成电路封装10中进一步包括盖体构件400。盖体构件400设置在第一管芯堆叠101、第二管芯堆叠201及集成电路结构IC1之上。在一些实施例中,盖体构件400可为包含半导体材料、无机材料、绝缘材料或其组合的衬底。举例来说,盖体构件400包含硅、陶瓷、石英等。在一些实施例中,盖体构件400是无器件构件,但本公开并不限于此。在替代实施例中,盖体构件400可为含器件构件。
在一些实施例中,在盖体构件400与第一管芯堆叠101之间进一步设置有粘合层AL1,在盖体构件400与第二管芯堆叠201之间进一步设置有粘合层AL2,且在盖体构件400与集成电路结构IC1之间进一步设置有粘合层AL3。粘合层AL1、AL2及AL3可包括氧化物层、管芯贴合胶带(die attach tape,DAF)或合适的粘合剂。
参照图3,集成电路封装10中进一步包括介电包封体E。介电包封体E形成在第一管芯堆叠101、第二管芯堆叠201及集成电路结构IC1周围。具体来说,介电包封体E填充第一管芯堆叠101、第二管芯堆叠201及集成电路结构IC1中的任意两者之间的间隙。在一些实施例中,介电包封体E包含模制化合物、模制底部填充胶、树脂等。在一些实施例中,介电包封体E包含例如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)、其组合等聚合物材料。在替代实施例中,介电包封体E包含氧化硅、氮化硅或其组合。在一些实施例中,第一管芯堆叠101、第二管芯堆叠201及集成电路结构IC1中的任意两者之间的间隙介于10μm至70μm范围内。
其中第一管芯堆叠101、第二管芯堆叠201及集成电路结构IC1中的任意两者之间的间隙填充有介电包封体E的以上实施例是出于例示目的而提供,且不被解释为限制本公开。在替代实施例中,如图3中所示,第一管芯堆叠101、第二管芯堆叠201及集成电路结构IC1中的任意两者之间的间隙可填充有空气A。所述空气可为干燥空气。所述空气可以干燥惰性气体(例如氩气)、干燥非活性气体(例如氮气)或任何合适的气体来替换。
图4至图8所示集成电路封装11至15是图3所示集成电路封装10的经修改结构,因此以下示出其之间的不同之处,且本文中不再对相似之处予以赘述。
图4所示集成电路封装11可相似于图3所示集成电路封装10,且其之间的不同之处在于,图3中的集成电路结构IC1是单个管芯结构,而图4中的集成电路结构IC2是包括多个第三管芯结构C3的第三管芯堆叠。在一些实施例中,第三管芯结构C3中的每一者包括半导体衬底S3、内连线结构IS3、结合结构BS31及可选的结合结构BS32。
如图4中所示,在集成电路结构IC2中,第三管芯结构C3以面对背配置进行堆叠。然而,本公开并不限于此,且可应用另一种面对面配置和/或背对背配置。此外,其中集成电路结构IC2具有三个管芯结构的实施例是出于例示目的而提供,且不被解释为限制本公开。集成电路结构IC2的管芯结构的数目不受本公开所限制。
在一些实施例中,两个相邻第三管芯结构C3通过包括金属对金属结合及介电质对介电质结合的混合结合而彼此结合。具体来说,一个第三管芯结构C3的结合垫结合到另一个第三管芯结构C3的另一个结合垫,且一个第三管芯结构C3的结合介电层结合到另一个第三管芯结构C3的另一个结合介电层。
图5所示集成电路封装12可相似于图3所示集成电路封装10,且其之间的不同之处在于,图3中的第一/第二管芯堆叠101/201中的第一/第二管芯结构C1/C2通过混合结合而结合,而图5中的第一/第二管芯堆叠102/202中的第一/第二管芯结构C1/C2通过焊料接头(solder joint)而结合。
在一些实施例中,第一管芯结构C1中的每一者包括半导体衬底S1、内连线结构IS1、结合垫P1及凸块B1以及可选的结合结构BS11。结合垫P1可为凸块下金属化垫。凸块B1设置在垫P1之上且电连接到垫P1,且因此电连接到内连线结构IS1。在一些实施例中,凸块B1包含铜、焊料、镍或其组合。在一些实施例中,凸块B1可为焊球、微凸块受控塌陷芯片连接(C4)凸块、球栅阵列(BGA)球、微凸块、化学镀镍钯浸金技术(ENEPIG)形成的凸块、铜柱、混合结合凸块等。在一些实施例中,凸块B1的尺寸小于凸块Bi的尺寸。举例来说,凸块Bi的尺寸是凸块B1的尺寸的约5至15倍。
在一些实施例中,第一管芯堆叠102的靠近插板结构I的最下第一管芯结构C1在其前侧处具有结合结构BS11且在其背侧处具有焊料凸块B1,且第一管芯堆叠102的远离插板结构I的最上第一管芯结构C1在其前侧处具有焊料凸块B1。在第一管芯堆叠102中,最上第一管芯结构C1与最下第一管芯结构C1之间的中间第一管芯结构C1在其前侧及背侧处具有焊料凸块B1。
在一些实施例中,第一管芯堆叠102中进一步包括底部填充层UF1。底部填充层UF1被形成为环绕凸块B1且填充所述两个相邻第一管芯结构C1之间的空间。在一些实施例中,底部填充层UF1包含例如环氧树脂等模制化合物。
在一些实施例中,第二管芯结构C2中的每一者包括半导体衬底S2、内连线结构IS2、结合垫P2及凸块B2以及可选的结合结构BS21。结合垫P2可为凸块下金属化垫。凸块B2设置在垫P2之上且电连接到垫P2,且因此电连接到内连线结构IS2。在一些实施例中,凸块B2包含铜、焊料、镍或其组合。在一些实施例中,凸块B2可为焊球、微凸块受控塌陷芯片连接(C4)凸块、球栅阵列(BGA)球、微凸块、化学镀镍钯浸金技术(ENEPIG)形成的凸块、铜柱、混合结合凸块等。在一些实施例中,凸块B2的尺寸小于凸块Bi的尺寸。举例来说,凸块Bi的尺寸是凸块B2的尺寸的约5至15倍。
在一些实施例中,第二管芯堆叠202的靠近插板结构I的最下第二管芯结构C2在其前侧处具有结合结构BS21且在其背侧处具有焊料凸块B2,且第二管芯堆叠202的远离插板结构I的最上第二管芯结构C2在其前侧处具有焊料凸块B2。在第二管芯堆叠202中,最上第二管芯结构C2与最下第二管芯结构C2之间的中间第二管芯结构C2在其前侧及背侧处具有焊料凸块B2。
在一些实施例中,第二管芯堆叠202中进一步包括底部填充层UF2。底部填充层UF2被形成为环绕凸块B2且填充所述两个相邻第二管芯结构C2之间的空间。在一些实施例中,底部填充层UF2包含例如环氧树脂等模制化合物。
图6至图8所示集成电路封装13至15可相似于图3至图5所示集成电路封装10至12,且其之间的不同之处在于,图3至图5所示集成电路封装10至12中的每一者设置有盖体构件400,而图6至图8所示集成电路封装13至15中的每一者不设置有盖体构件400。在图6至图8所示集成电路封装13至15中的每一者中,第一管芯堆叠101/102、第二管芯堆叠201/202及集成电路结构IC1/IC2中的任意两者之间的间隙填充有介电包封体E,以有效地保护封装免于损伤。
图9A至图9D是根据替代实施例的形成集成电路封装的方法的简化剖视图。为使例示简单及清晰,在图9A至图9D所示剖视图中示出仅几个元件。据理解,本公开不受以下所述方法所限制。可在所述方法之前、期间和/或之后提供附加操作且可替换或去除以下所述操作中的一些操作,以获得所述方法的附加实施例。
参照图9A,提供插板结构I。在一些实施例中,插板结构I包括半导体衬底Si、位于半导体衬底Si之上的重布线层结构RDLi及位于重布线层结构RDLi之上的毯覆结合结构BSi。
此后,在插板结构I之上提供具有结合结构B11的第一管芯堆叠101/102、具有结合结构BS21的第二管芯堆叠201/202及具有结合结构BS31的集成电路结构IC1/IC2。在一些实施例中,可首先执行与图2A至图2B中的操作相似的操作,以形成第一管芯堆叠101/102及第二管芯堆叠201/202。具体来说,将第一管芯结构C1逐一地堆叠在载体衬底上以形成第一管芯堆叠101/102,将第二管芯结构C2逐一地堆叠在载体衬底上以形成第二管芯堆叠201/202,并移除载体衬底。在一些实施例中,当提供集成电路结构IC1/IC2作为管芯堆叠时,可在堆叠第一管芯结构C1及第二管芯结构C2的操作期间形成集成电路结构IC1/IC2。
参照图9B,通过包括金属对金属结合及介电质对介电质结合的混合结合将第一管芯堆叠101/102、第二管芯堆叠201/202及集成电路结构IC1/IC2结合到插板结构I。在一些实施例中,将第一管芯堆叠101/102、第二管芯堆叠201/202及集成电路结构IC1/IC2的相应结合结构BS11、BS21及BS31结合到插板结构I的毯覆结合结构BSi。
参照图9C,移除插板结构I的硅部分。在一些实施例中,插板结构I的半导体衬底Si被完全移除。
参照图9D,形成凸块Bi以电连接到重布线层结构RDLi。因此,提供一种具有无硅插板结构的集成电路封装。在一些实施例中,可选地形成盖体构件400以覆盖第一管芯堆叠101/102的顶部、第二管芯堆叠201/202的顶部及集成电路结构IC1/IC2的顶部。
由于硅衬底是半导电的,因此其可能负面地影响形成在其中及形成在其上的电路及连接的性能。举例来说,硅衬底可能造成信号劣化(signal degradation)。在本公开的一些实施例中,提供一种无硅插板结构,且这种无硅插板结构有益于减小封装大小,降低信号劣化并改善封装性能。在一些实施例中,不再使用传统的焊料接头,而是通过混合结合将两个或更多个管芯堆叠结合到插板结构,因此封装大小可进一步减小。
图10至图15是根据又一些替代实施例的各种集成电路封装的剖视图。
图10至图15所示集成电路封装20至25相似于图3至图8所示集成电路封装10至15,其之间的不同之处在于,图3至图8所示集成电路封装10至15中的每一者的插板结构I是无硅插板,而图10至图15所示集成电路封装20至25中的每一者的插板结构I是含硅插板。在一些实施例中,图10至图15所示集成电路封装20至25中的每一者的插板结构I包括半导体衬底Si、衬底穿孔TSVi、重布线层结构RDLi及毯覆结合结构BSi。在一些实施例中,衬底穿孔TSVi延伸到重布线层结构RDLi中且搭接在重布线层结构RDLi的金属垫上。
在一些实施例中,图10至图15所示集成电路封装20至25中的每一者的插板结构I中进一步包括凸块下金属化垫UBMi及凸块Bi。凸块下金属化垫UBMi及凸块Bi电连接到重布线层结构RDLi。
图16A至图16C是根据又一些替代实施例的形成集成电路封装的方法的简化剖视图。为使例示简单及清晰,在图16A至图16C所示剖视图中示出仅几个元件。据理解,本公开不受以下所述方法所限制。可在所述方法之前、期间和/或之后提供附加操作且可替换或去除以下所述操作中的一些操作,以获得所述方法的附加实施例。
参照图16A,提供插板结构I。在一些实施例中,插板结构I包括半导体衬底Si、位于半导体衬底Si之上的重布线层结构RDLi及位于重布线层结构RDLi之上的毯覆结合结构BSi。在一些实施例中,半导体衬底Si包括衬底穿孔TSVi(例如,硅穿孔)。
此后,在插板结构I之上提供具有结合结构B11的第一管芯堆叠101/102、具有结合结构BS21的第二管芯堆叠201/202及具有结合结构BS31的集成电路结构IC1/IC2。
参照图16B,通过包括金属对金属结合及介电质对介电质结合的混合结合将第一管芯堆叠101/102、第二管芯堆叠201/202及集成电路结构IC1/IC2结合到插板结构I。在一些实施例中,将第一管芯堆叠101/201、第二管芯堆叠201/202及集成电路结构IC1/IC2的相应结合结构BS11、BS21及BS31结合到插板结构I的毯覆结合结构BSi。
参照图16C,形成凸块Bi以电连接到衬底穿孔TSVi,且因此电连接到重布线层结构RDLi。因此,提供一种具有含硅插板结构的集成电路封装。在一些实施例中,可选地形成盖体构件400以覆盖第一管芯堆叠101/102的顶部、第二管芯堆叠201/202的顶部及集成电路结构IC1/IC2的顶部。
在一些实施例中,不再使用传统的焊料接头,而是通过混合结合将两个或更多个管芯堆叠结合到插板结构,因此封装大小可进一步减小。
本公开考虑到以上实例的许多变型。据理解,不同的实施例可具有不同的优点,且所有实施例未必需要特定优点。
根据本公开的一些实施例,一种集成电路封装包括集成电路结构、第一管芯堆叠及虚设管芯。第一管芯堆叠包括多个第一管芯结构且在第一管芯堆叠的第一侧处结合到集成电路结构。虚设管芯包括多个衬底穿孔,位于第一管芯堆叠旁边且在第一管芯堆叠的第一侧处电连接到集成电路结构。在一些实施例中,虚设管芯的衬底穿孔的高度与第一管芯堆叠的高度相同。
在一些实施例中,所述集成电路封装进一步包括:重布线层结构,在所述第一管芯堆叠的第二侧处电连接到所述第一管芯堆叠,其中所述第二侧与所述第一管芯堆叠的所述第一侧相对;以及多个凸块,电连接到所述重布线层结构。在一些实施例中,所述第一管芯堆叠通过包括金属对金属结合及介电质对介电质结合的混合结合而结合到所述集成电路结构。在一些实施例中,所述第一管芯堆叠与所述虚设管芯之间的间隙填充有介电包封体。在一些实施例中,所述第一管芯堆叠与所述虚设管芯之间的间隙填充有空气。在一些实施例中,所述第一管芯堆叠中的两个相邻第一管芯结构通过包括金属对金属结合及介电质对介电质结合的混合结合而结合。在一些实施例中,所述集成电路封装进一步包括:第二管芯堆叠,包括多个第二管芯结构且在所述第一管芯堆叠的所述第一侧处结合到所述集成电路结构,其中所述虚设管芯的所述衬底穿孔的所述高度与所述第二管芯堆叠的高度相同。
根据本公开的替代实施例,一种集成电路封装包括插板结构、第一管芯堆叠及第二管芯堆叠。第一管芯堆叠包括多个第一管芯结构且通过包括金属对金属结合及介电质对介电质结合的混合结合而结合到插板结构。第二管芯堆叠包括多个第二管芯结构且通过包括金属对金属结合及介电质对介电质结合的混合结合而结合到插板结构。
在一些实施例中,所述插板结构是无硅插板结构。在一些实施例中,所述集成电路封装进一步包括集成电路结构,所述集成电路结构位于所述第一管芯堆叠与所述第二管芯堆叠之间且通过包括金属对金属结合及介电质对介电质结合的混合结合而结合到所述插板结构。在一些实施例中,所述集成电路结构是单个管芯结构。在一些实施例中,所述集成电路结构是包括多个第三管芯结构的第三管芯堆叠。在一些实施例中,所述第一管芯堆叠、所述第二管芯堆叠及所述集成电路结构中的任意两者之间的间隙填充有介电包封体。在一些实施例中,所述集成电路封装进一步包括盖体构件,所述盖体构件位于所述第一管芯堆叠及所述第二管芯堆叠之上。在一些实施例中,所述第一管芯堆叠与所述第二管芯堆叠之间的间隙填充有介电包封体或空气。在一些实施例中,所述第一管芯堆叠中的两个相邻第一管芯结构通过包括金属对金属结合及介电质对介电质结合的混合结合而结合,且所述第二管芯堆叠中的两个相邻第二管芯结构通过包括金属对金属结合及介电质对介电质结合的混合结合而结合。在一些实施例中,所述第一管芯堆叠中的两个相邻第一管芯结构通过焊料接头而结合,且所述第二管芯堆叠中的两个相邻第二管芯结构通过焊料接头而结合。
根据本公开的又一些替代实施例,一种形成集成电路封装的方法包括以下操作。提供具有毯覆结合结构的插板结构。提供具有第一结合结构的第一管芯堆叠、具有第二结合结构的第二管芯堆叠及具有第三结合结构的集成电路结构。通过包括金属对金属结合及介电质对介电质结合的混合结合将第一管芯堆叠、第二管芯堆叠及集成电路结构结合到插板结构,其中将第一管芯堆叠的第一结合结构、第二管芯堆叠的第二结合结构及集成电路结构的第三结合结构结合到插板结构的毯覆结合结构。移除插板结构的硅部分。
在一些实施例中,所述第一管芯堆叠及所述第二管芯堆叠是通过包括以下的方法形成:将第一管芯结构逐一地堆叠在载体衬底上,以形成所述第一管芯堆叠;将第二管芯结构逐一地堆叠在所述载体衬底上,以形成所述第二管芯堆叠;以及移除所述载体衬底。在一些实施例中,所述形成集成电路封装的方法进一步包括在所述第一管芯堆叠、所述第二管芯堆叠及所述集成电路结构之上形成盖体构件。
也可包括其他特征及工艺。举例来说,可包括测试结构,以帮助对三维(three-dimensional,3D)封装或3DIC器件进行验证测试。所述测试结构可例如包括在重布线层中或在衬底上形成的测试垫,以使得能够对3D封装或3DIC进行测试、对探针和/或探针卡(probe card)进行使用等。可对中间结构以及最终结构执行验证测试。另外,本文中所公开的结构及方法可结合包括对已知良好管芯(known good die)进行中间验证的测试方法来使用,以提高良率并降低成本。
以上概述了若干实施例的特征,以使所属领域中的技术人员可更好地理解本公开的方面。所属领域中的技术人员应理解,其可容易地使用本公开作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的和/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到,这些等效构造并不背离本公开的精神及范围,而且他们可在不背离本公开的精神及范围的条件下对其作出各种改变、代替及变更。
Claims (1)
1.一种集成电路封装,包括:
集成电路结构;
第一管芯堆叠,包括多个第一管芯结构且在所述第一管芯堆叠的第一侧处结合到所述集成电路结构;以及
虚设管芯,包括多个衬底穿孔,位于所述第一管芯堆叠旁边且在所述第一管芯堆叠的所述第一侧处电连接到所述集成电路结构,其中所述虚设管芯的所述衬底穿孔的高度与所述第一管芯堆叠的高度相同。
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