TW202312377A - 半導體封裝及其製造方法 - Google Patents

半導體封裝及其製造方法 Download PDF

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TW202312377A
TW202312377A TW111101458A TW111101458A TW202312377A TW 202312377 A TW202312377 A TW 202312377A TW 111101458 A TW111101458 A TW 111101458A TW 111101458 A TW111101458 A TW 111101458A TW 202312377 A TW202312377 A TW 202312377A
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cavity
semiconductor
die
circuit substrate
redistribution layer
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TW111101458A
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TWI788189B (zh
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林孟良
莊博堯
翁得期
陳碩懋
鄭心圃
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台灣積體電路製造股份有限公司
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Publication of TW202312377A publication Critical patent/TW202312377A/zh

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Abstract

提供半導體封裝以及其製造方法。半導體封裝至少包括電路基底、半導體晶粒和填充材料。電路基底有第一表面、與所述第一表面相反的第二表面和從所述第一表面凹進去的凹穴。電路基底包括介電材料和埋設在介電材料中並位於凹穴下方的金屬底板。金屬底板的位置對應於凹穴的位置。金屬底板是電性浮置的並被介電材料隔離。半導體晶粒設置在凹穴中，且與電路基底電性連接。填充材料設置在半導體晶粒和電路基底之間。填充材料填充凹穴且封裝半導體晶粒，而連接半導體晶粒和電路基底。

Description

半導體封裝及其製造方法
半導體晶粒可以與其他半導體元件或晶粒加工封裝，封裝的尺寸大小是由半導體晶粒和/或其他元件的安排配置所決定。
以下揭露內容提供用以實施本發明的不同特徵的許多不同實施例或實例。下文描述組件及配置的特定實例以簡化本揭露內容。當然，此等組件及配置僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或第二特徵上的形成可包含第一特徵及第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第一特徵與第二特徵之間形成以使得第一特徵與第二特徵可不直接接觸的實施例。另外，本揭露內容可在各種實例中重複附圖標號及/或字母。此重複是出於簡單及清楚的目的，且本身並不指示所論述的各種實施例及/或組態之間的關係。
此外，本文中為了易於描述，可使用諸如「在...之下（underlying）」、「下方（below）」、「下部（lower）」、「在…之上（overlying）」、「上部（upper）」以及類似術語的空間相對術語來描述如圖式中所示出的一個元件或特徵與另一元件或特徵的關係。除圖式中所描繪的定向之外，空間相對術語亦意欲涵蓋元件在使用或操作中的不同定向。裝置可以其他方式定向（旋轉90度或處於其他定向），且本文中所使用的空間相對描述詞可同樣相應地進行解釋。
還可包括其他特徵及製程。舉例來說，可包括測試結構來輔助對三維（3D）封裝或三維積體電路（three dimensional integrated circuit，3DIC）器件進行驗證測試。測試結構可包括例如形成在重佈線層中或形成在基底上的測試焊盤，所述測試焊盤使得能夠對3D封裝或3DIC進行測試、對探針和/或探針卡進行使用等。可對中間結構及最終結構執行驗證測試。另外，本文中所公開的結構及方法可與測試方法結合使用，所述測試方法包括在中間階段驗證出已知良好的晶粒以提高良率（yield）且降低成本。
圖1到圖6是根據本公開的一些示例性實施例在半導體封裝的製造方法中的各階段的示意性剖視圖。在一些實施例中，一個或多個晶粒可表示多個晶粒，半導體製造方法所得到的一個或多個封裝可表示多個半導體封裝。
參考圖1，在一些實施例中，提供了其上具有剝離層(未示出)的載體102。在某些實施例中，載體102是半導體基底，例如本體矽晶圓或玻璃基底。舉例來說，剝離層可包括光熱轉化(LTHC)離型層。
參考圖1，在一些實施例中，在載體102上形成了重佈線層110。重佈線層110的形成包括相繼地交替形成一層以上的介電材料層和一層以上的金屬化層。參考圖1，在某些實施例中，重佈線層110的形成包括相繼地形成第一介電材料層112、第一金屬化層113、第二介電材料層114、第二金屬化層115、第三介電材料層116、第三金屬化層117、第四介電材料層118和接合部分119。在一些實施例中，重佈線層110的形成還包括形成介電材料層（未示出）、圖案化介電材料層以形成開口，沉積金屬材料填充開口以形成金屬化圖形。在一些實施例中，金屬化層113、115、117和接合部分119是電性互連的。
在一些實施例中，介電材料層112、114、116、118的材料可以相同或不同。在一些實施例中，介電材料層112、114、116、118的材料包括一種或多種聚合物介電材料，例如聚醯亞胺、苯並環丁烯(BCB)、聚苯並惡唑(PBO)或任何其他合適的基於聚合物的介電材料。在一些實施例中，金屬化層113、115、117和接合部分119的材料可以相同或不同，金屬化層113、115、117和接合部分119的材料可以選自銅、鈷、鎳、鋁、鎢或其組合。在一些實施例中，金屬化層113、115、117可以包括路由跡線或扇出跡線。在一些實施例中，第一金屬化層113可能包括鍵合部分113B和墊113P。在一些實施例中，第三金屬化層117可以包括與接合部分119相連的接觸墊117P，用於接收凸塊或其他組件。在一些實施例中，接合部分119進一步可選地包括在接合部分的表面上形成的用於增強鍵合的附著層、種晶層、預先焊料、焊料膏和/或凸塊下金屬(UBM)圖案。
參考圖2，提供兩個或多個半導體晶粒120並放置在載體102之上的重佈線層110之上。在圖2中，僅示出了兩個晶粒作為封裝結構的示例性晶粒，但是應當理解，在封裝結構內可以包括多於兩個晶粒或不同類型的晶粒。在一些實施例中，晶粒120中的一個或多個包括一個或多個存儲晶片，例如高頻寬記憶體晶片、動態隨機存取記憶體（DRAM）晶片或靜態隨機存取記憶體（SRAM）晶片。在一些實施例中，晶粒120中的一個或多個可以包括專用積體電路（ASIC）晶片、類比晶片、感測器晶片、無線應用晶片（例如藍牙晶片或射頻（RF）晶片）或電壓調節器晶片中的一個或多個。在一些實施例中，晶粒120之一可能是包括存儲晶片的記憶體晶粒，而另一個晶粒120可能是包括控制器晶片的系統級晶片(SoC)晶粒。在某些實施例中，晶粒和晶片可以互換使用。
在某些實施例，如在圖2中，設有接觸點122的半導體晶粒120朝下，半導體晶粒120的接觸點122與重佈線層110的接合部分119鍵合。在一實施例中，半導體晶粒120到重佈線層110的鍵合包括執行回流焊接製程透過焊料焊劑鍵合接觸點122和接合部分119。在一些實施例中，接觸點122是金屬柱條、微凸塊、銅柱、銅合金柱或其他合適的金屬連接件。在某些實施例中，半導體晶粒120並排安裝在載體102之上的重佈線層110上，並且並排或堆疊在另外晶粒之上佈置的晶粒的數量可以在產品設計的基礎上進行調整或修改，但是不受示例性實施例限制。在某些實施例中，底充膠126填充在半導體晶粒120和重佈線層110之間，包封了鍵合的接觸點122和接合部分119，以獲得更好的貼合黏著。在某些實施例中，底充膠126至少部分填充了半導體晶粒120之間的空隙。
參考圖3，在一些實施例中，位於重佈線層110上的半導體晶粒120被模壓封裝在模製化合物130中，形成模封結構MS。在實施例中，模製化合物130填充了晶粒120之間的空間，至少側向地覆蓋填充了重佈線層110上的晶粒120。在實施例中，模製化合物130的材料包括環氧樹脂、酚類樹脂或含矽的樹脂。在某些實施例中，模製化合物130的材料包括填充物顆粒。在某些實施例中，模製化合物130包覆成型然後平坦化，直到晶粒120露出背表面120B。在某些實施例中，對包覆模塑成型的模製化合物130進行研磨，直到暴露出晶粒120的背表面120B。在實施例中，在平坦化之後，模製化合物130的頂表面130T和晶粒120的背表面120B變成實質上彼此齊平。在某些實施例中，模製化合物130透過研磨製程或化學機械研磨(CMP)製程進行平坦化。
參考圖4，在一些實施例中，貼合另一載體104到模封結構MS（貼合到晶粒120的背表面120B）之後，整個結構被顛倒（翻轉），利用剝離層（未顯示）使載體102與模封結構MS分離，然後移除。載體102與模封結構MS分離後，包括鍵合部分113B和墊113P在內的第一金屬化層113從重佈線層110的表面110S暴露出來。
在一些實施例中，如圖5，另一個半導體晶粒140與重佈線層110鍵合，導電件150形成在重佈線層110上。在一些實施例中，半導體晶粒140有第一高度H1（從表面110S厚度方向垂直測量），導電件150有第二高度H2（從表面110S厚度方向垂直測量），第二高度H2比第一高度H1小。在某些實施例中，導電件150是設置在半導體晶粒140旁邊。有的實施例，半導體晶粒140的接觸點142是朝下的，半導體晶粒140是裝在重佈線層110的第一金屬化層113上的。在某些實施例中，半導體晶粒140與重佈線層110鍵合，半導體晶粒140的接觸點142鍵合且連接到重佈線層110的鍵合部分113B。在某些實施例中，半導體晶粒140的接觸點142的尺寸或大小大於半導體晶粒120的接觸點122的尺寸或大小。在一些實施例中，接觸點142是金屬柱條、微凸塊、銅柱、銅合金柱或其他合適的金屬連接件。在圖5中，僅示出了一個半導體晶粒作為封裝結構的示例性晶粒，但是應當理解，在封裝結構內可以包括兩個或更多個晶粒或不同類型的半導體晶粒。在某些實施例中，在半導體晶粒140和重佈線層110之間形成底充膠146，並封裝了鍵合的接觸點142和鍵合部分113B，以獲得更好的貼合黏著。在實施例中，半導體晶粒140到重佈線層110的鍵合包括執行回流焊接製程透過焊料焊劑鍵合接觸點142和鍵合部分113B。在某些實施例中，導電件150設置在第一金屬化層113上，並且透過執行植球製程和回流焊接製程固定到接觸墊113P。實施例中，導電件150可為例如微凸塊、金屬柱、具焊料膏金屬柱、化學鍍鎳化學鍍鈀沉金（ENEPIG）形成的凸塊，或受控塌陷晶片連接（C4）凸塊。如圖5所示，部分導電件150透過重佈線層110電性連接到半導體晶粒120，部分導電件150透過重佈線層110電性連接到半導體晶粒140。在某些實施例中，半導體晶粒140透過重佈線層110電性連接到半導體晶粒120，半導體晶粒120與重佈線層110是電性連接的。在一些實施例中，半導體晶粒140可包括一個或多個被動元件，例如電容器、電感或電阻器。在某些實施例中，半導體晶粒140可能包括整合被動元件(IPD)。
參考圖6，在一些實施例中，沿著切割道（未示出），執行切割製程以將整個結構（至少切割通過重佈線層110和模製化合物130）切割成單獨的和分離的半導體封裝10。在實施例中，切割製程可以包括晶圓切割製程，包括機械鋸切（mechanical ablation）或鐳射切割（laser ablation）。在某些實施例中，移除了載體104。
圖7到圖9是根據本公開的一些實施例的半導體封裝的示意性平面視圖。需要注意的是，圖7至圖9中的封裝單元或結構僅用於說明，圖7至圖9中的實施例在結構描述可參照圖1至圖6，且包括在本公開的預期範圍內。
參考圖7，封裝結構70與前面實施例中顯示的封裝結構10類似，但簡化了插圖以顯示封裝結構70中半導體晶粒的相對配置。在某些實施例中，半導體晶粒740和半導體晶粒700A以及700B位於重佈線層710的兩個相對的側處。從圖7中可以看出，半導體晶粒700A和700B以並排排列並位於重佈線層710下方，另一個半導體晶粒740安裝在重佈線層710上，位於下方兩個半導體晶粒700A、700B之間的中心位置。在一些實施例中，半導體晶粒700A和700B是同類型的晶粒，半導體晶粒700A、700B和740是不同類型的晶粒。在一些實施例中，半導體晶粒700A和700B是不同類型的晶粒，半導體晶粒700A、700B和740是不同類型的晶粒。從圖7的平面視圖來看，晶粒700A或700B具有長度L700和寬度W700，晶粒740具有長度L740和寬度W740。在圖7中，在某些實施例中，半導體晶粒740的垂直投影（沿厚度方向）與半導體晶粒700A和700B都部分重疊。在一些實施例中，半導體晶粒740的跨度沿著半導體晶粒700A、700B的相鄰長側延展且從一個半導體晶粒700A延伸到另一個半導體晶粒700B，使得半導體晶粒740交疊半導體晶粒700A和700B。在實施例中，長度L700大於長度L740，L740/L700範圍的比例從大約0.1到大約0.95。在實施例中，寬度L740小於寬度W700但大於半導體晶粒700A和700B之間的空隙的寬度Wg。在實施例中，空隙寬度Wg的範圍從大約1微米到大約200微米。
參考圖8，封裝結構80與前面實施例中顯示的封裝結構10類似，但簡化了插圖以顯示封裝結構80中半導體晶粒的相對配置。在一些實施例中，半導體晶粒840A、840B和半導體晶粒800A和800B位於重佈線層810的兩個相對的側處。如在圖8中所見，半導體晶粒800A和800B以並排排列並位於重佈線層810的底側下，而半導體晶粒840A、840B安裝在重佈線層810的頂側上，位於下面兩個半導體晶粒800A、800B之間的中心位置。實施例中，半導體晶粒800A和800B是同類型的晶粒，半導體晶粒840A、840B是同類型的晶粒但與晶粒800A、800B不同。在實施例中，半導體晶粒800A和800B是不同類型的晶粒，半導體晶粒840A、840B是不同類型的晶粒且與晶粒800A、800B不同。從圖8的平面視圖來看，晶粒800A或800B具有長度L800和寬度W800，晶粒840A或840B具有長度L840和寬度W840。在圖8中，在某些實施例中，半導體晶粒840A或840B的垂直投影（沿厚度方向）與半導體晶粒800A和800B部分重疊。在一些實施例中，介於半導體晶粒840A和840B之間間距範圍從大約1微米到大約1000微米。在實施例中，長度L800比長度L840大，寬度L840比寬度W800小但比介於半導體晶粒800A和800B之間空隙的寬度Wg大。
參考圖9，封裝結構90類似於前面實施例中顯示的封裝結構10，但簡化了圖示以顯示封裝結構90中半導體晶粒的相對配置。在一些實施例中，半導體晶粒940A、940B、940C、940D和半導體晶粒900A、900B分別位於重佈線層910的兩個相對的側處。從圖9中可以看出，半導體晶粒900A和900B以並排排列並位於重佈線層910的底側處，而半導體晶粒940A、940B、940C、940D則安裝在重佈線層910的頂側上，並位於底層兩個半導體晶粒900A、900B之間的中心位置。在實施例中，半導體晶粒940A、940B、940C、940D是同類型的晶粒，但與晶粒900A、900B不同類型。在實施例中，半導體晶粒900A和900B是不同類型的晶粒，半導體晶粒940A、940B、940C、940D是不同類型的晶粒，且與晶粒900A、900B不同類型。在圖9中，在某些實施例中，半導體晶粒940A、940B、940C或940D的垂直投影（沿厚度方向）與半導體晶粒900A和900B均部分重疊。在一些實施例中，半導體晶粒940A、940B、940C、940D之間的間距範圍從約1微米到約1000微米。在實施例中，半導體晶粒940A、940B、940C、940D中的任何一個的寬度都比半導體晶粒900A和900B之間的空隙的寬度Wg大。相鄰晶粒940A、940B、940C、940D之間的間距可以在產品設計的基礎上進行調整。
圖10至圖13是根據本公開的一些示例性實施例在連接到電路基底的半導體封裝的製造方法中的各階段處所形成的結構的示意性剖視圖。圖13A是示意性剖視圖，說明根據本公開的一些實施例連接到電路基底的半導體封裝。圖14A是示意性放大部分剖視圖，顯示根據本公開的一些示例性實施例的半導體封裝結構的連接的部分。圖14B是示意性放大部分剖視圖，顯示根據本公開的一些示例性實施例連接到電路基底的半導體封裝結構的另一個連接的部分。圖15A和圖15B是示意性平面視圖，顯示根據本公開的一些實施例連接到電路基底的半導體封裝中的底板和凹穴的相對構造。應注意，圖14A至圖15B中所示的構造僅用於說明，而這些構造或方案在結構描述參照圖10至圖13，也包括在本公開的預期範圍內。
在某些實施例中，參考圖10，提供了電路基底600。在某些實施例中，電路基底600包括積層板、印刷電路板、層疊板或可撓層合板。在一些實施例中，電路基底600可包括一個或多個主動元件、被動元件或不同組合於其中。在一些實施例中，舉例來說，電路基底600包括了介電材料601、金屬化圖形602、貫穿通孔604以及鍵合墊606與 608連接到金屬化層602和通孔604來提供雙側電性連接。在某些實施例中，金屬化圖形602包括埋設在介電材料601中的一個或多個底板605。如圖10右側的上方放大平面視圖，在某些實施例中，底板605包括三個長條板，它們彼此間隔並具有距離Ss並平行排列。在實施例中，距離Ss範圍從大約1微米到大約200微米。在實施例中，如在圖10中左側側處的放大平面視圖中所見，底板605是帶有開口或帶有網格圖案的單一金屬板。在一些實施例中，金屬化圖形602被設計成電性連接各種元件，例如埋設於電路基底中的主動元件和/或被動元件以形成功能性電路。在某些實施例中，接合連結物610是在電路基底600的頂表面600T上的鍵合墊606上形成的。在一些實施例中，接合連結物610包括焊料或預先焊料、微凸塊、金屬柱或金屬柱條與焊料膏。在一些實施例中，導電球620可以形成在電路基底600的底表面600B上的接觸墊608上，進一步的電性連接。在一些實施例中，導電球620包括焊料球、球柵陣列（BGA）連接件、受控塌陷晶片連接（C4）凸塊。
在一些實施例中，材料包括金屬化圖形，材料包括銅、鋁、鎳、鈷、金、銀、鎢、其組合或其類似物。在實施例中，介電材料601包括有機介電材料。在某些實施例中，介電材料601可能包括味之素（Ajinomoto）增層膜、聚合物材料（例如，聚醯亞胺、聚酯、苯並環丁烯、聚苯並惡唑、或其類似物）、預浸料、樹脂塗層銅(RCC)、光圖像介電材料(PID)、酚醛紙、酚醛棉紙、玻璃纖維編織布、浸漬玻璃纖維編織布、模製化合物或組合。在一些實施例中，電路基底600的介電材料601可以透過壓模法、包覆模塑和平坦化、層疊或其他合適的技術形成。在一些實施例，金屬化圖形602、通孔604和墊606與608可以透過鍍覆製程例如電鍍覆、化學鍍、浸入鍍覆或其類似物中的一或多種所形成。
在一些實施例中，參考圖11，在電路基底600中形成凹穴CV。在圖11中，在某些實施例中，凹穴CV以深度Dcv（從頂表面600T測量）凹入電路基底600，並在到達底板605之前停止。在某些實施例中，凹穴CV具有寬度Wcv，範圍從大約10微米到大約10釐米。在某些實施例中，凹穴的尺寸足夠大，可以容納後來設置的晶粒或封裝單元。在實施例中，凹穴CV是透過對電路基底600進行機械燒蝕製程或鐳射燒蝕製程而形成的，從頂表面600T中去除介電材料601的部分，形成電路基底600中的凹穴CV。在某些實施例中，凹穴CV是在不存在金屬化圖形或佈線的排除區（keep-out region）中形成的，而凹穴CV的形成僅涉及去除區中的介電材料601。即凹穴CV露出的表面是無金屬化（無金屬）的介電表面。在一些實施例中，埋設介電材料601中的底板605位於排除區下方，而凹穴CV是透過去除底板605上方的介電材料601而形成的。在實施例中，在凹穴CV的形成過程中，介電層601的去除在到達底板605之前在一特定距離處停止，而底板605可作為緩衝或阻擋層甚至是標記，以精確控制移除製程。在實施例中，由於凹穴CV是透過去除介電材料601而不是金屬材料形成的，因此凹穴CV的尺寸得到了更好的表面平面性控制。在實施例中，凹穴CV的底與底板605以距離Ds隔開。在實施例中，間距距離Ds範圍從大約1微米到大約100微米。換句話說，凹穴的底和底板605之間的介電材料601夾層具有範圍從大約1微米到大約100微米的厚度。在某些實施例中，在圖10和圖11中，形狀為三個長條的底板605位於凹穴CV的正下方，而底板605是電性浮置的，並以介電材料601而與其他金屬化圖形602電性隔離。在某些實施例中，凹穴CV的位置對應於底板605的分佈位置。
參考圖15A和圖15B，相對於結合到電路基底600的封裝結構10，顯示出底板605和凹穴CV的構造和位置，但是某些組件被省略並且圖示被簡化。參考圖11和圖15A的平面視圖，可以看出凹穴CV的跨度與底板605的跨度完全重疊。在實施例中，底板605的跨度大於凹穴CV的跨度，從平面視圖來看，底板605的分佈跨度和凹穴CV的跨度呈同心（同環）排列。應當理解，這裡示出了一個凹穴作為示例，但是多於一個凹穴也是可能的，並且可以根據要容納到凹穴中的晶粒的形狀和數量來修改電路基底中形成的凹穴形狀與大小。從圖15B的平面視圖來看，有兩凹穴CV1和CV2容納兩個半導體晶粒140，底板605位於凹穴CV2之下，底板跨度比凹穴CV2的跨度大。在某些實施例中，凹穴CV1之下沒有底板，但其他功能金屬化圖形可能存在於凹穴CV1之下。
在某些實施例中，如圖12中所示，與圖6中描述的封裝單元相似的封裝結構10安裝到電路基底600的頂表面600T上，而封裝結構10透過接合連結物610和連接件150連接到電路基底600的墊606。在某些實施例中，透過執行回流焊接製程，封裝結構10的連接件150和基底600的接合連結物610接合且融合在一起成為融合的連接件630。在某些實施例中，回流焊接製程包括執行熱製程將連接件150變成熔化的狀態或半熔化的狀態以與接合連結物610整合鍵合成為位於封裝結構10和電路基底600之間的融合連接件630。回流焊接溫度可以高於連接件150和/或接合連結物610的熔融點。在某些實施例中，導電球620的尺寸或大小大於連接件630的尺寸或大小，連接件630大於封裝結構10中的接觸點142和122。透過這些導電性連接配置，精細節距的半導體晶粒120電性連接到較大節距的半導體晶粒140和更大節距的電路基底600。
鍵合封裝結構10與電路基底600之後，半導體晶粒140位於凹穴CV中。由於電路基底中的凹穴容納了安裝到電路基底的封裝單元突出的晶粒，因此整個封裝結構的總厚度可能會減少。從圖12中可以看出，凹穴CV的尺寸大於半導體晶粒140，半導體晶粒140與凹穴CV的側壁和底部間隔開來而之間有空間存在。在某些實施例中，半導體晶粒140的背表面140S與凹穴CV的底面相隔一距離Dt，距離Dt範圍從約1微米到約100微米。舉例來說，距離Dt比凹穴的深度Dcv小，且Dt/Dcv比例範圍約0.1至約0.5。儘管在圖15中示出，一個半導體晶粒140位於凹穴CV內，但是可以理解，在凹穴CV中可以容納不止一個晶粒。在某些實施例中，當圖8和圖9中所示的封裝單元安裝到電路基底時，電路基底可能包括單一個凹穴以在同一個凹穴中容納兩個或四個晶粒，或多個凹穴以一對一方式在其中容納一個或多個晶粒。
在圖13中，在某些實施例中，形成底充膠640並填充在封裝結構10和電路基底600之間以形成半導體元件封裝結構13。在某些實施例中，底充膠640填充在半導體晶粒140和凹穴CV之間，並填充在位於封裝單元10和電路基底600之間的融合連接件630之間。在某些實施例中，所形成的底充膠640為無空隙填充材料填充凹穴CV以及填充于封裝單元10和電路基底600之間。底充膠640可以保護融合的連接件630免受熱或物理應力的影響，並進一步保護位於電路基底600的凹穴CV中的半導體晶粒140。由於凹穴CV的側壁和底面沒有暴露出金屬化圖形或跡線，因此在凹穴CV的底充膠640和表面之間實現了更好的附著性，提升整個元件結構的可靠性。
在一些實施例中，在圖13中，底充膠640是由毛細管底充膠填充（CUF）形成的，底充膠640不僅填充了封裝結構10和電路基底600之間的空隙，而且還溢流出來部分覆蓋重佈線層110的側壁。在一些實施例中，如圖13A所示，底充膠640A由轉移成型所形成，底充膠640A的側壁是共面的，與重佈線層110的側壁垂直對齊。在某些實施例中，可以進行固化製程以鞏固底充膠640。在一些實施例中，由於凹穴CV的側壁和底面沒有暴露出金屬化圖形或跡線，所以後來填充的底充膠640和凹穴CV的表面（例如介電材料601的介電表面）具有良好的附著性，且封裝元件結構的耐受性和可靠性變得更好。
本發明不受半導體封裝類型的限制，也不受半導體封裝10連接到電路基底600的數量的限制。在本公開的圖中，為了說明的目的，集成扇出型(InFO)封裝顯示為半導體封裝單元。然而，顯然可以使用其他類型的半導體封裝來生產包括在此公開的電路基底的半導體元件封裝結構，並且所有這些半導體元件旨在落入本說明和所附權利要求的範圍之內。舉例來說，基底上晶圓上晶片（Chip-on-Wafer-on-Substrate，CoWoS）結構、三維積體電路(3DIC)結構、晶圓上晶片(CoW)封裝、層疊封裝(PoP)結構都可以用作半導體封裝單元，單獨或在組合中使用。
從圖14A的示例性示意性視圖來看，半導體晶粒140與兩個半導體晶粒120是透過接觸點122、142與重佈線層110的垂直堆疊金屬化圖案VM達到電性連接。在一些實施例中，半導體晶粒140可作為橋接元件用於透過垂直堆疊金屬化圖案VM電性連接兩個半導體晶粒120，這導致更短的電路徑和更好的電效能。在某些實施例中，垂直堆疊金屬化圖案VM包括相互垂直對齊堆疊的通孔和夾在堆疊通孔之間的金屬圖案。
在其他一些實施例中，參考圖14B，半導體晶粒140A還包括貫穿半導體晶粒140A的半導體穿孔（through semiconductor via，TSV）140V，位於凹穴CV內的半導體晶粒140A是透過凸塊Bp電性連接至電路基底600的凹穴CV下方的金屬化圖形602。即封裝結構的半導體晶粒140A是電性連接至電路基底600的金屬化圖形602。參考圖14B，半導體晶粒140A可作為封裝單元的其他晶粒的橋接組件，將上面的封裝單元和下面的電路基底電性連接成為電性連接路徑的部分，進一步縮短了電的導通路徑，提高了整體結構的效能。以圖15B中描述的結構為例，圖14B中描述的連結方案可以適用於凹穴CV2中的半導體晶粒。
根據一些實施例，半導體封裝至少包括電路基底、半導體晶粒和填充材料。電路基底有第一表面，與第一表面相反的第二表面和從第一表面凹進去的凹穴。電路基底包括介電材料和埋設在介電材料中並位於凹穴下方的金屬底板。金屬底板的位置對應於凹穴的位置。金屬底板是電性浮置且被介電材料隔離。半導體晶粒設置在凹穴中且與電路基底電性連接。填充材料設置在半導體晶粒和電路基底之間，填充材料填充凹穴且封裝半導體晶粒而連接半導體晶粒和電路基底。
根據本公開的一些實施例，半導體封裝進一步包括重佈線層，設置在並且連接到所述半導體晶粒的主動表面並且連接到所述電路基底的所述第一表面。根據本公開的一些實施例，其中所述半導體晶粒透過所述重佈線層電性連接到所述電路基底。根據本公開的一些實施例，半導體封裝進一步包括模封結構設置在所述重佈線層上，其中所述模封結構包括另一個半導體晶粒電性連接到所述重佈線層和所述半導體晶粒，且電性連接到所述電路基底。根據本公開的一些實施例，其中所述重佈線層包括垂直堆疊金屬化圖案，且所述半導體晶粒透過所述垂直堆疊金屬化圖案電性連接到所述另一個半導體晶粒。
根據本公開的一些實施例，其中所述半導體晶粒包括貫穿穿透所述半導體晶粒的半導體穿孔，並且所述半導體晶粒透過所述半導體穿孔電性連接到所述電路基底。根據本公開的一些實施例，其中所述凹穴的底面與所述金屬底板隔開一距離且所述介電材料夾在其間。
根據本公開的一些實施例，其中所述凹穴的垂直投影落入所述金屬底板的跨度內。
根據本公開的一些實施例，其中所述凹穴的垂直投影與所述金屬底板交疊。
根據一些實施例，半導體封裝至少包括具有第一表面和與第一表面相對的第二表面的重佈線層、設置在重佈線層的第一表面上的模封結構以及電路基底。模封結構包括側向地被模製化合物包圍的第一晶粒和第二晶粒，第一和第二晶粒是和重佈線層電性連接。電路基底與重佈線層的第二表面相連。電路基底包括介電材料、凹穴下凹進介電材料且具有無金屬的介電表面以及埋設於介電材料中並位於凹穴下方的底板。第三晶粒設置在重佈線層的第二表面上和重佈線層電性連接的。第三晶粒位於凹穴內，底充膠位於第三晶粒和凹穴之間以及位於電路基底和重佈線層之間。
根據本公開的一些實施例，其中夾在所述底板和所述凹穴的底面之間的所述介電材料具有從約1微米到約100微米的厚度。
根據本公開的一些實施例，其中所述凹穴的垂直投影落在所述底板的跨度內，並且所述底板的所述跨度大於所述凹穴的跨度。
根據本公開的一些實施例，其中所述底板包括具有網格圖案的單金屬板，且所述凹穴的垂直投影和所述單金屬板交疊。
根據本公開的一些實施例，其中所述底板包括多個平行排列的金屬板，且所述凹穴的垂直投影和所述多個平行排列的金屬板交疊。
根據本公開的一些實施例，其中所述第三晶粒的背表面與所述凹穴的底面相距約1微米至約100微米的距離。
根據本公開的一些實施例，其中所述第三晶粒被所述底充膠包封並且所述第三晶粒透過所述重佈線層電性連接到所述電路基底。
根據本公開的一些實施例，其中所述第三晶粒包括貫穿穿透所述第三晶粒的半導體穿孔，並且所述第三晶粒透過所述半導體穿孔電性連接到所述電路基底。
根據一些實施例，提供了製造方法。形成重佈線層。第一半導體晶粒鍵合到重佈線層的第一表面上。半導體晶粒與模製化合物一起成型。第二半導體晶粒鍵合到重佈線層的與第一表面相對的第二表面上。提供具有介電材料和埋設在介電材料中的底板的電路基底。透過去除介電層的部分而不暴露底板，在電路基底中形成凹穴。電路基底與重佈線層相連，第二半導體晶粒容納在凹穴中。底充膠分配到凹穴中以填充凹穴並圍繞第二半導體晶粒並填充在電路基底和重佈線層之間。
根據本公開的一些實施例，其中在所述電路基底中形成凹穴包括執行機械燒蝕製程以移除所述介電材料並在來自所述底板的距離處停止。
根據本公開的一些實施例，其中在所述電路基底中形成凹穴包括執行鐳射燒蝕製程以移除所述介電材料，並在離所述底板一距離處停止。
前文概述若干實施例的特徵，使得所屬技術領域的技術人員可更好地理解本揭露內容的態樣。所屬技術領域的技術人員應理解，其可易於使用本揭露內容作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他方法及結構的基礎。所屬領域的技術人員亦應認識到，此類等效構造並不脫離本揭露內容的精神及範疇，且所屬領域的技術人員可在不脫離本揭露內容的精神及範疇的情況下在本文中作出改變、替代以及更改。
10、70、80、90:半導體封裝 13:半導體元件封裝結構 102、104:載體 110、710、810、910:重佈線層 110S:表面 112:第一介電材料層 113:第一金屬化層 113B:鍵合部分 113P、117P、606、608:墊 114:第二介電材料層 115:第二金屬化層 116:第三介電材料層 117:第三金屬化層 118:第四介電材料層 119:接合部分 120、140、140A、700A、700B、740、800A、800B、840A、840B、900A、900B、940A、940B、940C、940D:半導體晶粒 120B、140S:背表面 122、142:接觸點 126、146、640、640A:底充膠 130:模製化合物 130T、600T:頂表面 150:導電件 600:電路基底 600B:底表面 601:介電材料 602:金屬化圖形 604:通孔 605:底板 610:接合連結物 620:導電球 630:連接件 CV、CV1、CV2:凹穴 Dcv:深度 Dt、Ds、Ss:距離 H1:第一高度 H2:第二高度 L700、L740、L800、L840:長度 MS:模封結構 VM:垂直堆疊金屬化圖案 Wcv、W700、W740、W800、W840:寬度
當結合隨附圖式閱讀以下具體實施方式時將最佳地理解本揭露內容的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。事實上，出於論述清晰起見，可任意地增大或減小各種特徵的尺寸。 圖1到圖6是根據本公開的一些示例性實施例在半導體封裝的製造方法中的各階段的示意性剖視圖。 圖7到圖9是根據本公開的一些實施例的半導體封裝的示意性平面視圖。 圖10至圖13是根據本公開的一些示例性實施例在連接到電路基底的半導體封裝的製造方法中的各階段處所形成的結構的示意性剖視圖。 圖13A是示意性剖視圖，說明根據本公開的一些實施例連接到電路基底的半導體封裝。 圖14A是示意性放大部分剖視圖，顯示根據本公開的一些示例性實施例的半導體封裝結構的連接的部分。 圖14B是示意性放大部分剖視圖，顯示根據本公開的一些示例性實施例連接到電路基底的半導體封裝結構的另一個連接的部分。 圖15A和圖15B是示意性平面視圖，顯示根據本公開的一些實施例連接到電路基底的半導體封裝中的底板和凹穴的相對構造。
10:半導體封裝
13:半導體元件封裝結構
110:重佈線層
113:第一金屬化層
113P:墊
120、140:半導體晶粒
600:電路基底
601:介電材料
602:金屬化圖形
604:通孔
605:底板
620:導電球
630:連接件
640:底充膠
CV:凹穴
Dt:距離

Claims (20)

  1. 一種半導體封裝，包括： 電路基底，具有第一表面與所述第一表面相對的第二表面和從所述第一表面凹入的凹穴，其中所述電路基底包括介電材料和埋設於所述介電材料中且位於所述凹穴下方的金屬底板，其中所述金屬底板的位置對應於所述凹穴的位置，並且所述金屬底板是電性浮置且被所述介電材料隔離； 半導體晶粒，設置於所述凹穴內且與所述電路基底電性連接；以及 填充材料，設置於所述半導體晶粒和所述電路基底之間，其中所述填充材料填充所述凹穴並封裝所述半導體晶粒以連接所述半導體晶粒和所述電路基底。
  2. 如請求項1所述的半導體封裝，進一步包括重佈線層，設置在並且連接到所述半導體晶粒的主動表面並且連接到所述電路基底的所述第一表面。
  3. 如請求項2所述的半導體封裝，其中所述半導體晶粒透過所述重佈線層電性連接到所述電路基底。
  4. 如請求項2所述的半導體封裝，進一步包括模封結構設置在所述重佈線層上，其中所述模封結構包括另一個半導體晶粒電性連接到所述重佈線層和所述半導體晶粒，且電性連接到所述電路基底。
  5. 如請求項4所述的半導體封裝，其中所述重佈線層包括垂直堆疊金屬化圖案，且所述半導體晶粒透過所述垂直堆疊金屬化圖案電性連接到所述另一個半導體晶粒。
  6. 如請求項1所述的半導體封裝，其中所述半導體晶粒包括貫穿穿透所述半導體晶粒的半導體穿孔，並且所述半導體晶粒透過所述半導體穿孔電性連接到所述電路基底。
  7. 如請求項1所述的半導體封裝，其中所述凹穴的底面與所述金屬底板隔開一距離且所述介電材料夾在其間。
  8. 如請求項1所述的半導體封裝，其中所述凹穴的垂直投影落入所述金屬底板的跨度內。
  9. 如請求項1所述的半導體封裝，其中所述凹穴的垂直投影與所述金屬底板交疊。
  10. 一種半導體封裝，包括： 重佈線層，具有第一表面和與所述第一表面相反的第二表面； 模封結構，設置在所述重佈線層的所述第一表面上，其中所述模封結構包括第一晶粒和第二晶粒側向地被模製化合物包圍，所述第一晶粒和所述第二晶粒電性連接到所述重佈線層； 電路基底，與所述重佈線層的所述第二表面相連，其中所述電路基底包括介電材料、凹穴凹入所述介電材料且具有無金屬的介電表面，以及底板埋設於所述介電材料且位於所述凹穴下方； 第三晶粒，設置於所述重佈線層的所述第二表面上，位於所述凹穴內且與所述重佈線層電性連接；以及 底充膠，設置於所述第三晶粒和所述凹穴之間以及所述電路基底和所述重佈線層之間。
  11. 如請求項10所述的半導體封裝，其中夾在所述底板和所述凹穴的底面之間的所述介電材料具有從約1微米到約100微米的厚度。
  12. 如請求項10所述的半導體封裝，其中所述凹穴的垂直投影落在所述底板的跨度內，並且所述底板的所述跨度大於所述凹穴的跨度。
  13. 如請求項10所述的半導體封裝，其中所述底板包括具有網格圖案的單金屬板，且所述凹穴的垂直投影和所述單金屬板交疊。
  14. 如請求項10所述的半導體封裝，其中所述底板包括多個平行排列的金屬板，且所述凹穴的垂直投影和所述多個平行排列的金屬板交疊。
  15. 如請求項10所述的半導體封裝，其中所述第三晶粒的背表面與所述凹穴的底面相距約1微米至約100微米的距離。
  16. 如請求項10所述的半導體封裝，其中所述第三晶粒被所述底充膠包封並且所述第三晶粒透過所述重佈線層電性連接到所述電路基底。
  17. 如請求項10所述的半導體封裝，其中所述第三晶粒包括貫穿穿透所述第三晶粒的半導體穿孔，並且所述第三晶粒透過所述半導體穿孔電性連接到所述電路基底。
  18. 一種半導體封裝製造方法，包括： 形成重佈線層； 鍵合第一半導體晶粒到所述重佈線層的第一表面； 以模製化合物模塑所述半導體晶粒； 鍵合第二半導體晶粒到所述重佈線層的與所述第一表面相對的第二表面； 提供具有介電材料和埋設在所述介電材料中的底板的電路基底； 透過去除所述介電層的部分而不暴露所述底板而在所述電路基底中形成凹穴； 將所述電路基底與所述重佈線層連接，在所述凹穴中容納所述第二半導體晶粒；以及 將底充膠分配到所述凹穴以填充所述凹穴，包圍所述第二半導體晶粒，並填充至所述電路基底和所述重佈線層之間。
  19. 如請求項18所述的半導體封裝製造方法，其中在所述電路基底中形成凹穴包括執行機械燒蝕製程以移除所述介電材料並在來自所述底板的距離處停止。
  20. 如請求項18所述的半導體封裝製造方法，其中在所述電路基底中形成凹穴包括執行鐳射燒蝕製程以移除所述介電材料，並在離所述底板一距離處停止。
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