CN115513189A - 半导体封装及其制造方法 - Google Patents

半导体封装及其制造方法 Download PDF

Info

Publication number
CN115513189A
CN115513189A CN202210041865.7A CN202210041865A CN115513189A CN 115513189 A CN115513189 A CN 115513189A CN 202210041865 A CN202210041865 A CN 202210041865A CN 115513189 A CN115513189 A CN 115513189A
Authority
CN
China
Prior art keywords
circuit substrate
die
semiconductor
semiconductor die
redistribution layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210041865.7A
Other languages
English (en)
Inventor
林孟良
庄博尧
翁得期
陈硕懋
郑心圃
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN115513189A publication Critical patent/CN115513189A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81011—Chemical cleaning, e.g. etching, flux
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Abstract

本公开的各种实施例涉及半导体封装和其制造方法。半导体封装至少包括电路衬底、半导体管芯和填充材料。电路衬底有第一表面、与所述第一表面相反的第二表面和从所述第一表面凹进去的凹穴。电路衬底包括介电材料和埋设在介电材料中并位于凹穴下方的金属底板。金属底板的位置对应于凹穴的位置。金属底板是电性浮置的并被介电材料隔离。半导体管芯设置在凹穴中，且与电路衬底电连接。填充材料设置在半导体管芯和电路衬底之间。填充材料填充凹穴且封装半导体管芯，而连接半导体管芯和电路衬底。

Description

半导体封装及其制造方法
技术领域
本发明的实施例涉及一种半导体封装以及其制造方法。
背景技术
半导体管芯可以与其他半导体元件或管芯加工封装，封装的尺寸大小是由半导体管芯和/或其他元件的安排配置所决定。
发明内容
本公开实施例描述一种半导体封装，所述半导体封装至少包括电路衬底、半导体管芯和填充材料。电路衬底有第一表面，与第一表面相反的第二表面和从第一表面凹进去的凹穴。电路衬底包括介电材料和埋设在介电材料中并位于凹穴下方的金属底板。金属底板的位置对应于凹穴的位置。金属底板是电性浮置且被介电材料隔离。半导体管芯设置在凹穴中且与电路衬底电连接。填充材料设置在半导体管芯和电路衬底之间，填充材料填充凹穴且封装半导体管芯而连接半导体管芯和电路衬底。
本公开实施例描述一种半导体封装，所述半导体封装至少包括具有第一表面和与第一表面相对的第二表面的重布线层、设置在重布线层的第一表面上的模封结构以及电路衬底。模封结构包括侧向地被模制化合物包围的第一管芯和第二管芯，第一和第二管芯是和重布线层电连接。电路衬底与重布线层的第二表面相连。电路衬底包括介电材料、凹穴下凹进介电材料且具有无金属的介电表面以及埋设于介电材料中并位于凹穴下方的底板。第三管芯设置在重布线层的第二表面上和重布线层电连接的。第三管芯位于凹穴内，底充胶位于第三管芯和凹穴之间以及位于电路衬底和重布线层之间。
本公开实施例描述一种半导体封装制造方法。形成重布线层。第一半导体管芯键合到重布线层的第一表面上。半导体管芯与模制化合物一起成型。第二半导体管芯键合到重布线层的与第一表面相对的第二表面上。提供具有介电材料和埋设在介电材料中的底板的电路衬底。通过去除介电层的部分而不暴露底板，在电路衬底中形成凹穴。电路衬底与重布线层相连，第二半导体管芯容纳在凹穴中。底充胶分配到凹穴中以填充凹穴并围绕第二半导体管芯并填充在电路衬底和重布线层之间。
附图说明
当结合随附图式阅读时从以下详细描述最好地理解本公开的各方面。应注意，根据业界中的标准惯例，各种特征未按比例绘制。实际上，为了论述清楚起见，可任意增大或减小各种特征的尺寸。
图1到图6是根据本公开的一些示例性实施例在半导体封装的制造方法中的各阶段的示意性剖视图。
图7到图9是根据本公开的一些实施例的半导体封装的示意性平面视图。
图10至图13是根据本公开的一些示例性实施例在连接到电路衬底的半导体封装的制造方法中的各阶段处所形成的结构的示意性剖视图。
图13A是示意性剖视图，说明根据本公开的一些实施例连接到电路衬底的半导体封装。
图14A是示意性放大部分剖视图，显示根据本公开的一些示例性实施例的半导体封装结构的连接的部分。
图14B是示意性放大部分剖视图，显示根据本公开的一些示例性实施例连接到电路衬底的半导体封装结构的另一个连接的部分。
图15A和图15B是示意性平面视图，显示根据本公开的一些实施例连接到电路衬底的半导体封装中的底板和凹穴的相对构造。
具体实施方式
以下公开内容提供诸多不同的实施例或实例以实施所提供主题的不同特征。下文阐述组件及排列的具体实例以简化本公开。当然，这些仅是实例且不旨在进行限制。举例来说，在以下说明中，第一特征形成在第二特征之上或形成在第二特征上可包括其中第一特征与第二特征形成为直接接触的实施例，且还可包括其中在第一特征与第二特征之间可形成附加特征、从而使得第一特征与第二特征可能不直接接触的实施例。另外，本公开可在各种实例中重复使用参考编号和/或字母。此种重复使用是出于简洁及清晰的目的，且自身并不表示所论述的各种实施例和/或配置之间的关系。
此外，为易于说明，本文中可使用例如“在…下方(beneath)”、“低于(below)”、“下部(lower)”、“在…上方(above)”、“上部(upper)”等空间相对性用语来阐述如图中所示的一个元件或特征与另一(其他)元件或特征之间的关系。除图中所绘示的取向以外，空间相对性用语还旨在囊括器件在使用或操作中的不同取向。装置可以其他方式取向(旋转90度或处于其他取向)，且本文中所使用的空间相对性描述语可同样相应地进行解释。
还可包括其他特征及工艺。举例来说，可包括测试结构来辅助对三维(3D)封装或三维集成电路(three dimensional integrated circuit，3DIC)器件进行验证测试。测试结构可包括例如形成在重布线层中或形成在衬底上的测试焊盘，所述测试焊盘使得能够对3D封装或3DIC进行测试、对探针和/或探针卡进行使用等。可对中间结构及最终结构执行验证测试。另外，本文中所公开的结构及方法可与测试方法结合使用，所述测试方法包括在中间阶段验证出已知良好的管芯以提高良率(yield)且降低成本。
图1到图6是根据本公开的一些示例性实施例在半导体封装的制造方法中的各阶段的示意性剖视图。在一些实施例中，一个或多个管芯可表示多个管芯，半导体制造方法所得到的一个或多个封装可表示多个半导体封装。
参考图1，在一些实施例中，提供了其上具有剥离层(未示出)的载体102。在某些实施例中，载体102是半导体衬底，例如本体硅晶片或玻璃衬底。举例来说，剥离层可包括光热转化(LTHC)离型层。
参考图1，在一些实施例中，在载体102上形成了重布线层110。重布线层110的形成包括相继地交替形成一层以上的介电材料层和一层以上的金属化层。参考图1，在某些实施例中，重布线层110的形成包括相继地形成第一介电材料层112、第一金属化层113、第二介电材料层114、第二金属化层115、第三介电材料层116、第三金属化层117、第四介电材料层118和接合部分119。在一些实施例中，重布线层110的形成还包括形成介电材料层(未示出)、图案化介电材料层以形成开口，沉积金属材料填充开口以形成金属化图形。在一些实施例中，金属化层113、115、117和接合部分119是电互连的。
在一些实施例中，介电材料层112、114、116、118的材料可以相同或不同。在一些实施例中，介电材料层112、114、116、118的材料包括一种或多种聚合物介电材料，例如聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)或任何其他合适的基于聚合物的介电材料。在一些实施例中，金属化层113、115、117和接合部分119的材料可以相同或不同，金属化层113、115、117和接合部分119的材料可以选自铜、钴、镍、铝、钨或其组合。在一些实施例中，金属化层113、115、117可以包括路由迹线或扇出迹线。在一些实施例中，第一金属化层113可能包括键合部分113B和垫113P。在一些实施例中，第三金属化层117可以包括与接合部分119相连的接触垫117P，用于接收凸块或其他组件。在一些实施例中，接合部分119进一步可选地包括在接合部分的表面上形成的用于增强键合的附着层、种晶层、预先焊料、焊料膏和/或凸块下金属(UBM)图案。
参考图2，提供两个或多个半导体管芯120并放置在载体102之上的重布线层110之上。在图2中，仅示出了两个管芯作为封装结构的示例性管芯，但是应当理解，在封装结构内可以包括多于两个管芯或不同类型的管芯。在一些实施例中，管芯120中的一个或多个包括一个或多个存储芯片，例如高带宽存储器芯片、动态随机存取存储器(DRAM)芯片或静态随机存取存储器(SRAM)芯片。在一些实施例中，管芯120中的一个或多个可以包括专用集成电路(ASIC)芯片、模拟芯片、传感器芯片、无线应用芯片(例如蓝牙芯片或射频(RF)芯片)或电压调节器芯片中的一个或多个。在一些实施例中，管芯120之一可能是包括存储芯片的存储器管芯，而另一个管芯120可能是包括控制器芯片的系统级芯片(SoC)管芯。在某些实施例中，管芯和芯片可以互换使用。
在某些实施例，如在图2中，设有接触点122的半导体管芯120朝下，半导体管芯120的接触点122与重布线层110的接合部分119键合。在一实施例中，半导体管芯120到重布线层110的键合包括执行回流焊接工艺通过焊料焊剂键合接触点122和接合部分119。在一些实施例中，接触点122是金属柱条、微凸块、铜柱、铜合金柱或其他合适的金属连接件。在某些实施例中，半导体管芯120并排安装在载体102之上的重布线层110上，并且并排或堆叠在另外管芯之上布置的管芯的数量可以在产品设计的基础上进行调整或修改，但是不受示例性实施例限制。在某些实施例中，底充胶126填充在半导体管芯120和重布线层110之间，包封了键合的接触点122和接合部分119，以获得更好的贴合粘着。在某些实施例中，底充胶126至少部分填充了半导体管芯120之间的空隙。
参考图3，在一些实施例中，位于重布线层110上的半导体管芯120被模压封装在模制化合物130中，形成模封结构MS。在实施例中，模制化合物130填充了管芯120之间的空间，至少侧向地覆盖填充了重布线层110上的管芯120。在实施例中，模制化合物130的材料包括环氧树脂、酚类树脂或含硅的树脂。在某些实施例中，模制化合物130的材料包括填充物颗粒。在某些实施例中，模制化合物130包覆成型然后平坦化，直到管芯120露出背表面120B。在某些实施例中，对包覆模塑成型的模制化合物130进行研磨，直到暴露出管芯120的背表面120B。在实施例中，在平坦化之后，模制化合物130的顶表面130T和管芯120的背表面120B变成大体上并彼此齐平。在某些实施例中，模制化合物130通过研磨工艺或化学机械研磨(CMP)工艺进行平坦化。
参考图4，在一些实施例中，贴合另一载体104到模封结构MS(贴合到管芯120的背表面120B)之后，整个结构被颠倒(翻转)，通过剥离层(未显示)载体102与模封结构MS分离，然后移除。载体102与模封结构MS分离后，包括键合部分113B和垫113P在内的第一金属化层113从重布线层110的表面110S暴露出来。
在一些实施例中，如图5，另一个半导体管芯140与重布线层110键合，导电件150形成在重布线层110上。在一些实施例中，半导体管芯140有第一高度H1(从表面110S厚度方向垂直测量)，导电件150有第二高度H2(从表面110S厚度方向垂直测量)，第二高度H2比第一高度H1小。在某些实施例中，导电件150是设置在半导体管芯140旁边。有的实施例，半导体管芯140的接触点142是朝下的，半导体管芯140是装在重布线层110的第一金属化层113上的。在某些实施例中，半导体管芯140与重布线层110键合，半导体管芯140的接触点142键合并连接到重布线层110的键合部分113B。在某些实施例中，半导体管芯140的接触点142的尺寸或大小大于半导体管芯120的接触点122的尺寸或大小。在一些实施例中，接触点142是金属柱条、微凸块、铜柱、铜合金柱或其他合适的金属连接件。在图5中，仅示出了一个半导体管芯作为封装结构的示例性管芯，但是应当理解，在封装结构内可以包括两个或更多个管芯或不同类型的半导体管芯。在某些实施例中，在半导体管芯140和重布线层110之间形成底充胶146，并封装了键合的接触点142和键合部分113B，以获得更好的贴合粘着。在实施例中，半导体管芯140到重布线层110的键合包括执行回流焊接工艺通过焊料焊剂键合接触点142和键合部分113B。在某些实施例中，导电件150设置在第一金属化层113上，并且通过执行植球工艺和回流焊接工艺固定到接触垫113P。实施例中，导电件150可为例如微凸块、金属柱、具焊料膏金属柱、化学镀镍化学镀钯沉金(ENEPIG)形成的凸块，或受控塌陷芯片连接(C4)凸块。如图5所示，部分导电件150通过重布线层110电连接到半导体管芯120，部分导电件150通过重布线层110电连接到半导体管芯140。在某些实施例中，半导体管芯140通过重布线层110电连接到半导体管芯120，半导体管芯120与重布线层110是电连接的。在一些实施例中，半导体管芯140可包括一个或多个无源组件，例如电容器、电感或电阻器。在某些实施例中，半导体管芯140可能包括一体化无源器件(IPD)。
参考图6，在一些实施例中，沿着切割道(未示出)，执行切割工艺以将整个结构(至少切割通过重布线层110和模制化合物130)切割成单独的和分离的半导体封装10。在实施例中，切割工艺可以包括晶片切割工艺，包括机械锯切(mechanical ablation)或激光切割(laser ablation)。在某些实施例中，移除了载体104。
图7到图9是根据本公开的一些实施例的半导体封装的示意性平面视图。需要注意的是，图7至图9中的封装单元或结构仅用于说明，图7至图9中的实施例在结构描述可参照图1至图6，且包括在本公开的预期范围内。
参考图7，封装结构70与前面实施例中显示的封装结构10类似，但简化了插图以显示封装结构70中半导体管芯的相对配置。在某些实施例中，半导体管芯740和半导体管芯700A以及700B位于重布线层710的两个相对的侧处。从图7中可以看出，半导体管芯700A和700B以并排排列并位于重布线层710下方，另一个半导体管芯740安装在重布线层710上，位于下方两个半导体管芯700A、700B之间的中心位置。在一些实施例中，半导体管芯700A和700B是同类型的管芯，半导体管芯700A、700B和740是不同类型的管芯。在一些实施例中，半导体管芯700A和700B是不同类型的管芯，半导体管芯700A、700B和740是不同类型的管芯。从图7的平面视图来看，管芯700A或700B具有长度L700和宽度W700，管芯740具有长度L740和宽度W740。在图7中，在某些实施例中，半导体管芯740的垂直投影(沿厚度方向)与半导体管芯700A和700B都部分重叠。在一些实施例中，半导体管芯740的跨度沿着半导体管芯700A、700B的相邻长侧延展且从一个半导体管芯700A延伸到另一个半导体管芯700B，使得半导体管芯740交叠半导体管芯700A和700B。在实施例中，长度L700大于长度L740，L740/L700范围的比例从大约0.1到大约0.95。在实施例中，宽度L740小于宽度W700但大于半导体管芯700A和700B之间的空隙的宽度Wg。在实施例中，空隙宽度Wg的范围从大约1微米到大约200微米。
参考图8，封装结构80与前面实施例中显示的封装结构10类似，但简化了插图以显示封装结构80中半导体管芯的相对配置。在一些实施例中，半导体管芯840A、840B和半导体管芯800A和800B位于重布线层810的两个相对的侧处。如在图8中所见，半导体管芯800A和800B以并排排列并位于重布线层810的底侧下，而半导体管芯840A、840B安装在重布线层810的顶侧上，位于下面两个半导体管芯800A、800B之间的中心位置。实施例中，半导体管芯800A和800B是同类型的管芯，半导体管芯840A、840B是同类型的管芯但与管芯800A、800B不同。在实施例中，半导体管芯800A和800B是不同类型的管芯，半导体管芯840A、840B是不同类型的管芯且与管芯800A、800B不同。从图8的平面视图来看，管芯800A或800B具有长度L800和宽度W800，管芯840A或840B具有长度L840和宽度W840。在图8中，在某些实施例中，半导体管芯840A或840B的垂直投影(沿厚度方向)与半导体管芯800A和800B部分重叠。在一些实施例中，介于半导体管芯840A和840B之间间距范围从大约1微米到大约1000微米。在实施例中，长度L800比长度L840大，宽度L840比宽度W800小但比介于半导体管芯800A和800B之间空隙的宽度Wg大。
参考图9，封装结构90类似于前面实施例中显示的封装结构10，但简化了图示以显示封装结构90中半导体管芯的相对配置。在一些实施例中，半导体管芯940A、940B、940C、940D和半导体管芯900A、900B分别位于重布线层910的两个相对的侧处。从图9中可以看出，半导体管芯900A和900B以并排排列并位于重布线层910的底侧处，而半导体管芯940A、940B、940C、940D则安装在重布线层910的顶侧上，并位于底层两个半导体管芯900A、900B之间的中心位置。在实施例中，半导体管芯940A、940B、940C、940D是同类型的管芯，但与管芯900A、900B不同类型。在实施例中，半导体管芯900A和900B是不同类型的管芯，半导体管芯940A、940B、940C、940D是不同类型的管芯，且与管芯900A、900B不同类型。在图9中，在某些实施例中，半导体管芯940A、940B、940C或940D的垂直投影(沿厚度方向)与半导体管芯900A和900B均部分重叠。在一些实施例中，半导体管芯940A、940B、940C、940D之间的间距范围从约1微米到约1000微米。在实施例中，半导体管芯940A、940B、940C、940D中的任何一个的宽度都比半导体管芯900A和900B之间的空隙的宽度Wg大。相邻管芯940A、940B、940C、940D之间的间距可以在产品设计的基础上进行调整。
图10至图13是根据本公开的一些示例性实施例在连接到电路衬底的半导体封装的制造方法中的各阶段处所形成的结构的示意性剖视图。图13A是示意性剖视图，说明根据本公开的一些实施例连接到电路衬底的半导体封装。图14A是示意性放大部分剖视图，显示根据本公开的一些示例性实施例的半导体封装结构的连接的部分。图14B是示意性放大部分剖视图，显示根据本公开的一些示例性实施例连接到电路衬底的半导体封装结构的另一个连接的部分。图15A和图15B是示意性平面视图，显示根据本公开的一些实施例连接到电路衬底的半导体封装中的底板和凹穴的相对构造。应注意，图14A至图15B中所示的构造仅用于说明，而这些构造或方案在结构描述参照图10至图13，也包括在本公开的预期范围内。
在某些实施例中，参考图10，提供了电路衬底600。在某些实施例中，电路衬底600包括积层板、印刷电路板、层叠板或可挠层合板。在一些实施例中，电路衬底600可包括一个或多个有源组件、无源组件或不同组合于其中。在一些实施例中，举例来说，电路衬底600包括了介电材料601、金属化图形602，贯穿通孔604以及键合垫606与608连接到金属化层602和通孔604来提供双侧电连接。在某些实施例中，金属化图形602包括埋设在介电材料601中的一个或多个底板605。如图10右侧的上方放大平面视图，在某些实施例中，底板605包括三个长条板，它们彼此间隔并具有距离Ss并平行排列。在实施例中，距离Ss范围从大约1微米到大约200微米。在实施例中，如在图10中左侧侧处的放大平面视图中所见，底板605是带有开口或带有网格图案的单一金属板。在一些实施例中，金属化图形602被设计成电连接各种组件，例如埋设于电路衬底中的有源组件和/或无源组件以形成功能性电路。在某些实施例中，接合连结物610是在电路衬底600的顶表面600T上的键合垫606上形成的。在一些实施例中，接合连结物610包括焊料或预先焊料、微凸块、金属柱或金属柱条与焊料膏。在一些实施例中，导电球620可以形成在电路衬底600的底表面600B上的接触垫608上，进一步的电连接。在一些实施例中，导电球620包括焊料球、球栅阵列(BGA)连接件、受控塌陷芯片连接(C4)凸块。
在一些实施例中，材料包括金属化图形，材料包括铜、铝、镍、钴、金、银、钨、其组合或其类似物。在实施例中，介电材料601包括有机介电材料。在某些实施例中，介电材料601可能包括味之素(Ajinomoto)增层膜、聚合物材料(例如，聚酰亚胺、聚酯、苯并环丁烯、聚苯并恶唑、或其类似物)、预浸料、树脂涂层铜(RCC)、光图像介电材料(PID)、酚醛纸、酚醛棉纸、玻璃纤维编织布、浸渍玻璃纤维编织布、模制化合物或组合。在一些实施例中，电路衬底600的介电材料601可以通过压模法、包覆模塑和平坦化、层叠或其他合适的技术形成。在一些实施例，金属化图形602、通孔604和垫606与608可以通过镀覆工艺例如电镀覆、化学镀、浸入镀覆或其类似物中的一或多种所形成。
在一些实施例中，参考图11，在电路衬底600中形成凹穴CV。在图11中，在某些实施例中，凹穴CV以深度Dcv(从顶表面600T测量)凹入电路衬底600，并在到达底板605之前停止。在某些实施例中，凹穴CV具有宽度Wcv，范围从大约10微米到大约10厘米。在某些实施例中，凹穴的尺寸足够大，可以容纳后来设置的管芯或封装单元。在实施例中，凹穴CV是通过对电路衬底600进行机械烧蚀工艺或激光烧蚀工艺而形成的，从顶表面600T中去除介电材料601的部分，形成电路衬底600中的凹穴CV。在某些实施例中，凹穴CV是在不存在金属化图形或布线的排除区(keep-out region)中形成的，而凹穴CV的形成仅涉及去除区中的介电材料601。即凹穴CV露出的表面是无金属化(无金属)的介电表面。在一些实施例中，埋设介电材料601中的底板605位于排除区下方，而凹穴CV是通过去除底板605上方的介电材料601而形成的。在实施例中，在凹穴CV的形成过程中，介电层601的去除在到达底板605之前在一特定距离处停止，而底板605可作为缓冲或阻挡层甚至是标记，以精确控制移除工艺。在实施例中，由于凹穴CV是通过去除介电材料601而不是金属材料形成的，因此凹穴CV的尺寸得到了更好的表面平面性控制。在实施例中，凹穴CV的底与底板605以距离Ds隔开。在实施例中，间距距离Ds范围从大约1微米到大约100微米。换句话说，凹穴的底和底板605之间的介电材料601夹层具有范围从大约1微米到大约100微米的厚度。在某些实施例中，在图10和图11中，形状为三个长条的底板605位于凹穴CV的正下方，而底板605是电性浮置的，并通过介电材料601而与其他金属化图形602电性隔离。在某些实施例中，凹穴CV的位置对应于底板605的分布位置。
参考图15A和图15B，相对于结合到电路衬底600的封装结构10，显示出底板605和凹穴CV的构造和位置，但是某些组件被省略并且图示被简化。参考图11和图15A的平面视图，可以看出凹穴CV的跨度与底板605的跨度完全重叠。在实施例中，底板605的跨度大于凹穴CV的跨度，从平面视图来看，底板605的分布跨度和凹穴CV的跨度呈同心(同环)排列。应当理解，这里示出了一个凹穴作为示例，但是多于一个凹穴也是可能的，并且可以根据要容纳到凹穴中的管芯的形状和数量来修改电路衬底中形成的凹穴形状与大小。从图15B的平面视图来看，有两凹穴CV1和CV2容纳两个半导体管芯140，底板605位于凹穴CV2之下，底板跨度比凹穴CV2的跨度大。在某些实施例中，凹穴CV1之下没有底板，但其他功能金属化图形可能存在于凹穴CV1之下。
在某些实施例中，如图12中所示，与图6中描述的封装单元相似的封装结构10安装到电路衬底600的顶表面600T上，而封装结构10通过接合连结物610和连接件150连接到电路衬底600的垫606。在某些实施例中，通过执行回流焊接工艺，封装结构10的连接件150和衬底600的接合连结物610接合且融合在一起成为融合的连接件630。在某些实施例中，回流焊接工艺包括执行热工艺将连接件150变成熔化的状态或半熔化的状态以与接合连结物610整合键合成为位于封装结构10和电路衬底600之间的融合连接件630。回流焊接温度可以高于连接件150和/或接合连结物610的熔融点。在某些实施例中，导电球620的尺寸或大小大于连接件630的尺寸或大小，连接件630大于封装结构10中的接触点142和122。通过这些导电连接配置，精细节距的半导体管芯120电连接到较大节距的半导体管芯140和更大节距的电路衬底600。
键合封装结构10与电路衬底600之后，半导体管芯140位于凹穴CV中。由于电路衬底中的凹穴容纳了安装到电路衬底的封装单元突出的管芯，因此整个封装结构的总厚度可能会减少。从图12中可以看出，凹穴CV的尺寸大于半导体管芯140，半导体管芯140与凹穴CV的侧壁和底部间隔开来而之间有空间存在。在某些实施例中，半导体管芯140的背表面140S与凹穴CV的底面相隔一距离Dt，距离Dt范围从约1微米到约100微米。举例来说，距离Dt比凹穴的深度Dcv小，且Dt/Dcv比例范围约0.1至约0.5。尽管在图15A中示出，一个半导体管芯140位于凹穴CV内，但是可以理解，在凹穴CV中可以容纳不止一个管芯。在某些实施例中，当图8和图9中所示的封装单元安装到电路衬底时，电路衬底可能包括单一个凹穴以在同一个凹穴中容纳两个或四个管芯，或多个凹穴以一对一方式在其中容纳一个或多个管芯。
在图13中，在某些实施例中，形成底充胶640并填充在封装结构10和电路衬底600之间以形成半导体组件封装结构13。在某些实施例中，底充胶640填充在半导体管芯140和凹穴CV之间，并填充在位于封装单元10和电路衬底600之间的融合连接件630之间。在某些实施例中，所形成的底充胶640为无空隙填充材料填充凹穴CV以及填充于封装单元10和电路衬底600之间。底充胶640可以保护融合的连接件630免受热或物理应力的影响，并进一步保护位于电路衬底600的凹穴CV中的半导体管芯140。由于凹穴CV的侧壁和底面没有暴露出金属化图形或迹线，因此在凹穴CV的底充胶640和表面之间实现了更好的附着性，提升整个组件结构的可靠性。
在一些实施例中，在图13中，底充胶640是由毛细管底充胶填充(CUF)形成的，底充胶640不仅填充了封装结构10和电路衬底600之间的空隙，而且还溢流出来部分覆盖重布线层110的侧壁。在一些实施例中，如图13A所示，底充胶640A由转移成型所形成，底充胶640A的侧壁是共面的，与重布线层110的侧壁垂直对齐。在某些实施例中，可以进行固化工艺以巩固底充胶640。在一些实施例中，由于凹穴CV的侧壁和底面没有暴露出金属化图形或迹线，所以后来填充的底充胶640和凹穴CV的表面(例如介电材料601的介电表面)具有良好的附着性，且封装组件结构的耐受性和可靠性变得更好。
本发明不受半导体封装类型的限制，也不受半导体封装10连接到电路衬底600的数量的限制。在本公开的图中，为了说明的目的，集成扇出型(InFO)封装显示为半导体封装单元。然而，显然可以使用其他类型的半导体封装来生产包括在此公开的电路衬底的半导体组件封装结构，并且所有这些半导体组件旨在落入本说明和所附权利要求的范围之内。举例来说，衬底上晶片上芯片(Chip-on-Wafer-on-Substrate，CoWoS)结构、三维集成电路(3DIC)结构、晶片上芯片(CoW)封装、层叠封装(PoP)结构都可以用作半导体封装单元，单独或在组合中使用。
从图14A的示例性示意性视图来看，半导体管芯140与两个半导体管芯120是通过接触点122、142与重布线层110的垂直堆叠金属化图案VM达到电连接。在一些实施例中，半导体管芯140可作为桥接组件用于通过垂直堆叠金属化图案VM电连接两个半导体管芯120，这导致更短的电路径和更好的电效能。在某些实施例中，垂直堆叠金属化图案VM包括相互垂直对齐堆叠的通孔和夹在堆叠通孔之间的金属图案。
在其他一些实施例中，参考图14B，半导体管芯140A还包括贯穿半导体管芯140A的半导体穿孔(through semiconductor via，TSV)140V，位于凹穴CV内的半导体管芯140A是通过凸块Bp电连接至电路衬底600的凹穴CV下方的金属化图形602。即封装结构的半导体管芯140A是电连接至电路衬底600的金属化图形602。参考图14B，半导体管芯140A可作为封装单元的其他管芯的桥接组件，将上面的封装单元和下面的电路衬底电性连接成为电连接路径的部分，进一步缩短了电的导通路径，提高了整体结构的效能。以图15B中描述的结构为例，图14B中描述的连结方案可以适用于凹穴CV2中的半导体管芯。
根据一些实施例，半导体封装至少包括电路衬底、半导体管芯和填充材料。电路衬底有第一表面，与第一表面相反的第二表面和从第一表面凹进去的凹穴。电路衬底包括介电材料和埋设在介电材料中并位于凹穴下方的金属底板。金属底板的位置对应于凹穴的位置。金属底板是电性浮置且被介电材料隔离。半导体管芯设置在凹穴中且与电路衬底电连接。填充材料设置在半导体管芯和电路衬底之间，填充材料填充凹穴且封装半导体管芯而连接半导体管芯和电路衬底。
根据本公开的一些实施例，半导体封装进一步包括重布线层，设置在并且连接到所述半导体管芯的有源表面并且连接到所述电路衬底的所述第一表面。根据本公开的一些实施例，其中所述半导体管芯通过所述重布线层电连接到所述电路衬底。根据本公开的一些实施例，半导体封装进一步包括模封结构设置在所述重布线层上，其中所述模封结构包括另一个半导体管芯电连接到所述重布线层和所述半导体管芯，且电连接到所述电路衬底。根据本公开的一些实施例，其中所述重布线层包括垂直堆叠金属化图案，且所述半导体管芯通过所述垂直堆叠金属化图案电连接到所述另一个半导体管芯。
根据本公开的一些实施例，其中所述半导体管芯包括贯穿穿透所述半导体管芯的半导体穿孔，并且所述半导体管芯通过所述半导体穿孔电连接到所述电路衬底。根据本公开的一些实施例，其中所述凹穴的底面与所述金属底板隔开一距离且所述介电材料夹在其间。
根据本公开的一些实施例，其中所述凹穴的垂直投影落入所述金属底板的跨度内。
根据本公开的一些实施例，其中所述凹穴的垂直投影与所述金属底板交叠。
根据一些实施例，半导体封装至少包括具有第一表面和与第一表面相对的第二表面的重布线层、设置在重布线层的第一表面上的模封结构以及电路衬底。模封结构包括侧向地被模制化合物包围的第一管芯和第二管芯，第一和第二管芯是和重布线层电连接。电路衬底与重布线层的第二表面相连。电路衬底包括介电材料、凹穴下凹进介电材料且具有无金属的介电表面以及埋设于介电材料中并位于凹穴下方的底板。第三管芯设置在重布线层的第二表面上和重布线层电连接的。第三管芯位于凹穴内，底充胶位于第三管芯和凹穴之间以及位于电路衬底和重布线层之间。
根据本公开的一些实施例，其中夹在所述底板和所述凹穴的底面之间的所述介电材料具有从约1微米到约100微米的厚度。
根据本公开的一些实施例，其中所述凹穴的垂直投影落在所述底板的跨度内，并且所述底板的所述跨度大于所述凹穴的跨度。
根据本公开的一些实施例，其中所述底板包括具有网格图案的单金属板，且所述凹穴的垂直投影和所述单金属板交叠。
根据本公开的一些实施例，其中所述底板包括多个平行排列的金属板，且所述凹穴的垂直投影和所述多个平行排列的金属板交叠。
根据本公开的一些实施例，其中所述第三管芯的背表面与所述凹穴的底面相距约1微米至约100微米的距离。
根据本公开的一些实施例，其中所述第三管芯被所述底充胶包封并且所述第三管芯通过所述重布线层电连接到所述电路衬底。
根据本公开的一些实施例，其中所述第三管芯包括贯穿穿透所述第三管芯的半导体穿孔，并且所述第三管芯通过所述半导体穿孔电连接到所述电路衬底。
根据一些实施例，提供了制造方法。形成重布线层。第一半导体管芯键合到重布线层的第一表面上。半导体管芯与模制化合物一起成型。第二半导体管芯键合到重布线层的与第一表面相对的第二表面上。提供具有介电材料和埋设在介电材料中的底板的电路衬底。通过去除介电层的部分而不暴露底板，在电路衬底中形成凹穴。电路衬底与重布线层相连，第二半导体管芯容纳在凹穴中。底充胶分配到凹穴中以填充凹穴并围绕第二半导体管芯并填充在电路衬底和重布线层之间。
根据本公开的一些实施例，其中在所述电路衬底中形成凹穴包括执行机械烧蚀工艺以移除所述介电材料并在来自所述底板的距离处停止。
根据本公开的一些实施例，其中在所述电路衬底中形成凹穴包括执行激光烧蚀工艺以移除所述介电材料，并在离所述底板一距离处停止。
前文概述若干实施例的特征，使得本领域的技术人员可更好地理解本公开的各方面。本领域的技术人员应了解，其可容易地将本公开用作设计或修改用于进行本文中所引入的实施例的相同目的和/或实现相同优势的其它工艺和结构的基础。本领域的技术人员还应认识到，这些等效构造并不脱离本公开的精神和范围，且本领域的技术人员可在不脱离本公开的精神和范围的情况下在本文中进行各种改变、替代和更改。

Claims (10)

1.一种半导体封装，包括：
电路衬底，具有第一表面与所述第一表面相对的第二表面和从所述第一表面凹入的凹穴，其中所述电路衬底包括介电材料和埋设于所述介电材料中且位于所述凹穴下方的金属底板，其中所述金属底板的位置对应于所述凹穴的位置，并且所述金属底板是电性浮置且被所述介电材料隔离；
半导体管芯，设置于所述凹穴内且与所述电路衬底电连接；以及
填充材料，设置于所述半导体管芯和所述电路衬底之间，其中所述填充材料填充所述凹穴并封装所述半导体管芯以连接所述半导体管芯和所述电路衬底。
2.根据权利要求1所述的半导体封装，其中所述半导体管芯包括贯穿穿透所述半导体管芯的半导体穿孔，并且所述半导体管芯通过所述半导体穿孔电连接到所述电路衬底。
3.根据权利要求1所述的半导体封装，其中所述凹穴的底面与所述金属底板隔开一距离且所述介电材料夹在其间。
4.根据权利要求1所述的半导体封装，其中所述凹穴的垂直投影落入所述金属底板的跨度内。
5.根据权利要求1所述的半导体封装，其中所述凹穴的垂直投影与所述金属底板交叠。
6.一种半导体封装，包括：
重布线层，具有第一表面和与所述第一表面相反的第二表面；
模封结构，设置在所述重布线层的所述第一表面上，其中所述模封结构包括第一管芯和第二管芯侧向地被模制化合物包围，所述第一管芯和所述第二管芯电连接到所述重布线层；
电路衬底，与所述重布线层的所述第二表面相连，其中所述电路衬底包括介电材料、凹穴凹入所述介电材料且具有无金属的介电表面，以及底板埋设于所述介电材料且位于所述凹穴下方；
第三管芯，设置于所述重布线层的所述第二表面上，位于所述凹穴内且与所述重布线层电连接；以及
底充胶，设置于所述第三管芯和所述凹穴之间以及所述电路衬底和所述重布线层之间。
7.根据权利要求6所述的半导体封装，其中所述第三管芯的背表面与所述凹穴的底面相距1微米至100微米的距离。
8.根据权利要求6所述的半导体封装，其中所述第三管芯被所述底充胶包封并且所述第三管芯通过所述重布线层电连接到所述电路衬底。
9.一种半导体封装制造方法，包括：
形成重布线层；
键合第一半导体管芯到所述重布线层的第一表面；
以模制化合物模塑所述半导体管芯；
键合第二半导体管芯到所述重布线层的与所述第一表面相对的第二表面；
提供具有介电材料和埋设在所述介电材料中的底板的电路衬底；
通过去除所述介电层的部分而不暴露所述底板而在所述电路衬底中形成凹穴；
将所述电路衬底与所述重布线层连接，在所述凹穴中容纳所述第二半导体管芯；以及
将底充胶分配到所述凹穴以填充所述凹穴，包围所述第二半导体管芯，并填充至所述电路衬底和所述重布线层之间。
10.根据权利要求9所述的半导体封装制造方法，其中在所述电路衬底中形成凹穴包括执行机械烧蚀工艺以移除所述介电材料并在来自所述底板的距离处停止。
CN202210041865.7A 2021-08-31 2022-01-14 半导体封装及其制造方法 Pending CN115513189A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/462,000 2021-08-31
US17/462,000 US11908764B2 (en) 2021-08-31 2021-08-31 Semiconductor package including a circuit substrate having a cavity and a floor plate embedded in a dielectric material and a semiconductor die disposed in the cavity

Publications (1)

Publication Number Publication Date
CN115513189A true CN115513189A (zh) 2022-12-23

Family

ID=84500633

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210041865.7A Pending CN115513189A (zh) 2021-08-31 2022-01-14 半导体封装及其制造方法

Country Status (3)

Country Link
US (2) US11908764B2 (zh)
CN (1) CN115513189A (zh)
TW (1) TWI788189B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220149005A1 (en) * 2020-11-10 2022-05-12 Qualcomm Incorporated Package comprising a substrate and a high-density interconnect integrated device

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6982491B1 (en) * 2004-01-20 2006-01-03 Asat Ltd. Sensor semiconductor package and method of manufacturing the same
TWI352406B (en) * 2006-11-16 2011-11-11 Nan Ya Printed Circuit Board Corp Embedded chip package with improved heat dissipati
TWI344694B (en) * 2007-08-06 2011-07-01 Siliconware Precision Industries Co Ltd Sensor-type package and method for fabricating the same
US8367477B2 (en) * 2009-03-13 2013-02-05 Wen-Cheng Chien Electronic device package and method for forming the same
US9385095B2 (en) * 2010-02-26 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US9048233B2 (en) * 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US20110316140A1 (en) * 2010-06-29 2011-12-29 Nalla Ravi K Microelectronic package and method of manufacturing same
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8927339B2 (en) * 2010-11-22 2015-01-06 Bridge Semiconductor Corporation Method of making thermally enhanced semiconductor assembly with bump/base/flange heat spreader and build-up circuitry
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US8536695B2 (en) * 2011-03-08 2013-09-17 Georgia Tech Research Corporation Chip-last embedded interconnect structures
US8487426B2 (en) * 2011-03-15 2013-07-16 Advanced Semiconductor Engineering, Inc. Semiconductor package with embedded die and manufacturing methods thereof
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US9899238B2 (en) * 2014-12-18 2018-02-20 Intel Corporation Low cost package warpage solution
US9620465B1 (en) * 2016-01-25 2017-04-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dual-sided integrated fan-out package
KR102595896B1 (ko) * 2016-08-08 2023-10-30 삼성전자 주식회사 인쇄회로기판 및 이를 가지는 반도체 패키지
KR101963292B1 (ko) * 2017-10-31 2019-03-28 삼성전기주식회사 팬-아웃 반도체 패키지
US10804254B2 (en) * 2018-06-29 2020-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package with cavity substrate
US10832985B2 (en) * 2018-09-27 2020-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Sensor package and method
US11380620B2 (en) * 2019-06-14 2022-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package including cavity-mounted device
US11443993B2 (en) * 2019-09-09 2022-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with cavity in interposer

Also Published As

Publication number Publication date
TWI788189B (zh) 2022-12-21
US20230386956A1 (en) 2023-11-30
TW202312377A (zh) 2023-03-16
US20230067914A1 (en) 2023-03-02
US11908764B2 (en) 2024-02-20

Similar Documents

Publication Publication Date Title
US11824040B2 (en) Package component, electronic device and manufacturing method thereof
US11476125B2 (en) Multi-die package with bridge layer
US10867949B2 (en) Substrate design for semiconductor packages and method of forming same
US10276509B2 (en) Integrated fan-out package
US10026671B2 (en) Substrate design for semiconductor packages and method of forming same
US9935090B2 (en) Substrate design for semiconductor packages and method of forming same
CN115910814A (zh) 形成封装结构的方法
CN115632042A (zh) 半导体装置
KR101684787B1 (ko) 반도체 패키지 디바이스 및 그 형성 방법
KR101859340B1 (ko) 반도체 패키지용 기판 설계 및 그 형성 방법
US11610864B2 (en) Chip package structure and method of forming the same
US20220359335A1 (en) Semiconductor package and manufacturing method thereof
CN107301981B (zh) 集成的扇出型封装件以及制造方法
US20230386956A1 (en) Manufacturing method of semiconductor package
US11756873B2 (en) Semiconductor package and manufacturing method thereof
US11398422B2 (en) Package structure and fabricating method thereof
US11270921B2 (en) Semiconductor package including dies having high-modulus dielectric layer and manufacturing method thereof
US20240063130A1 (en) Package structure and fabricating method thereof
CN219716864U (zh) 包括铜柱数组的半导体结构
CN220121823U (zh) 集成电路封装
US20240071888A1 (en) Package structure
CN113838840A (zh) 半导体封装及制造半导体封装的方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination