TW202310257A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

Info

Publication number
TW202310257A
TW202310257A TW111103075A TW111103075A TW202310257A TW 202310257 A TW202310257 A TW 202310257A TW 111103075 A TW111103075 A TW 111103075A TW 111103075 A TW111103075 A TW 111103075A TW 202310257 A TW202310257 A TW 202310257A
Authority
TW
Taiwan
Prior art keywords
conductive connection
wafer
semiconductor device
metal layer
electrode
Prior art date
Application number
TW111103075A
Other languages
English (en)
Other versions
TWI824396B (zh
Inventor
築山慧至
青木秀夫
大田洋
山田朋恭
高橋祐樹
Original Assignee
日商鎧俠股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商鎧俠股份有限公司 filed Critical 日商鎧俠股份有限公司
Publication of TW202310257A publication Critical patent/TW202310257A/zh
Application granted granted Critical
Publication of TWI824396B publication Critical patent/TWI824396B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8314—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1438—Flash memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1611—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1811—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/182—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

本實施形態的半導體裝置是具備基板及半導體晶片。基板是具有：第1面，及被設在第1面上的複數的導電連接部。半導體晶片是具有：與第1面對向的第2面，及被設在第2面上，與複數的導電連接部的各者電性連接的複數的連接凸塊。在配置有半導體晶片的第1面上的晶片區域之中的晶片外周區域所配置的導電連接部是具有與在晶片區域之中的晶片中心區域所配置的導電連接部不同的厚度。

Description

半導體裝置及其製造方法
本實施形態是關於半導體裝置及其製造方法。 [關聯申請案的引用] 本案是以2021年08月17日申請的日本專利申請案第2021-132880號為基礎主張優先權，且在此引用其內容全體。
在半導體裝置的封裝構造中，有半導體晶片被覆晶連接於配線基板的情況。但，因為半導體晶片的彎曲，有難以將半導體晶片適當地連接至配線基板的情況。
一實施形態是提供一種可使晶片更適當地連接至基板的半導體裝置及其製造方法。
本實施形態的半導體裝置是具備基板及半導體晶片。基板是具有：第1面，及被設在第1面上的複數的導電連接部。半導體晶片是具有：與第1面對向的第2面，及被設在第2面上，與複數的導電連接部的各者電性連接的複數的連接凸塊。在配置有半導體晶片的第1面上的晶片區域之中的晶片外周區域所配置的導電連接部是具有與在晶片區域之中的晶片中心區域所配置的導電連接部不同的厚度。
若根據上述的構成，則可提供一種可使晶片更適當地連接至基板的半導體裝置及其製造方法。
以下，參照圖面說明本發明的實施形態。本實施形態不是限定本發明者。在以下的實施形態中，配線基板的上下方向是表示以設有半導體晶片的面作為上面時的相對方向，有時與按照重力加速度的上下方向不同。圖面是模式性或概念性者，各部分的比率等是未必一定要與現實者相同。在說明書與圖面中，關於已出的圖面，和前述者同樣的要素是附上相同的符號，而詳細的說明是適當省略。
(第1實施形態) 圖1是表示第1實施形態的半導體裝置1的構成之一例的剖面圖。半導體裝置1是具備配線基板10、半導體晶片20、30~33、黏著層40~43、間隔件50、51、黏著層60、61、金屬材料70、樹脂層80、接合線90及密封樹脂91。半導體裝置1是例如NAND型快閃記憶體的封裝。
配線基板10是可為含有配線層11及絕緣層15的印刷基板或中介層(interposer)。配線層11是例如可使用銅(Cu)、鎳(Ni)或該等的合金等的低電阻金屬。絕緣層15是例如可使用玻璃環氧樹脂等的絕緣性材料。就圖而言，是只在絕緣層15的表面及背面設有配線層11。但，配線基板10是亦可具有層疊複數的配線層11及複數的絕緣層15而構成的多層配線構造。配線基板10是例如中介層般，亦可具有貫通其表面及背面的貫通電極12(柱狀電極16)。
在配線基板10的表面(面F1)是設有被設在配線層11上的阻焊劑層14。阻焊劑層14是自金屬材料70保護配線層11，用以抑制短路不良的絕緣層。
在配線基板10的背面也設有被設在配線層11上的阻焊劑層14。在從阻焊劑層14露出的配線層11是設有金屬凸塊13。金屬凸塊13是為了電性連接未圖示的其他的零件與配線基板10而設。
半導體晶片20是例如控制記憶體晶片的控制器晶片。在半導體晶片20的朝向配線基板10的面F2是設有未圖示的半導體元件。半導體元件是例如可為構成控制器的CMOS(Complementary Metal Oxide Semiconductor)電路。在半導體晶片20的背面(下面) 的面F2是設有與半導體元件電性連接的電極支柱21。電極支柱21是例如可使用銅、鎳或該等的合金等的低電阻金屬材料。
在作為連接凸塊的電極支柱21的周圍是設有金屬材料70。電極支柱21是經由金屬材料70來與在阻焊劑層14的開口部露出的配線層11電性連接。金屬材料70是例如可使用焊錫、銀、銅等的低電阻金屬材料。金屬材料70是例如在開口部內被覆配線基板10的配線層11的一部分，且半導體晶片20的電極支柱21的側面的一部分也被覆。藉此，金屬材料70是電性連接半導體晶片20的電極支柱21與配線基板10的配線層11。
在金屬材料70的周圍的區域，及半導體晶片20與配線基板10之間的區域是設有樹脂層80。樹脂層80是例如使底部填充膠(Underfill)樹脂硬化者，被覆半導體晶片20的周圍而保護。
半導體晶片30是例如含有NAND型快閃記憶體的記憶體晶片。半導體晶片30是在其表面(上面)具有半導體元件(未圖示)。半導體元件是例如可為記憶格陣列及其周邊電路(CMOS電路)。記憶格陣列是可為立體配置複數的記憶格的立體型記憶格陣列。並且，在半導體晶片30上是經由黏著層41來黏著半導體晶片31。在半導體晶片31上是經由黏著層42來黏著半導體晶片32。在半導體晶片32上是經由黏著層43來黏著半導體晶片33。半導體晶片31~33是例如與半導體晶片30同樣，含有NAND型快閃記憶體的記憶體晶片。半導體晶片30~33是可為相同的記憶體晶片。就圖而言，是除了作為控制器晶片的半導體晶片20以外，還層疊有作為4個記憶體晶片的半導體晶片30~ 33。但，半導體晶片的層疊數是可為3個以下，或亦可為5個以上。
間隔件50是例如設在半導體晶片20的側方。間隔件50是經由黏著層60來黏著於配線基板10的表面(上面)。黏著層60是被設在配線基板10與間隔件50之間。間隔件51是被設在半導體晶片20的上方。在間隔件51的上方設有半導體晶片30~33。間隔件51是經由黏著層61來黏著於間隔件50的上面。黏著層61是被設在間隔件50與間隔件51之間。間隔件50、51的材料是例如矽(Si)或聚醯亞胺。
接合線90是被連接至配線基板10及半導體晶片30~33的任意的焊墊。為了以接合線90連接，半導體晶片30~33是僅焊墊份錯開層疊。另外，半導體晶片20是藉由電極支柱21來覆晶連接，因此打線接合是未被進行。但，半導體晶片20也除了藉由電極支柱21的連接以外，即使被打線接合也無妨。
進一步，密封樹脂91會將半導體晶片20、30~33、黏著層40~43、60、61、間隔件50、51、接合線90等密封。藉此，半導體裝置1是使複數的半導體晶片20、30~33在配線基板10上構成為1個的半導體封裝。當無樹脂層80時，亦可密封樹脂91取代樹脂層80，位於金屬材料70的周圍的區域及半導體晶片20與配線基板10之間的區域。
其次，說明有關配線基板10與半導體晶片20之間的連接的詳細。
圖2是表示第1實施形態的半導體晶片20及其周邊的構成之一例的剖面圖。另外，圖2是將半導體晶片20連接至配線基板10的時機的剖面圖。配線基板10與半導體晶片20的連接的時機是例如回流(reflow)工序，被加熱處理至金屬材料70的融點以上的溫度的期間。又，就圖2而言，最上層的配線層11會擴大於厚度方向而示。
被配置於面F1側的最上層的配線層11是包括複數的導電連接部111及周邊配線112。
導電連接部111是被設在面F1上。導電連接部111是被配置於配置有半導體晶片20的面F1上的晶片區域R1。導電連接部111是至少一部分從阻焊劑層14露出。導電連接部111是藉由與金屬材料70接觸，使配線基板10與半導體晶片20電性連接。被設在面F2上的複數的電極支柱21是與被設在面F1上的複數的導電連接部111的各者電性連接。
導電連接部111是包括導電連接部111a及導電連接部111b。
導電連接部111a是被配置於晶片區域R1之中的晶片中心區域R11。又，導電連接部111a的側面是例如以阻焊劑層14所覆蓋。
導電連接部111b是被配置於晶片區域R1之中的晶片外周區域R12。又，導電連接部111b的側面是例如從阻焊劑層14露出。
晶片區域R1是例如被分割成晶片中心區域R11及晶片中心區域R11的外周的晶片外周區域R12。晶片中心區域R11的面積是例如晶片大小的2分之1以下，晶片外周區域R12的面積是例如晶片大小的2分之1以上。但，面積的比例是不限於此，亦可被變更。
周邊配線112是被設在面F1上。周邊配線112是被配置於與晶片區域R1不同的面F1上的周邊區域R2。周邊配線112是例如被阻焊劑層14覆蓋。另外，周邊配線112是例如亦可一部分從阻焊劑層14露出，使得與圖1所示的接合線90電性連接。
在此，圖2所示的半導體晶片20是在回流工序中，彎曲成下凸。半導體晶片20的彎曲是例如因為半導體基板的材料(例如矽(Si))與半導體元件的金屬之間的熱膨脹係數的差而產生。
如圖2所示般，被配置於晶片外周區域R12的導電連接部111b是具有與被配置於晶片中心區域R11的導電連接部111a不同的厚度。藉此，即使在半導體晶片20產生彎曲，還是可更適當地連接配線基板10與半導體晶片20。
更詳細，被配置於晶片外周區域R12的導電連接部111b是比被配置於晶片中心區域R11的導電連接部111a更厚。藉此，即使半導體晶片20彎曲成下凸，還是可適當地進行晶片外周區域R12的配線基板10與半導體晶片20的連接。
又，被配置於晶片外周區域R12的導電連接部111b的厚度與被配置於晶片中心區域R11的導電連接部111a的厚度的差是對應於與配線基板10連接的時機的半導體晶片20的彎曲為理想。半導體晶片20的彎曲的量是例如半導體晶片20的中心部與外周端部之間的高度的差。
複數的導電連接部111a、111b之中，導電連接部111a、111b的厚度的最大值與最小值的差是例如約3μm~約20μm的範圍內。更詳細，導電連接部111a與導電連接部111b的高度的差是例如約3μm~約20μm的範圍內。
又，周邊配線112是具有導電連接部111a的厚度與導電連接部111b的厚度之間的厚度。
圖3是表示第1實施形態的半導體裝置1的構成之一例的平面圖。圖3的A-A線是表示對應於剖面圖的圖2的剖面。
就圖3所示的例子而言，阻焊劑層14(SR)是不被設在晶片外周區域R12，絕緣層15(例如預浸料坯 (PP、Prepreg))會在晶片外周區域R12露出。
導電連接部111a是例如具有焊墊形狀。圖3所示的導電連接部111a的形狀是大略橢圓形，或亦可為矩形或大略圓形等。導電連接部111a的上面是從阻焊劑層14露出。導電連接部111b是例如具有配線形狀(手指(finger)狀)。圖3所示的導電連接部111b是具有細長的形狀。又，如圖3所示般，導電連接部111a的面積是比導電連接部111b的面積更大。
其次，說明有關導電連接部111a、111b的詳細。
圖4A及圖4B是表示第1實施形態的半導體裝置1的構成之一例的剖面圖。圖4A是表示被配置於晶片中心區域R11的導電連接部111a的剖面圖。圖4B是表示被配置於晶片外周區域R12的導電連接部111b的剖面圖。
配線基板10是更具有複數的柱狀電極(VIA)16。柱狀電極16是使最上層的配線層11與其他的配線層11電性連接。柱狀電極16是例如被設為從配線基板10內的內部配線113延伸至面F1的法線方向。複數的柱狀電極16是與複數的導電連接部111的各者電性連接。
導電連接部111a是如圖3及圖4A所示般，從面F1的法線方向看，被配置為與柱狀電極16重疊。導電連接部111a及柱狀電極16是例如具有導通孔在墊(pad on via)構造。
導電連接部111b是如圖3及圖4B所示般，從面F1的法線方向看，離開柱狀電極16而配置。亦即，導電連接部111b是被配置為從柱狀電極16沿著面F1來拉出。
又，如在圖2所說明般，導電連接部111b是比導電連接部111a更厚。
其次，說明有關半導體裝置1的製造方法。另外，更詳細說明有關圖4A及圖4B所示的導電連接部111a、111b的形成方法。
圖5~圖10是表示第1實施形態的半導體裝置1的製造方法之一例的剖面圖。圖5~圖10是表示晶片中心區域R11及晶片外周區域R12的各者的剖面圖。
首先，如圖5所示般，準備配線基板10。就圖5所示的例子而言，配線基板10是具有3層的絕緣層151~153及4層的配線層L1~L4。絕緣層151~153是在絕緣層15所含的各個的層，例如預浸料坯 (prepreg)。在配線層L2、L3是藉由使用光蝕刻法(photolithography)等的圖案化來形成電路。在配線層L1、L4是例如形成有薄的銅箔17。就圖5所示的例子而言，在配線層L2與配線層L3之間形成柱狀電極16。又，就圖5而言，是顯示一部分的內部配線113。
其次，如圖6所示般，從面F1側，在絕緣層153形成到達至配線層L2的內部配線113的穴(hole)10h。穴10h是例如藉由雷射等所形成。
其次，如圖7所示般，在配線層L1的銅箔17上形成作為遮罩機能的抗鍍劑層18，以填埋穴10h的方式形成金屬層M1。另外，在形成金屬層M1之前，亦可在穴10h內(例如側壁)形成種子層(未圖示)。例如，藉由濺射來形成鉻(Cr)、鈦(Ti)或該等的合金，然後，藉由無電解電鍍來形成銅，藉此形成種子層。抗鍍劑層18是例如被形成為使得形成柱狀電極16的區域的穴10h開口。金屬層M1為底層。金屬層M1是被形成為比穴10h更低。亦即，金屬層M1是被形成至比面F1更低的預定的高度。更詳細，金屬層M1是被形成為從內部配線113延伸至比面F1更低的預定的高度。金屬層M1是例如藉由無電解電鍍所形成。
就無電解電鍍而言，當表面的狀態為相同時，電鍍反應形成相同。因此，被配置於晶片中心區域R11的金屬層M1的厚度是與被配置於晶片外周區域R12的金屬層M1的厚度幾乎相同。亦即，複數的金屬層M1的厚度是大致相同。
其次，如圖8所示般，將抗鍍劑層18剝離，在配線層L1的銅箔17上再度形成抗鍍劑層18，在配線層L1的銅箔17(面F1)上及金屬層M1上形成金屬層M2。抗鍍劑層18是例如被形成為使得形成導電連接部111a、111b的區域開口。金屬層M2是例如藉由電解電鍍來形成。電解電鍍是可比無電解電鍍更短時間形成金屬層M2。
其次，如圖9所示般，將抗鍍劑層18剝離，以金屬層M1、M2作為遮罩蝕刻銅箔17。
在此，如圖9所示般，金屬層M1(柱狀電極16)附近的金屬層M2是被形成比離開金屬層M1(柱狀電極16)的金屬層M2的上面更厚。這是為了以金屬層M1會比面F1更低的方式形成金屬層M1。金屬層M1附近的金屬層M2是被形成為一部分會填埋穴10h。另一方面，離開金屬層M1的金屬層M2是從面F1形成於厚度方向。因此，藉由調整金屬層M1的厚度，可調整導電連接部111a的厚度與導電連接部111b的厚度的差。亦即，在圖8所示的工序中，在面F1上的晶片中心區域R11，從面F1的法線方向看，形成與柱狀電極16重疊的導電連接部111a，且在面F1上的晶片外周區域R12，從面F1的法線方向看，形成離開柱狀電極16的導電連接部111b。
其次，如圖10所示般，形成貫通絕緣層151的柱狀電極16。並且，在配線層L4，進行使用光蝕刻法(photolithography)等的圖案化，藉由電鍍等來形成電路。又，形成阻焊劑層14。例如，在配線基板10的兩面塗佈阻焊劑，使曝光及顯像、硬化。藉此，如圖4A及圖4B所示般，可形成按照面F1上的位置而具有不同的厚度的導電連接部111a、111b。然後，以電極支柱21與導電連接部111a、111b會電性連接的方式，將半導體晶片20設在配線基板10。其次，藉由設置間隔件50、51及半導體晶片30~33等，完成圖1所示的半導體裝置1。
如上述般，導電連接部111及柱狀電極16是包括金屬層M1及金屬層M2。金屬層M1是例如被設為從被設在配線基板10的內部的內部配線113延伸至面F1的法線方向。金屬層M2是被設在金屬層M1的上方，與金屬層M1不同。
在金屬層M1與金屬層M2之間，例如材料不同。金屬層M1、M2是例如可使用銅、鎳、金(Au)或該等的合金等的低電阻金屬材料。
又，金屬層M1及金屬層M2是有使用不同的電鍍液來形成的情況。此情況，例如，在金屬層M1與金屬層M2之間，即使材料為相同，也會有例如雜質的濃度及種類(物質)不同的可能性。雜質是例如來自電鍍液的添加劑。在第1實施形態中，金屬層M1、M2是分別藉由無電解電鍍及電解電鍍來形成，因此通常藉由彼此不同的電鍍液來形成，又，使用彼此不同的爐來形成。此結果，在金屬層M1與金屬層M2之間，會有混入的雜質的狀態變化的可能性。
如以上般，若根據第1實施形態，則導電連接部111b是具有與導電連接部111a不同的厚度。
若導電連接部111a、111b的厚度不同，連接時的半導體晶片20彎曲成下凸時，因為被配置於晶片外周區域R12的導電連接部111b會離開電極支柱21，而有發生連接不良的可能性。
對於此，就第1實施形態而言，是在導電連接部111a與導電連接部111b之間厚度不同。藉此，即使在半導體晶片20產生彎曲，還是可更適當地連接配線基板10與半導體晶片20。
又，就第1實施形態而言，從面F1的法線方向看，可按照導電連接部111是否與柱狀電極16重疊，來分別改變導電連接部111a、111b的厚度。藉此，可同時並行形成具有不同的厚度的導電連接部111a、111b。
又，複數的導電連接部111a的厚度是亦可在晶片中心區域R11內不同，複數的導電連接部111b的厚度是亦可在晶片外周區域R12內不同。導電連接部111a、111b的厚度是例如亦可從半導體晶片20的中心部到外周端部，慢慢地變化。更詳細，導電連接部111a、111b的厚度是亦可從半導體晶片20的中心部到外周端部，慢慢地變厚。此結果，可更適當地連接配線基板10與半導體晶片20。這是因為半導體晶片20的彎曲，從半導體晶片20的中心部到外周端部，配線基板10與半導體晶片20之間的距離會慢慢地變大。
又，就第1實施形態而言，導電連接部111a是焊墊狀，導電連接部111b是配線狀(手指狀)。又，比導電連接部111a更厚的導電連接部111b是側面會從阻焊劑層14露出，金屬材料70(例如焊錫)會按照半導體晶片20的彎曲而濕潤。藉此，可利用被配置於晶片外周區域R12的導電連接部111b的側面來吸收彎曲所致的半導體晶片20的高度變化。
另外，半導體晶片20是依構成而有在連接時彎曲成上凸的情況。此情況，只要導電連接部111a比導電連接部111b更厚即可。因此，只要將導電連接部111a、111b與柱狀電極16之間的配置的關係設為相反即可。亦即，導電連接部111a是從面F1的法線方向看，離開柱狀電極16而配置。導電連接部111b是從面F1的法線方向看，被配置為與柱狀電極16重疊。
又，導電連接部111a、111b、周邊配線112及金屬層M1、M2的厚度是亦可作為上面的高度。
又，半導體晶片20的電極支柱21是亦可從半導體晶片20的中心部到外周端部，具有大致相同的厚度或大致相同的直徑。亦即，半導體晶片20的電極支柱21是亦可不拘位置，厚度及直徑等大略均一。
又，亦可使用阻焊劑層14作為抗鍍劑層18。
又，對於周邊配線112形成電鍍的時機是例如亦可與導電連接部111a、111b的形成金屬層M2的時機相同，或亦可相異。
(第2實施形態) 圖11是表示第2實施形態的半導體裝置1的構成之一例的平面圖。第2實施形態是與第1實施形態作比較，導電連接部111b的形狀，及導電連接部111b與柱狀電極16之間的位置關係不同。
就圖11所示的例子而言，阻焊劑層14是在晶片外周區域R12也設置，被設在晶片區域R1的幾乎全面。
導電連接部111b是例如與導電連接部111a同樣具有焊墊形狀。導電連接部111b的上面是從阻焊劑層14露出。導電連接部111b是例如具有導通孔在墊(pad on via)構造。
其次，說明有關導電連接部111a、111b的詳細。
圖12A及圖12B是表示第2實施形態的半導體裝置1的構成之一例的剖面圖。圖12A是表示被配置於晶片中心區域R11的導電連接部111a的剖面圖。圖12B是表示被配置於晶片外周區域R12的導電連接部111b的剖面圖。
導電連接部111a是如圖11及圖12A所示般，從面F1的法線方向看，被配置為與柱狀電極16重疊。導電連接部111a及柱狀電極16是例如具有導通孔在墊構造。
導電連接部111b是如圖11及圖12B所示般，從面F1的法線方向看，被配置為與柱狀電極16重疊。導電連接部111b及柱狀電極16是例如具有導通孔在墊構造。
如圖12A及圖12B所示般，導電連接部111b是比導電連接部111a更厚。
第2實施形態的半導體裝置1的其他的構成是與第1實施形態的半導體裝置1的對應的構成同樣，因此省略其詳細的說明。
其次，說明有關半導體裝置1的製造方法。另外，更詳細說明有關圖12A及圖12B所示的導電連接部111a、111b的形成方法。
圖13~圖15是表示第2實施形態的半導體裝置1的製造方法之一例的剖面圖。圖13~圖15是表示晶片中心區域R11及晶片外周區域R12的各者的剖面圖。
圖13~圖15所示的工序是在與圖5及圖6同樣的工序之後進行。
穴10h的形成後(參照圖6)，如圖13所示般，在配線層L1的銅箔17上形成作為遮罩機能的抗鍍劑層18，在穴10h內形成金屬層M1。另外，在形成金屬層M1之前，亦可在穴10h內(例如側壁)形成種子層。抗鍍劑層18是例如被形成為使得形成柱狀電極16的區域的穴10h開口。就圖13所示的例子而言，金屬層M1是被設置至面F1。金屬層M1是亦可被設置至比面F1更低的預定的高度，亦可被設置至比面F1更高的高度。金屬層M3是例如藉由無電解電鍍所形成。
其次，如圖14所示般，剝離抗鍍劑層18，在配線層L1的銅箔17上再度形成抗鍍劑層18，在配線層L1的銅箔17(面F1)上及金屬層M1上形成金屬層M2。抗鍍劑層18是例如被形成為使得形成導電連接部111、111b的區域開口。被配置於晶片外周區域R12的金屬層M2是比被配置於晶片中心區域R11的金屬層M2更厚。金屬層M2是例如藉由電解電鍍來形成。另外，有關金屬層M2的形成方法的詳細是參照圖16~圖18，之後說明。
其次，如圖15所示般，將抗鍍劑層18剝離，以金屬層M1、M2作為遮罩，將配線層L1的銅箔17蝕刻。
另外，被配置於晶片外周區域R12的金屬層M2會形成比被配置於晶片中心區域R11的金屬層M2更厚，因此導電連接部111b是比導電連接部111a更厚。
圖15所示的工序之後，進行與圖10同樣的工序。藉此，如圖12A及圖12B所示般，可形成按照面F1上的位置而具有不同的厚度的導電連接部111a、111b。
其次，說明有關金屬層M2的形成方法的詳細。
圖16是表示第2實施形態的電鍍裝置200的構成之一例的圖。電鍍裝置200是進行電解電鍍。電鍍裝置200是以電流密度會按照面F1上的位置而變化的方式電鍍金屬材料，藉此在面F1上形成按照面F1上的位置而具有不同的厚度的複數的金屬層M2(導電連接部111a、111b)。金屬層M2的電鍍厚度是根據電流密度及電鍍時間。更詳細，金屬層M2的厚度是和電流密度與電鍍時間的乘積成比例。因此，藉由使電解電鍍的電流密度變化，可在相同的電鍍時間，按照面F1上的位置來使金屬層M2的厚度變化。
電鍍裝置200是具備容器210、電源220及陽極230。
容器210是收容取多面基板100、陽極230及電鍍液。取多面基板100是例如在大型的基板中，配線基板10的同圖案的配線會被形成於複數處的基板。另外，取多面基板100是亦可為1個的配線基板10。
電源220是具有電源陰極221及電源陽極222。電源陰極221是與取多面基板100電性連接的端子。電源陽極222是與陽極230電性連接的端子。電源220是經由電源陰極221及電源陽極222來供給電力(例如電壓)。
陽極230是與取多面基板100對向而設的對向電極。陽極230是例如不溶性電極。
圖17是表示第2實施形態的取多面基板100及陽極230的構成之一例的圖。
如圖17所示般，在取多面基板100是含有複數的配線基板10。陽極230是含有複數的單位電極231。複數的單位電極231是對應於複數的配線基板10的各者而配置。
另外，電解電鍍是藉由未圖示的配線，在各個的配線基板10的配線大致全部被電性連接的狀態下進行。在電解電鍍之後，多餘的配線是藉由蝕刻等來斷線，配線基板10的各配線是被電性分離。
圖18是表示第2實施形態的單位電極231的構成之一例的圖。
單位電極231是具有電極部231a及絕緣部231b。
電極部231a是作為電極機能。在未設電極部231a的位置配置絕緣部231b。就圖18所示的例子而言，絕緣部231b是被配置於單位電極231之中的中心的區域，電極部231a是被配置於絕緣部231b的外周。
電鍍裝置200是藉由使用對向電極(陽極230)之電鍍，該對向電極(陽極230)是被配置為與配線基板10對向，且具有被配置為電流密度會按照面F1上的位置而變化的電極部231a，在面F1上形成按照面F1上的位置而具有不同的厚度的複數的導電連接部111a、111b。
電解電鍍的電鍍厚是如上述般，與電流密度成比例。電流密度是例如可藉由調整電極部231a與配線基板10的電鍍位置之間的距離來調整。配線基板10的晶片中心區域R11是例如主要與絕緣部231b對向。晶片中心區域R11是離電極部231a的距離比較大，因此電流密度變小。藉此，被配置於晶片中心區域R11的金屬層M2是被形成比較薄。另一方面，配線基板10的晶片外周區域R12是例如主要與電極部231a對向。晶片外周區域R12是離電極部231a的距離比較小，因此電流密度變大。藉此，被形成於晶片外周區域R12的金屬層M2是被形成比較厚。
藉由如此單位電極231的電極部231a的設計，可按照配線基板10的位置來控制電流密度。此結果，可按照配線基板10的位置來控制金屬層M2的厚度。
如以上般，若根據第2實施形態，則在電解電鍍中，藉由按照面F1上的位置來使電流密度變化，形成不同的厚度的導電連接部111a、111b。
第2實施形態的半導體裝置1是可取得與第1實施形態同樣的效果。
(第2實施形態的變形例) 圖19是表示第2實施形態的變形例的取多面基板100的構成之一例的圖。第2實施形態的變形例是使用複數的電源220的點，與第2實施形態不同。
電鍍裝置200是以按照面F1上的位置來供給不同的電力之方式電鍍，藉此在面F1上形成按照面F1上的位置而具有不同的厚度的複數的金屬層M2(導電連接部111a、111b)。
如圖19所示般，設有複數的電源220。電源220是具有電源220a、電源220b及電源220c。電源220a、220b、220c是分別具有電源陰極221a、221b、221c。電源陰極221a、221b、221c是與取多面基板100電性連接。
電源220a是例如與藉由未圖示的配線來與取多面基板100電性連接，使得形成被配置於晶片中心區域R11的導電連接部111a。電源220b是例如與藉由未圖示的配線來與取多面基板100電性連接，使得形成被配置於晶片外周區域R12的導電連接部111b。電源220c是例如與藉由未圖示的配線來與取多面基板100電性連接，使得形成周邊配線112。又，電源220a、220b、220c是分別供給對應於導電連接部111a、導電連接部111b及周邊配線112的厚度之電力。
藉由如此改變電源220a、220b、220c亦即供給電力，可按照面F1上的位置來調整電流密度。此結果，可改變各個的厚度來形成導電連接部111a、111b及周邊配線112。
又，從半導體晶片20的中心部到外周端部，使導電連接部111a、111b的厚度慢慢地變化時，可使用對應於厚度的種類的數量的電源220。
又，就第2實施形態的變形例而言，例如，亦可使用具有電極部231a會被配置於對向面的大略全面的單位電極231之陽極230。
第2實施形態的變形例的半導體裝置1是可取得與第2實施形態同樣的效果。又，亦可在第2實施形態的變形例的半導體裝置1組合第2實施形態。此情況，可使用具有圖18所示的單位電極231的陽極230，作為陽極230。
(第3實施形態) 圖20是表示第3實施形態的半導體裝置1的構成之一例的平面圖。第3實施形態是在晶片外周區域R12設置具有焊墊形狀的導電連接部111b及具有配線形狀的導電連接部111b的雙方。亦即，第3實施形態是第1實施形態與第2實施形態的組合。
就圖20所示的例子而言，阻焊劑層14是晶片外周區域R12之中，不被設在晶片中心區域R11的上下。晶片外周區域R12之中，晶片中心區域R11的左右是阻焊劑層14不被設置，絕緣層15會露出。
就圖20所示的例子而言，具有焊墊形狀的導電連接部111b是被配置於晶片中心區域R11的上下。具有配線形狀的導電連接部111b是被配置於晶片中心區域R11的左右。
具有配線形狀的導電連接部111b是如圖4B所示般，從面F1的法線方向看，被配置為離開柱狀電極16。又，具有焊墊形狀的導電連接部111b是如圖12B所示般，從面F1的法線方向看，被配置為與柱狀電極16重疊。因此，導電連接部111b的一部分是從面F1的法線方向看，被配置為與柱狀電極16重疊。
第3實施形態的半導體裝置1的其他的構成是與第1實施形態及第2實施形態的半導體裝置1的對應的構成同樣，因此省略其詳細的說明。
第3實施形態的半導體裝置1是可取得與第1實施形態及第2實施形態同樣的效果。
(第4實施形態) 圖21及圖22是表示第4實施形態的半導體裝置1的製造方法之一例的剖面圖。第4實施形態是金屬層會在1工序被形成的點，與第2實施形態不同。圖21及圖22是表示晶片中心區域R11及晶片外周區域R12的各者的剖面圖。
圖21及圖22所示的工序是在與圖5及圖6同樣的工序之後進行。
穴10h的形成後(參照圖6)，如圖21所示般，在配線層L1的銅箔17上形成作為遮罩機能的抗鍍劑層18。抗鍍劑層18是例如被形成為使得形成導電連接部111a、111b的區域開口。
其次，如圖22所示般，在穴10h內及配線層L1的銅箔17(面F1)上形成金屬層M3。另外，在形成金屬層M3之前，亦可在穴10h內(例如側壁)形成種子層。被配置於晶片外周區域R12的金屬層M3是例如使用在第2實施形態說明過的金屬層M2的形成方法，形成比被配置於晶片中心區域R11的金屬層M3更厚。金屬層M3是例如藉由電解電鍍所形成。
又，金屬層M3是被一體形成。亦即，柱狀電極16及導電連接部111a是一體的金屬層M3，柱狀電極16及導電連接部111b亦為一體的金屬層M3。
在此，電解電鍍是電鍍速度比無電解電鍍更快，因此會有容易在穴10h內形成空洞下堵塞穴10h的可能性。於是，在穴10h內的金屬層的形成未能使用無電解電鍍時，例如藉由使條件一致或放慢電鍍形成速度等來進行金屬層M3的形成。
圖22所示的工序之後，進行與圖15及圖10同樣的工序。
第4實施形態的半導體裝置1是可取得與第2實施形態同樣的效果。另外，第4實施形態是在第1實施形態也可適用。亦即，亦可在1工序形成圖4A及圖4B所示的導電連接部111a、111b。此情況，金屬層M3是例如可藉由無電解電鍍所形成，或亦可藉由電解電鍍所形成。
(第5實施形態) 第5實施形態是金屬層M2藉由無電解電鍍來形成的點，與第1實施形態不同。亦即，圖8所示的金屬層M2是藉由無電解電鍍所形成。
就第5實施形態而言，金屬層M1及金屬層M2的雙方是藉由無電解電鍍所形成。
第5實施形態的半導體裝置1是可取得與第1實施形態同樣的效果。
(第6實施形態) 圖23及圖24是表示第6實施形態的半導體裝置1的製造方法之一例的剖面圖。第6實施形態是金屬層M1藉由電解電鍍來形成，金屬層M2藉由無電解電鍍來形成的點，與第2實施形態不同。圖23及圖24是表示晶片中心區域R11及晶片外周區域R12的各者的剖面圖。
圖23及圖24所示的工序是在與圖5及圖6同樣的工序之後進行。
穴10h的形成後(參照圖6)，如圖23所示般，在配線層L1的銅箔17上形成作為遮罩機能的抗鍍劑層18，在穴10h內形成金屬層M1。另外，在形成金屬層M1之前，亦可在穴10h內(例如側壁)形成種子層。抗鍍劑層18是例如被形成為使得形成柱狀電極16的區域的穴10h開口。被配置於晶片外周區域R12的金屬層M1是具有與被配置於晶片中心區域R11的金屬層M1不同的厚度。更詳細，被配置於晶片外周區域R12的金屬層M1是比被配置於晶片中心區域R11的金屬層M1更厚。被配置於晶片外周區域R12的金屬層M1是例如使用在第2實施形態說明過的金屬層M2的形成方法來形成比被配置於晶片中心區域R11的金屬層M1更厚。金屬層M1是亦可被形成比面F1更高，亦可被形成比面F1更低。金屬層M1是例如藉由電解電鍍所形成。
其次，如圖24所示般，剝離抗鍍劑層18，在配線層L1的銅箔17上再度形成抗鍍劑層18，在配線層L1的銅箔17(面F1)上及金屬層M1上形成金屬層M2。抗鍍劑層18是例如被形成為使得形成導電連接部111a、111b的區域開口。如上述般，被配置於晶片外周區域R12的金屬層M1是比被配置於晶片中心區域R11的金屬層M1更厚。因此，即使金屬層M2對於面F1上的位置大略均等地形成，被配置於晶片外周區域R12的金屬層M1、M2也會形成比被配置於晶片中心區域R11的金屬層M1、M2更厚。金屬層M2是例如藉由無電解電鍍所形成。
又，就圖24所示的例子而言，被配置於晶片中心區域R11的金屬層M2的上面是大略平坦。這是因為金屬層M1的上面會與面F1大略一致。另一方面，被配置於晶片外周區域R12的金屬層M2的上面是不平坦。這是因為金屬層M1的上面與面F1不一致，例如越過面F1而突出。如此，亦可按照金屬層M1的上面的高度，在導電連接部111a與導電連接部111b之間，上面的形狀不同。
圖24所示的工序之後，進行與圖15及圖10同樣的工序。
第6實施形態的半導體裝置1是可取得與第2實施形態同樣的效果。又，第6實施形態的半導體裝置1是亦可組合第2實施形態的變形例。另外，第6實施形態是在第1實施形態也可適用。此情況，圖7所示的金屬層M1是例如藉由電解電鍍所形成。另外，被配置於晶片中心區域R11的金屬層M1是被形成為金屬層M1的上面會比面F1更低。圖8所示的金屬層M2是例如藉由無電解電鍍所形成。
另外，不限於上述的實施形態，例如在第1實施形態中，金屬層M1及金屬層M2的雙方亦可藉由電解電鍍來形成。又，例如在第2實施形態中，金屬層M1及金屬層M2的雙方亦可藉由電解電鍍來形成。其他，藉由各種的形態來形成導電連接部111a、111b。
說明了本發明的幾個的實施形態，但該等的實施形態是作為例子提示者，不是意圖限定發明的範圍。該等實施形態是可在其他的各種的形態被實施，可在不脫離發明的主旨的範圍進行各種的省略、置換、變更。該等實施形態或其變形是與含在發明的範圍或主旨同樣，為申請專利範圍記載的發明及其均等的範圍所包含者。
1:半導體裝置 10:配線基板 10h:穴 11:配線層 12:貫通電極 13:金屬凸塊 14:阻焊劑層 15:絕緣層 16:柱狀電極 17:銅箔 18:抗鍍劑層 20,30~33:半導體晶片 21:電極支柱 40~43,60,61:黏著層 50,51:間隔件 70:金屬材料 80:樹脂層 90:接合線 91:密封樹脂 100:取多面基板 111:導電連接部 111a:導電連接部 111b:導電連接部 112:周邊配線 151~153:絕緣層 200:電鍍裝置 210:容器 220:電源 220a,220b,220c:電源 221:電源陰極 221a,221b,221c:電源陰極 222:電源陽極 230:陽極 231:單位電極 231a:電極部 231b:絕緣部 L1~L4:配線層 M1:金屬層 M2:金屬層 F1:面 F2:面 R1:晶片區域 R11:晶片中心區域 R12:晶片外周區域
[圖1]是表示第1實施形態的半導體裝置的構成之一例的剖面圖。 [圖2]是表示第1實施形態的半導體晶片及其周邊的構成之一例的剖面圖。 [圖3]是表示第1實施形態的半導體裝置的構成之一例的平面圖。 [圖4A]是表示第1實施形態的半導體裝置的構成之一例的剖面圖。 [圖4B]是表示第1實施形態的半導體裝置的構成之一例的剖面圖。 [圖5]是表示第1實施形態的半導體裝置的製造方法之一例的剖面圖。 [圖6]是表示接續於圖5，半導體裝置的製造方法之一例的剖面圖。 [圖7]是表示接續於圖6，半導體裝置的製造方法之一例的剖面圖。 [圖8]是表示接續於圖7，半導體裝置的製造方法之一例的剖面圖。 [圖9]是表示接續於圖8，半導體裝置的製造方法之一例的剖面圖。 [圖10]是表示接續於圖9，半導體裝置的製造方法之一例的剖面圖。 [圖11]是表示第2實施形態的半導體裝置的構成之一例的平面圖。 [圖12A]是表示第2實施形態的半導體裝置的構成之一例的剖面圖。 [圖12B]是表示第2實施形態的半導體裝置的構成之一例的剖面圖。 [圖13]是表示第2實施形態的半導體裝置的製造方法之一例的剖面圖。 [圖14]是表示接續於圖13，半導體裝置的製造方法之一例的剖面圖。 [圖15]是表示接續於圖14，半導體裝置的製造方法之一例的剖面圖。 [圖16]是表示第2實施形態的電鍍裝置的構成之一例的圖。 [圖17]是表示第2實施形態的取多面基板及陽極的構成之一例的圖。 [圖18]是表示第2實施形態的單位電極的構成之一例的圖。 [圖19]是表示第2實施形態的變形例的取多面基板的構成之一例的圖。 [圖20]是表示第3實施形態的半導體裝置的構成之一例的平面圖。 [圖21]是表示第4實施形態的半導體裝置的製造方法之一例的剖面圖。 [圖22]是表示接續於圖21，半導體裝置的製造方法之一例的剖面圖。 [圖23]是表示第6實施形態的半導體裝置的製造方法之一例的剖面圖。 [圖24]是表示接續於圖23，半導體裝置的製造方法之一例的剖面圖。
10:配線基板
11:配線層
12:貫通電極
14:阻焊劑層
15:絕緣層
16:柱狀電極
20:半導體晶片
21:電極支柱
70:金屬材料
111:導電連接部
111a:導電連接部
111b:導電連接部
112:周邊配線
F1:面
F2:面
R1:晶片區域
R2:周邊區域
R11:晶片中心區域
R12:晶片外周區域

Claims (20)

  1. 一種半導體裝置，其特徵係具備： 基板，其係具有：第1面，及被設在前述第1面上的複數的導電連接部；及 半導體晶片，其係具有：與前述第1面對向的第2面，及被設在前述第2面上，與複數的前述導電連接部的各者電性連接的複數的連接凸塊， 在配置有前述半導體晶片的前述第1面上的晶片區域之中的晶片外周區域所配置的前述導電連接部係具有與在前述晶片區域之中的晶片中心區域所配置的前述導電連接部不同的厚度。
  2. 如請求項1記載的半導體裝置，其中，被配置於前述晶片外周區域的前述導電連接部係比被配置於前述晶片中心區域的前述導電連接部更厚。
  3. 如請求項1記載的半導體裝置，其中，複數的前述導電連接部之中，前述導電連接部的厚度的最大值與最小值的差為約3μm~約20μm的範圍內。
  4. 如請求項1記載的半導體裝置，其中，前述基板係更具有：被設為延伸於前述第1面的法線方向，且與複數的前述導電連接部的各者電性連接的複數的柱狀電極， 被配置於前述晶片中心區域的前述導電連接部係從前述法線方向看，被配置為與前述柱狀電極重疊， 被配置於前述晶片外周區域的前述導電連接部係從前述法線方向看，離開前述柱狀電極而配置。
  5. 如請求項1記載的半導體裝置，其中，前述基板係更具有：被設為延伸於前述第1面的法線方向，且與複數的前述導電連接部的各者電性連接的複數的柱狀電極， 被配置於前述晶片中心區域的前述導電連接部係從前述法線方向看，被配置為與前述柱狀電極重疊， 被配置於前述晶片外周區域的前述導電連接部的至少一部分係從前述法線方向看，被配置為與前述柱狀電極重疊。
  6. 如請求項1記載的半導體裝置，其中，前述基板係更具有：被設為延伸於前述第1面的法線方向，且與複數的前述導電連接部的各者電性連接的複數的柱狀電極， 前述柱狀電極及前述導電連接部係包括： 第1金屬層；及 被設在前述第1金屬層的上方，與前述第1金屬層不同的第2金屬層。
  7. 如請求項6記載的半導體裝置，其中，前述第1金屬層係被設置至比前述第1面更低的預定的高度。
  8. 如請求項6記載的半導體裝置，其中，複數的前述第1金屬層的厚度為大致相同。
  9. 如請求項6記載的半導體裝置，其中，被配置於前述晶片外周區域的前述第1金屬層係具有與被配置於前述晶片中心區域的前述第1金屬層不同的厚度。
  10. 如請求項6記載的半導體裝置，其中，在前述第1金屬層與前述第2金屬層之間，材料和雜質的濃度及種類的至少1個不同。
  11. 如請求項1記載的半導體裝置，其中，前述基板係更具有：被設為延伸於前述第1面的法線方向，且與複數的前述導電連接部的各者電性連接的複數的柱狀電極， 前述柱狀電極及前述導電連接部為一體的第3金屬層。
  12. 如請求項1記載的半導體裝置，其中，前述基板係更具有：被設在前述第1面上，且被配置於與前述晶片區域不同的區域的第1配線， 前述第1配線係具有被配置於前述晶片外周區域的前述導電連接部的厚度與被配置於前述晶片中心區域的前述導電連接部的厚度之間的厚度。
  13. 如請求項1記載的半導體裝置，其中，被配置於前述晶片外周區域的前述導電連接部的厚度與被配置於前述晶片中心區域的前述導電連接部的厚度的差係對應於與前述基板連接的時機的前述半導體晶片的彎曲。
  14. 如請求項1記載的半導體裝置，其中，前述導電連接部的厚度係從前述半導體晶片的中心部到外周端部慢慢地變化。
  15. 如請求項1記載的半導體裝置，其中，前述連接凸塊係從前述半導體晶片的中心部到外周端部，具有大致相同的厚度或大致相同的直徑。
  16. 一種半導體裝置的製造方法，其特徵係具備： 在基板的第1面形成按照前述第1面上的位置而具有不同的厚度的複數的導電連接部， 將具有第2面及被設在前述第2面的複數的連接凸塊之半導體晶片，以複數的前述連接凸塊會與複數的前述導電連接部的各者電性連接的方式設於前述基板之工序， 更具備： 在配置有前述半導體晶片的前述第1面上的晶片區域之中的晶片外周區域所配置的前述導電連接部係具有與在前述晶片區域之中的晶片中心區域所配置的前述導電連接部不同的厚度之工序。
  17. 如請求項16記載的半導體裝置的製造方法，其中，更具備： 在前述基板的前述第1面形成複數的穴， 以填埋複數的前述穴之方式形成複數的柱狀電極， 在前述第1面上的前述晶片中心區域，從前述第1面的法線方向看，形成與前述柱狀電極重疊的前述導電連接部，且在前述第1面上的前述晶片外周區域，從前述第1面的法線方向看，形成離開前述柱狀電極的前述導電連接部之工序。
  18. 如請求項16記載的半導體裝置的製造方法，其中，更具備：以電流密度會按照前述第1面上的位置而變化之方式電鍍金屬材料，藉此在前述第1面上形成按照前述第1面上的位置而具有不同的厚度的複數的前述導電連接部之工序。
  19. 如請求項18記載的半導體裝置的製造方法，其中，更具備：藉由使用對向電極之電鍍，該對向電極係被配置為與前述基板對向，且具有被配置為電流密度會按照前述第1面上的位置而變化的電極部， 在前述第1面上形成按照前述第1面上的位置而具有不同的厚度的複數的前述導電連接部之工序。
  20. 如請求項18記載的半導體裝置的製造方法，其中，更具備：以按照前述第1面上的位置來供給不同的電力之方式電鍍，藉此在前述第1面上形成按照前述第1面上的位置而具有不同的厚度的複數的前述導電連接部之工序。
TW111103075A 2021-08-17 2022-01-25 半導體裝置及其製造方法 TWI824396B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021-132880 2021-08-17
JP2021132880A JP2023027638A (ja) 2021-08-17 2021-08-17 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
TW202310257A true TW202310257A (zh) 2023-03-01
TWI824396B TWI824396B (zh) 2023-12-01

Family

ID=85228431

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111103075A TWI824396B (zh) 2021-08-17 2022-01-25 半導體裝置及其製造方法

Country Status (4)

Country Link
US (1) US20230058480A1 (zh)
JP (1) JP2023027638A (zh)
CN (1) CN115939079A (zh)
TW (1) TWI824396B (zh)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101096039B1 (ko) * 2009-11-09 2011-12-19 주식회사 하이닉스반도체 인쇄회로기판 및 이를 이용한 반도체 패키지
US10923447B2 (en) * 2017-05-23 2021-02-16 Micron Technology, Inc. Semiconductor device assembly with die support structures

Also Published As

Publication number Publication date
CN115939079A (zh) 2023-04-07
JP2023027638A (ja) 2023-03-02
TWI824396B (zh) 2023-12-01
US20230058480A1 (en) 2023-02-23

Similar Documents

Publication Publication Date Title
TWI479971B (zh) 佈線板，其製造方法及具有佈線板之半導體裝置
TWI487450B (zh) 佈線基板及其製造方法
TWI508196B (zh) 具有內建加強層之凹穴基板之製造方法
JP5598787B2 (ja) 積層型半導体装置の製造方法
US9536864B2 (en) Package structure and its fabrication method
TWI523591B (zh) 佈線基板之製造方法
JP6027966B2 (ja) エリアアレイユニットコネクタを備えるスタック可能モールド超小型電子パッケージ
EP2261974B1 (en) Electronic component used for wiring and method for manufacturing the same
JP2013030593A (ja) 半導体装置、該半導体装置を垂直に積層した半導体モジュール構造及びその製造方法
TWI402954B (zh) Assembly board and semiconductor module
US20100032196A1 (en) Multilayer wiring board, semiconductor package and method of manufacturing the same
TW201220446A (en) Package structure of embedded semiconductor component and manufacturing method thereof
US9941232B2 (en) Electronic component device
JP2011071315A (ja) 配線基板及び配線基板の製造方法
JP2016152260A (ja) 電子装置
CN110729254B (zh) 封装体的接着结构及其制造方法
US20080174005A1 (en) Electronic device and method for manufacturing electronic device
JP4963879B2 (ja) 半導体装置および半導体装置の製造方法
JP5404513B2 (ja) 半導体装置の製造方法
US10804190B2 (en) Multi-chip module and method for manufacturing same
JP6643213B2 (ja) リードフレーム及びその製造方法と電子部品装置
US20140167276A1 (en) Substrate for semiconductor package, semiconductor package using the substrate, and method of manufacturing the semiconductor package
US11869844B2 (en) Semiconductor device
JP4736762B2 (ja) Ｂｇａ型半導体装置及びその製造方法
TW202310257A (zh) 半導體裝置及其製造方法