TW202245204A - 用於模組內之電磁干擾(emi)屏蔽之導電通孔或溝槽之應用 - Google Patents
用於模組內之電磁干擾(emi)屏蔽之導電通孔或溝槽之應用 Download PDFInfo
- Publication number
- TW202245204A TW202245204A TW111110615A TW111110615A TW202245204A TW 202245204 A TW202245204 A TW 202245204A TW 111110615 A TW111110615 A TW 111110615A TW 111110615 A TW111110615 A TW 111110615A TW 202245204 A TW202245204 A TW 202245204A
- Authority
- TW
- Taiwan
- Prior art keywords
- conductive
- substrate
- ground plane
- conductive layer
- molding compound
- Prior art date
Links
- 150000001875 compounds Chemical class 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 238000000465 moulding Methods 0.000 claims description 47
- 238000000034 method Methods 0.000 claims description 45
- 238000000151 deposition Methods 0.000 claims description 20
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 7
- 229910052709 silver Inorganic materials 0.000 claims description 7
- 239000004332 silver Substances 0.000 claims description 7
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 238000009713 electroplating Methods 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- 239000003822 epoxy resin Substances 0.000 claims 1
- 229920000647 polyepoxide Polymers 0.000 claims 1
- 230000008569 process Effects 0.000 description 11
- 239000004020 conductor Substances 0.000 description 10
- 239000004593 Epoxy Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000002679 ablation Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000001465 metallisation Methods 0.000 description 5
- 239000003973 paint Substances 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 4
- 238000001721 transfer moulding Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005670 electromagnetic radiation Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 238000002207 thermal evaporation Methods 0.000 description 2
- 229940126062 Compound A Drugs 0.000 description 1
- NLDMNSXOCDLTTB-UHFFFAOYSA-N Heterophylliin A Natural products O1C2COC(=O)C3=CC(O)=C(O)C(O)=C3C3=C(O)C(O)=C(O)C=C3C(=O)OC2C(OC(=O)C=2C=C(O)C(O)=C(O)C=2)C(O)C1OC(=O)C1=CC(O)=C(O)C(O)=C1 NLDMNSXOCDLTTB-UHFFFAOYSA-N 0.000 description 1
- 238000010420 art technique Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 238000012776 robust process Methods 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 239000011265 semifinished product Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/52—Means for reducing coupling between antennas; Means for reducing coupling between an antenna and another structure
- H01Q1/526—Electromagnetic shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Electromagnetism (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
本發明揭示一種封裝半導體模組,其包括:一基板,其具有一接地平面;一電子裝置,其安裝於該基板之一表面上;一接合墊,其安置於該基板之該表面上且電連接至該接地平面;模塑化合物,其覆蓋該電子裝置;一導電柱,其安置於該電子裝置之一側上,該導電柱自該接合墊延伸且至少部分穿過該模塑化合物;及一導電層,其安置於該模塑化合物上且電耦合至該導電柱及該接地平面,該導電柱、該導電層及該接地平面一起形成整合電磁干擾屏蔽,該導電柱在垂直於由該基板之該表面界定之一平面之一方向上自該接合墊延伸至該導電層。
Description
本發明係針對半導體裝置封裝,且更特定言之,本發明係針對用於半導體裝置之電磁及/或射頻干擾屏蔽。
在射頻(RF)通信系統中普遍希望RF裝置與其他RF裝置產生之電磁(射頻)干擾(EMI)隔離以維持適當裝置效能。類似地,RF裝置通常應與自環境接收或傳輸至環境之電磁干擾隔離。
將RF裝置與此電磁干擾隔離之傳統方法係用通常稱為一「罐」之一接地金屬外殼覆蓋RF裝置。然而,此解決方案成本高昂且缺乏設計靈活性。另外,金屬會顯著增加一印刷電路板上之裝置佔據面積大小,且亦增加印刷電路板之重量。
根據一個態樣,提供一種具有一整合電磁干擾之封裝半導體模組。該封裝半導體模組包括:一基板,其具有一接地平面;一電子裝置,其安裝於該基板之一表面上;一接合墊,其安置於該基板之該表面上且電連接至該接地平面;模塑化合物,其覆蓋該電子裝置;一導電柱,其安置於該電子裝置之一側上,該導電柱自該接合墊延伸且至少部分穿過該模塑化合物;及一導電層,其安置於該模塑化合物上且電耦合至該導電柱及該接地平面,該導電柱、該導電層及該接地平面一起形成整合電磁干擾屏蔽,該導電柱在垂直於由該基板之該表面界定之一平面之一方向上自該接合墊延伸至該導電層。
在一些實施例中,該導電層安置於該模塑化合物之一頂部及側上。
在一些實施例中,該導電層在該模塑化合物之一側上實體接觸該接地平面。
在一些實施例中,該導電層在該模塑化合物之該頂部上實體接觸該導電柱。
在一些實施例中,該導電層包含銀填充之環氧樹脂。
在一些實施例中,該電子裝置係一RF裝置。
在一些實施例中,該封裝半導體模組進一步包括安置於該基板之該表面上之複數個電子裝置及安置於該複數個電子裝置之兩者之間的複數個導電柱。
在一些實施例中,該封裝半導體模組進一步包括安裝於該基板之該表面上之複數個電子裝置及僅安置於該複數個電子裝置之兩者之間的一單一導電柱。
在一些實施例中,該封裝半導體模組進一步包括環繞該電子裝置之複數個導電柱。
在一些實施例中,該封裝半導體模組進一步包括安置於該基板內且提供該接合墊與該接地平面之間的電連接之一導電通孔。
在一些實施例中,該導電通孔安置於該導電柱正下方。
在一些實施例中,該導電通孔自該導電柱橫向移位。
根據另一態樣,提供一種形成具有一整合電磁干擾屏蔽之一封裝半導體模組之方法。該方法包括:提供具有一接地平面之一基板;將一電子裝置安裝於該基板之一表面上;使一接合墊形成於該基板之該表面上且電連接至該接地平面;使模塑化合物沈積於該電子裝置上;在該電子裝置之一側上之該模塑化合物中燒蝕一通孔開口,燒蝕該通孔開口以暴露該接合墊之一上側;使一導電柱形成於該通孔開口內且與該接合墊電接觸;及使一導電層沈積於該模塑化合物上且與該導電柱及該接地平面實體接觸,該導電柱、該導電層及該接地平面一起形成該整合電磁干擾屏蔽,該導電柱在垂直於由該基板之該表面界定之一平面之一方向上自該接合墊延伸至該導電層。
在一些實施例中,使該導電柱形成於該通孔開口內包含將一焊膏沈積於該通孔開口內。
在一些實施例中,使該導電柱形成於該通孔開口內包含藉由電鍍形成該導電柱。
在一些實施例中,使該導電柱形成於該通孔開口內包含藉由物理氣相沈積形成該導電柱。
在一些實施例中,該方法進一步包括將複數個電子裝置安裝於該基板之該表面上。
在一些實施例中,形成該導電柱包含使複數個導電柱形成於該複數個電子裝置之兩者之間。
在一些實施例中,使該導電層沈積於該模塑化合物上包含使該導電層沈積於該模塑化合物之一頂部上及側上。
在一些實施例中,使該導電層沈積於該模塑化合物上包含使與該接地平面實體接觸之該導電層沈積於該模塑化合物之一側上。
某些實施例之以下描述呈現特定實施例之各種描述。然而,本文中所描述之創新可依多種不同方式體現,例如申請專利範圍所界定及涵蓋。在本說明書中,參考圖式,其中相同元件符號可指示相同或功能類似元件。應理解,圖式中所繪示之元件未必按比例繪製。再者,應理解,某些實施例可包含比一圖式中所繪示之元件多之元件及/或一圖式中所繪示之元件之一子集。此外,一些實施例可併入來自兩個或更多個圖式之特徵之任何適合組合。
本文中所揭示之態樣及實施例係針對一種半導體裝置模組及其製造方法,該等方法將一電磁干擾(EMI)屏蔽整合至裝置模組中。在一個實施例中,一或多個導電柱定位於該模組內之一或多個裝置之一或多個側上且耦合至該一或多個裝置上方及下方之導電層,藉此形成圍繞該一或多個裝置之一EMI屏蔽。該EMI屏蔽減少或消除歸因於自該模組中之一或多個其他裝置或環境接收之EMI之該模組內之該一或多個裝置之效能衰減。
一個態樣係針對一種具有一整合電磁干擾屏蔽之封裝半導體模組。在一個實施例中,該封裝半導體模組包括:一基板,其具有一接地平面;複數個電子裝置,其等安裝於該基板之一表面上;至少一個導電柱,其安置於該等電子裝置之至少一者之至少一個側上且電耦合至該接地平面;模塑化合物,其覆蓋該等電子裝置且至少部分覆蓋該至少一個導電柱;及一導電層,其安置於該模塑化合物之一頂面上且電耦合至該至少一個導電柱,其中該至少一個導電柱、該導電層及該接地平面一起包括該整合電磁干擾屏蔽。
在一個實例中,該導電層包括銀填充之環氧樹脂。該至少一個導電柱可由各種導電材料(諸如金、銅、焊料、導電性塗料、摻雜多晶矽或銀填充之環氧樹脂)製成。該至少一個導電柱可安置於該半導體模組中之該複數個電子裝置之兩者之間。在一個實例中,該複數個電子裝置係射頻(RF)裝置。
另一態樣係針對一種製造具有一整合電磁干擾屏蔽之一模組之方法。根據一個實施例,該方法包括:將複數個電子裝置連接至包含一接地平面之一基板;在該基板上提供電連接至該接地平面之接合墊;執行一模塑程序以將該複數個電子裝置囊封於模塑化合物中;在該模塑化合物中形成一或多個導電柱,其等位於該複數個電子裝置之相鄰者之間且與該等接合墊電連接;及將一導電層安置於該模塑化合物之一表面上,該導電層電連接至該一或多個導電柱。在一個實例中,該方法進一步包括在將該導電層安置於該模塑化合物之該表面上之前燒蝕該模塑化合物之該表面以形成該一或多個導電柱之通孔。該一或多個導電柱可藉由焊膏之絲網印刷、電鍍、化學氣相沈積、物理氣相沈積(蒸鍍沈積或濺鍍),藉由沈積導電性塗料或藉由技術中已知之沈積導電材料之其他方法來形成於通孔中。在一些實例中,將該導電層安置於該模塑化合物之該表面上包含在該模塑化合物之頂面及側面上塗覆一層銀填充之環氧樹脂或導電塗料。
在諸多現代應用(包含蜂巢式電話手機、個人數位助理(PDA)、媒體播放器及使用射頻(RF)組件之其他可攜式裝置)中,成品之大小(長度、寬度及厚度)及重量通常可為重要設計參數。例如,尤其針對蜂巢式電話手機,對在一給定外觀尺寸內提供更多功能及特徵之裝置之需求不斷增加。因此,用於此等裝置中之個別組件之大小及重量亦可為重要的。如上文所討論,用於針對RF裝置提供電磁干擾屏蔽之習知方法涉及在待屏蔽之個別RF裝置上方放置一接地金屬罐,其增加設計之大小、重量及成本且因此在諸多例項中可為非所要的。
本文中所揭示之態樣及實施例係針對用於提供在封裝程序期間整合至個別模組中且最少地增加模組之大小及/或重量之一干擾屏蔽之方法及設備。如本文中所使用,術語「EMI屏蔽」用於指代電磁干擾及射頻干擾屏蔽兩者。用於針對一電子裝置模組中之裝置驗證EMI保護之方法及結構之態樣及實施例可提供高設計靈活性以及製造EMI屏蔽之一較容易且較便宜方法。另外,根據本發明之態樣之一整合「柵柱」屏蔽提供一種用於達成模組間/模組內隔離及低封裝輪廓之方式,其無法藉由習知既有技術達成。如下文將討論,一柵柱籠可使用安置於一模組中之一或多個電子裝置之間或周圍之導電柱形成,以針對各種封裝及處理條件提供一穩固且實用之EMI屏蔽。
參考圖1,繪示封裝併入一整合EMI屏蔽之一電子裝置或模組之一方法之一個實例。下文繼續參考圖1討論方法之態樣及實施例。
一第一步驟100包含製備一基板以併入至一電子模組中。此步驟100可包含在基板上形成鍍金屬,其可用於使電子模組之各種組件互連且其之至少一些可變成整合EMI屏蔽之部分,如下文將進一步討論。在步驟102中,可根據熟習技術者已知之方法及技術來組裝以電子模組。此步驟102可包含諸如將複數個晶粒安裝至基板、形成任何必要內部或外部連接或連接點(包含沈積鍍金屬層及/或介電層)等等之動作。因此,應瞭解,儘管模組組裝經繪示為圖1中之一單一步驟102,但其可包括可同時、不同時及/或在不同位置中執行之若干步驟。此外,應瞭解,步驟100可被視為步驟102之部分。
圖2中繪示此一模組之一實例。模組200包括安裝至一基板204之至少兩個晶粒202。晶粒202之一些實例包含(但不限於)功率放大器、低雜訊放大器、收發器、線性裝置、濾波器及可需要或受益於EMI屏蔽之其他裝置。如上文所討論,RF裝置通常需要EMI屏蔽,且因此,晶粒202之至少一者可為一RF裝置且模組200可為一RF模組;然而,應瞭解,本發明不限於此,且晶粒202可包括任何類型之數位或類比裝置或組件。在一個實例中,晶粒202使用連接至接合墊208之接線206安裝至基板204,如圖2中所繪示。替代地,晶粒202可使用覆晶接合方法或熟習技術者已知之任何其他適合技術安裝至基板204。
根據一個實施例,一整合EMI屏蔽藉由在封裝期間使一或多個導電柱216形成於晶粒202之一或多者之一或多個側上(例如,相鄰晶粒202之間)來併入至模組200中。複數個此等導電柱216可圍繞晶粒202放置於基板204上且連接至封裝中之一接地平面212 (如下文進一步討論)以提供整合EMI屏蔽。為在一模塑模組中形成一整合屏蔽,一製造困難在於找到一方式來將基板中之接地平面212連接至頂部導電屏蔽層。使用導電柱連接器216來形成一整合屏蔽之方法之實施例提供一穩固製程以解決此困難,如下文進一步討論。
再次參考圖1,如上文所討論,步驟100可包含在基板204上形成將變成整合EMI屏蔽之鍍金屬。參考圖3,此鍍金屬可包含接合墊210、一接地平面212及將接合墊連接至接地平面212之通孔214。導電柱216可接著形成於接合墊210上(步驟108),如下文進一步討論。應瞭解,儘管在圖3中所繪示之實例中,針對導電柱216提供一個離散接合墊210及相關聯通孔214,但本文中所揭示之態樣及實施例不限於此且預期諸多其他組態。例如,如圖4中所繪示,個別接合墊210可用可至少部分環繞(若干)晶粒202之一鍍金屬軌道或環218替換。在此實例中,一或多個通孔214可提供於沿軌道218之點處以耦合軌道,及因此導電柱216至接地平面212。此外,在一個實例中,軌道218在兩個或更多個導電柱216之間可為連續的,且因此,各導電柱216無需具有一個別相關聯通孔214且通孔214可自導電柱橫向偏移。
根據一個實施例,形成一整合EMI屏蔽包含一轉移模塑程序(步驟104)以將(若干)晶粒202囊封於模塑化合物220中。在轉移模塑程序期間,基板204放置於一下模套中,一上模套降低至下模套上以密封圍繞裝置之一空腔,且模塑化合物220流入空腔中以囊封基板上之(若干)晶粒202。熟習技術者熟知轉移模塑程序。
仍參考圖1及圖3,在轉移模塑程序(步驟104)之後,一燒蝕程序(步驟106)可用於形成穿過模塑化合物220之導電柱216之通孔222。燒蝕程序可包含(例如)一雷射燒蝕程序、一各向異性蝕刻程序、利用機械鑽頭之一鑽孔程序、微燒蝕(噴砂)或形成穿過技術中已知之模塑化合物之一通孔。燒蝕程序暴露其上將形成導電柱216之接合墊210之上部。接合墊210可在燒蝕程序期間充當蝕刻停止層或燒蝕停止層。通孔222可為約100 µm寬以促進稍後用導電材料填充。
在通孔222形成之後,導電柱216形成於通孔222內且與接合墊210及接地平面212電接觸(步驟108)。導電柱216可藉由(例如)焊膏之絲網印刷、電鍍、化學氣相沈積、物理氣相沈積(蒸鍍沈積或濺鍍),藉由沈積導電性塗料或藉由技術中已知之沈積導電材料之其他方法來形成。導電柱216可由銅、金、銀、焊料、摻雜多晶矽或任何其他適合導電材料形成或包含銅、金、銀、焊料、摻雜多晶矽或任何其他適合導電材料。導電柱216可自接合墊210延伸至模塑化合物220之上表面及通孔222之上端,但在其他實施例中,可具有安置於模塑化合物220之上表面及通孔222之上端下方之上端。
在導電柱216形成之後,一薄導電塗層或層224可形成於模塑化合物220之頂部上(步驟110)以接觸導電柱216之暴露頂部。導電層224可使用熟習技術者已知之各種技術之任何者(諸如)藉由印刷、沈積、濺鍍等等來沈積於模塑化合物220之頂部上。在一個實例中,導電層224包括一金屬填充之環氧樹脂(諸如一銀填充之環氧樹脂)或噴塗於模塑化合物220之頂部上之一金屬塗料層(如美國專利第10,163,814號中所揭示,該案以引用方式併入本文中)。導電層224接觸導電柱216之暴露頂部且因此電連接暴露導電柱216。導電層224亦可覆蓋模塑化合物210之側且向下延伸至接地平面212之暴露位置或先前形成於模塑化合物210之側上(例如,步驟100中)之一導電材料層226且與接地平面212電連接。導電柱216可因此自下端透過接合墊210及通孔及自頂端透過導電層224及(視情況)導電材料層226電連接至接地平面212。
如上文所討論,在一個實例中,模組200包含沿基板204之一底面安置(如圖3中所展示)且藉由通孔214連接至導電柱216之一接地平面212。透過導電柱216及導電層224之頂部之間的接觸,一電連接形成於導電層與接地平面212之間,因此完成模組200中之一EMI屏蔽。導電柱216在基板204中之接地平面212與頂部導電屏蔽層224之間提供一撓性(因為其等可位於基板上之任何適合位置)且完全整合連接。因此,(若干)晶粒202之一或多者可實質上圍封於由導電層224、導電柱216 (及其等相關聯鍍金屬,諸如通孔214及接合墊210)及接地平面212形成之一接地EMI屏蔽中。不同於習知EMI屏蔽解決方案之龐大金屬罐,根據本發明之實施例之此整合EMI屏蔽可增加模組200之最小大小及重量。
導電柱216及相關聯接合墊210及通孔214之位置可經選擇以最小化用於最小化相關聯製造成本之導電柱216之數目,同時在一模組中之裝置或晶粒202之間提供足夠的模組內EMI保護以符合規範。例如,如圖5中所繪示,可發射相對大量EMI之一高功率裝置或晶粒202A (例如一功率放大器)以及可對EMI敏感之一第二裝置或晶粒202B (例如一低雜訊放大器)可存在於相同模組200中。因此,可期望在高功率裝置或晶粒202A與EMI敏感裝置或晶粒202B之間形成一或多個導電柱216。在一些例項中,導電柱216可依期望自高功率裝置或晶粒202A發射之電磁輻射之一波長之一分率彼此間隔。在其他實施例中,導電柱216或甚至一單一導電柱216可提供自高功率裝置或晶粒202A發射至接地平面212之足量能量傳導使得多個導電柱216或依所關注電磁輻射之波長之一分率間隔之導電柱216對於達成一所要EMI衰減而言可能不是必需的。針對尤其EMI敏感裝置或晶粒202C,可期望在裝置或晶粒202C之各側上提供導電柱216以防止模組內EMI及來自模組200外部源之EMI兩者。針對定位接近模組200之一邊緣或隅角之高功率或敏感裝置或晶粒202D,可期望僅在面向模組內之其他裝置或晶粒之裝置或晶粒202D之側上提供導電柱。
總言之,一有效、低成本且穩固之整合EMI屏蔽可僅使用通常早已存在於模組基板中之接地平面、沈積於模塑化合物之頂部上之導電材料之一薄層及用於將導電層連接至接地平面之本文中所討論之複數個導電柱來提供於任何轉移模塑模組中,藉此形成模組中之部分或全部裝置之一完整屏蔽。導電柱可放置於封裝中之任何位置,具有選用冗餘連接以確保與導電層224之接觸滿足所有電性要求,以允許可易於修改以適應不同模組佈局及裝置之一非常靈活之EMI屏蔽設計。類似地,如上文參考圖4所討論,將接線墊210 (或軌道218)連接至接地平面之通孔214無需與各墊或接地平面上之特定位置重合,以允許墊210及通孔214在模組中之靈活放置。提供一足夠EMI屏蔽所需之導電柱之數目取決於待屏蔽之裝置之操作頻率及所要屏蔽之位準。例如,密度(直接相鄰之導電柱216在任何給定方向上之間隔)可隨信號頻率增加而增加。在一個實例中,可使用約λ/20 (其中λ係待屏蔽之信號之波長)之一間隔。應瞭解,柱間隔不必均勻,只要維持在一給定頻率達成所要屏蔽之最小間隔即可。本文中所討論之導電柱可用於提供高度靈活且對模組增加最小成本、重量及/或大小之一完全整合EMI屏蔽。導電柱可使用低成本、穩固且無需取得任何額外或專用組裝設備之傳統處理技術來處理。
可在各種電子裝置中實施本發明之態樣。電子裝置之實例可包含(但不限於)消費性電子產品、諸如封裝射頻模組之消費性電子產品之部件、上行鏈路無線通信裝置、無線通信基礎設施、電子測試設備等等。電子裝置之實例可包含(但不限於)諸如一智慧型電話之一行動電話、諸如一智慧型手錶或一耳機之一穿戴式運算裝置、一電話、一電視、一電腦監視器、一電腦、一數據機、一手持電腦、一膝上型電腦、一平板電腦、一微波爐、一冰箱、諸如一汽車電子系統之一車載電子系統、一立體聲系統、一數位音樂播放器、一收音機、諸如一數位攝影機之一攝影機、一可攜式記憶體晶片、一洗衣機、一乾燥機、一洗衣機/乾燥機、一影印機、一傳真機、一掃描器、一多功能周邊裝置、一手錶、一時鐘等等。此外,電子裝置可包含半成品。
除非內文另有明確要求,否則貫穿描述及申請專利範圍,字詞「包括(comprise/comprising)」、「包含(include/including)」及其類似者應解釋為包含意義,而非解釋為排他性或詳盡性意義;即,應解釋成「包含,但不限於」之意義。如本文中通常所使用,字詞「耦合」指代可直接連接或藉由一或多個中間元件連接之兩個或更多個元件。同樣地,如本文中通常所使用,字詞「連接」指代可直接連接或藉由一或多個中間元件連接之兩個或更多個元件。另外,字詞「本文中」、「上文」、「下文」及類似含義之字詞在用於本申請案中時應指代本申請案之整體而非本申請案之任何特定部分。在背景允許之情況下,上文[實施方式]中所使用單數或複數字詞亦可分別包含複數或單數。字詞「或」涉及兩個或兩個以上項目之一清單,該字詞涵蓋字詞之所有以下解釋:清單中之任何項目、清單中之所有項目及清單中之項目之任何組合。
再者,除非另有具體規定或如所使用之內文內之其他理解,否則本文中所使用之條件性語言,尤其諸如「可」、「可能」、「可以」、「會」、「例如」、「舉例而言」、「諸如」及其類似者通常意欲表達某些實施例包含(但其他實施例不包含)某些特徵、元件及/或狀態。因此,此條件性語言通常並非意欲暗示特徵、元件及/或狀態係依一或多項實施例所需之任何方式,或一或多項實施例一定包含用於在具有或不具有作者輸入或提示之情況下決定在任何特定實施例中是否包含或執行此等特徵、元件及/或狀態之邏輯。
儘管已描述某些實施例,但此等實施例僅藉由實例方式呈現且並非意欲限制本發明之範疇。事實上,可依各種其他形式體現本文中所述之新穎設備、方法及系統;此外,在不背離本發明之精神之情況下,可對本文中所描述之方法及系統之形式作出各種省略、置換及變更。舉例而言,儘管區塊以一給定配置呈現,但替代實施例可用不同組件及/或電路拓撲執行類似功能,且一些區塊可被刪除、移動、添加、細分、組合及/或修改。可依各種不同方式實施此等區塊之各者。上述各種實施例之元件及動作之任何組合可經組合以提供進一步實施例。隨附申請專利範圍及其等效物意欲涵蓋如將落於本發明之範疇及精神內之此等形式或修改。
100:步驟
102:步驟
104:步驟
106:步驟
108:步驟
110:步驟
200:模組
202:晶粒
202A:高功率裝置或晶粒
202B:EMI敏感裝置或晶粒
202C:EMI敏感裝置或晶粒
202D:高功率或敏感裝置或晶粒
204:基板
206:接線
208:接合墊
210:接合墊
212:接地平面
214:通孔
216:導電柱
218:軌道
220:模塑化合物
222:通孔
224:導電層
226:導電材料層
現參考附圖藉由非限制性實例方式描述本發明之實施例。
圖1係繪示作為一封裝程序之部分之提供一整合EMI屏蔽之一方法之一個實例的一流程圖;
圖2係包括一基板及安裝至其之一或多個晶粒之一電子模組之一個實例之一圖式;
圖3係併入一整合EMI屏蔽之一裝置封裝之一個實例之一圖式;
圖4係包含一連續接線軌跡之一裝置封裝之一部分之一平面圖;及
圖5係繪示裝置或晶粒及導電柱之相對放置之一電子模組之一實例的一平面圖。
202:晶粒
204:基板
206:接線
208:接合墊
210:接合墊
212:接地平面
214:通孔
216:導電柱
220:模塑化合物
222:通孔
224:導電層
226:導電材料層
Claims (20)
- 一種具有一整合電磁干擾屏蔽之封裝半導體模組,其包括: 一基板,其具有一接地平面; 一電子裝置,其安裝於該基板之一表面上; 一接合墊,其安置於該基板之該表面上且電連接至該接地平面; 模塑化合物,其覆蓋該電子裝置; 一導電柱,其安置於該電子裝置之一側上,該導電柱自該接合墊延伸且至少部分穿過該模塑化合物;及 一導電層,其安置於該模塑化合物上且電耦合至該導電柱及該接地平面,該導電柱、該導電層及該接地平面一起形成該整合電磁干擾屏蔽,該導電柱在垂直於由該基板之該表面界定之一平面之一方向上自該接合墊延伸至該導電層。
- 如請求項1之封裝半導體模組,其中該導電層安置於該模塑化合物之一頂部及側上。
- 如請求項1之封裝半導體模組,其中該導電層在該模塑化合物之一側上實體接觸該接地平面。
- 如請求項1之封裝半導體模組,其中該導電層在該模塑化合物之該頂部上實體接觸該導電柱。
- 如請求項1之封裝半導體模組,其中該導電層包含銀填充之環氧樹脂。
- 如請求項1之封裝半導體模組,其中該電子裝置係一RF裝置。
- 如請求項1之封裝半導體模組,其進一步包括安裝於該基板之該表面上之複數個電子裝置及安置於該複數個電子裝置之兩者之間的複數個導電柱。
- 如請求項1之封裝半導體模組,其進一步包括安裝於該基板之該表面上之複數個電子裝置及僅安置於該複數個電子裝置之兩者之間的一單一導電柱。
- 如請求項1之封裝半導體模組,其進一步包括環繞該電子裝置之複數個導電柱。
- 如請求項1之封裝半導體模組,其進一步包括安置於該基板內且提供該接合墊與該接地平面之間的電連接之一導電通孔。
- 如請求項10之封裝半導體模組,其中該導電通孔安置於該導電柱正下方。
- 如請求項10之封裝半導體模組,其中該導電通孔自該導電柱橫向移位。
- 一種形成具有一整合電磁干擾屏蔽之一封裝半導體模組之方法,該方法包括: 提供具有一接地平面之一基板; 將一電子裝置安裝於該基板之一表面上; 使一接合墊形成於該基板之該表面上且電連接至該接地平面; 使模塑化合物沈積於該電子裝置上; 在該電子裝置之一側上之該模塑化合物中燒蝕一通孔開口,燒蝕該通孔開口以暴露該接合墊之一上側; 使一導電柱形成於該通孔開口內且與該接合墊電接觸;及 使一導電層沈積於該模塑化合物上且與該導電柱及該接地平面實體接觸,該導電柱、該導電層及該接地平面一起形成該整合電磁干擾屏蔽,該導電柱在垂直於由該基板之該表面界定之一平面之一方向上自該接合墊延伸至該導電層。
- 如請求項13之方法,其中使該導電柱形成於該通孔開口內包含將一焊膏沈積於該通孔開口內。
- 如請求項13之方法,其中使該導電柱形成於該通孔開口內包含藉由電鍍形成該導電柱。
- 如請求項13之方法,其中使該導電柱形成於該通孔開口內包含藉由物理氣相沈積形成該導電柱。
- 如請求項13之方法,其進一步包括將複數個電子裝置安裝於該基板之該表面上。
- 如請求項17之方法,其中形成該導電柱包含使複數個導電柱形成於該複數個電子裝置之兩者之間。
- 如請求項13之方法,其中使該導電層沈積於該模塑化合物上包含使該導電層沈積於該模塑化合物之一頂部上及側上。
- 如請求項19之方法,其中使該導電層沈積於該模塑化合物上包含使與該接地平面實體接觸之該導電層沈積於該模塑化合物之一側上。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US202163164763P | 2021-03-23 | 2021-03-23 | |
US63/164,763 | 2021-03-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW202245204A true TW202245204A (zh) | 2022-11-16 |
Family
ID=81344869
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW111110615A TW202245204A (zh) | 2021-03-23 | 2022-03-22 | 用於模組內之電磁干擾(emi)屏蔽之導電通孔或溝槽之應用 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20220310530A1 (zh) |
GB (1) | GB2606841A (zh) |
TW (1) | TW202245204A (zh) |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7799602B2 (en) * | 2008-12-10 | 2010-09-21 | Stats Chippac, Ltd. | Semiconductor device and method of forming a shielding layer over a semiconductor die after forming a build-up interconnect structure |
US9129954B2 (en) * | 2013-03-07 | 2015-09-08 | Advanced Semiconductor Engineering, Inc. | Semiconductor package including antenna layer and manufacturing method thereof |
US20180374798A1 (en) * | 2017-06-24 | 2018-12-27 | Amkor Technology, Inc. | Semiconductor device having emi shielding structure and related methods |
-
2022
- 2022-03-18 GB GB2203827.7A patent/GB2606841A/en active Pending
- 2022-03-22 TW TW111110615A patent/TW202245204A/zh unknown
- 2022-03-22 US US17/655,801 patent/US20220310530A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
US20220310530A1 (en) | 2022-09-29 |
GB2606841A (en) | 2022-11-23 |
GB202203827D0 (en) | 2022-05-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11646290B2 (en) | Shielded electronic component package | |
US7514774B2 (en) | Stacked multi-chip package with EMI shielding | |
US20140124907A1 (en) | Semiconductor packages | |
US7345365B2 (en) | Electronic component with die and passive device | |
KR101657622B1 (ko) | 전자기 간섭 인클로저를 갖는 무선 주파수 멀티-칩 집적 회로 패키지 및 패키지를 제조하기 위한 방법 | |
KR100692441B1 (ko) | 반도체 장치 및 반도체 장치의 제조 방법 | |
US6218731B1 (en) | Tiny ball grid array package | |
US7851894B1 (en) | System and method for shielding of package on package (PoP) assemblies | |
US8008753B1 (en) | System and method to reduce shorting of radio frequency (RF) shielding | |
KR100782774B1 (ko) | Sip 모듈 | |
US7566962B2 (en) | Semiconductor package structure and method for manufacturing the same | |
CN108701681B (zh) | 屏蔽emi的集成电路封装和及其制造方法 | |
US20080315396A1 (en) | Mold compound circuit structure for enhanced electrical and thermal performance | |
US20140124906A1 (en) | Semiconductor package and method of manufacturing the same | |
US20060214278A1 (en) | Shield and semiconductor die assembly | |
US7842546B2 (en) | Integrated circuit module and method of packaging same | |
CN111933636A (zh) | 一种半导体封装结构以及封装方法 | |
TWI484616B (zh) | 具電磁干擾屏蔽之封裝模組 | |
JP2004128288A (ja) | 半導体装置および電子装置 | |
CN108695299B (zh) | 电子封装件及其承载结构与制法 | |
TW202245204A (zh) | 用於模組內之電磁干擾(emi)屏蔽之導電通孔或溝槽之應用 | |
KR101741648B1 (ko) | 전자파 차폐 수단을 갖는 반도체 패키지 및 그 제조 방법 | |
US20180240738A1 (en) | Electronic package and fabrication method thereof | |
US20230326873A1 (en) | Semiconductor package and method of fabricating the same | |
WO2022236787A1 (zh) | 芯片封装结构及封装系统 |