WO2022236787A1 - 芯片封装结构及封装系统 - Google Patents

芯片封装结构及封装系统 Download PDF

Info

Publication number
WO2022236787A1
WO2022236787A1 PCT/CN2021/093696 CN2021093696W WO2022236787A1 WO 2022236787 A1 WO2022236787 A1 WO 2022236787A1 CN 2021093696 W CN2021093696 W CN 2021093696W WO 2022236787 A1 WO2022236787 A1 WO 2022236787A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
signal
packaging
soldering
points
Prior art date
Application number
PCT/CN2021/093696
Other languages
English (en)
French (fr)
Inventor
李永胜
史坡
杨正得
杨威
曾川权
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202180005963.9A priority Critical patent/CN115633543A/zh
Priority to PCT/CN2021/093696 priority patent/WO2022236787A1/zh
Publication of WO2022236787A1 publication Critical patent/WO2022236787A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits

Definitions

  • the present application relates to the technical field of chip packaging, in particular to a chip packaging structure and packaging system.
  • SiP system in package, system-in-package
  • SiP integrates electronic devices such as passive devices or active devices, chips (Die), and multilayer substrates, uses miniaturized self-shielding technologies such as sputtering protective coatings, and uses BGA (ball grid array, ball grid array)
  • BGA ball grid array, ball grid array
  • the soldering layer or LGA (land grid array, planar grid array) soldering layer is connected to the single board, which can obtain significant area gains, thereby effectively alleviating the problem of limited layout and wiring of electronic product circuit boards.
  • the DSM double side molding, double-sided plastic packaging
  • the DSM double side molding, double-sided plastic packaging
  • the DSM double side molding, double-sided plastic packaging
  • the present application provides a chip packaging structure and packaging system, which can weaken the electromagnetic signal interference generated between the chip and the signal soldering point when they are arranged on the same layer.
  • the present application provides a chip packaging structure, which can be coupled with a PCB to form a packaging system.
  • the chip packaging structure includes a packaging substrate, a chip, a plurality of signal soldering points and a plurality of grounding soldering points; the packaging substrate provides support for the entire structure, and has opposite first and second surfaces; the above-mentioned chip, a plurality of signal soldering points and multiple ground soldering points are coupled to the first surface, which is equivalent to setting the chip, multiple signal soldering points and multiple ground soldering points on the same layer; one or more of the multiple ground soldering points are arranged between the chip and the multiple ground soldering points Multiple signal soldering points are used to isolate the chip from multiple signal soldering points.
  • the ground soldering point can act as an electromagnetic shielding structure to reduce adverse radiation interference.
  • the chip and the signal soldering point are arranged on the same layer, and the grounding soldering point can isolate the chip from the signal soldering point, which can protect the chip from radiation interference of the signal soldering point, or protect the signal soldering point from radiation interference of the chip;
  • its structure is the adjustment of the welding point, which can be fully compatible with the process flow of DSM SiP, taking into account the electromagnetic protection performance and the cost of the product.
  • the chip may be a power device, and the plurality of signal welding points are welding points for transmitting interference-sensitive signals; or, the chip is an interference-sensitive device, and the plurality of signal welding points are welding points for transmitting power signals.
  • the plurality of signal soldering points and the plurality of grounding soldering points can be solder balls, and no additional process steps are required during process preparation, thereby reducing production costs.
  • multiple ground soldering points are arranged around the chip, which can form a "Faraday cage" on the periphery of the chip to achieve a good electromagnetic shielding effect.
  • the chip packaging structure also includes a first packaging layer arranged on the first surface and covering the chip, a plurality of signal soldering points and a plurality of grounding soldering points penetrate the first packaging layer and protrude from the surface of the first packaging layer, convenient Multiple signal soldering points and multiple grounding soldering points are soldered to the PCB to achieve coupling between the chip package structure and the PCB.
  • the chip packaging structure also includes an electronic device coupled to the second surface, and the package substrate includes a communication channel for connecting the electronic device and the chip, providing a reference ground for the chip to realize related electrical functions.
  • a second encapsulation layer is provided on the second surface, and the second encapsulation layer covers the above-mentioned electronic devices; moreover, a protective coating is formed on the surface of the second encapsulation layer by sputtering.
  • the present application also provides a packaging system, the packaging system includes a PCB and any one of the above-mentioned chip packaging structures, and the PCB is coupled to multiple grounding pads through the above-mentioned multiple signal soldering points To the chip package structure, it can help the system realize the function.
  • FIG. 1a to 1c are schematic cross-sectional structural diagrams of a packaging system in the prior art
  • FIG. 2 is a schematic cross-sectional structure diagram of a chip packaging structure provided by an embodiment of the present application
  • FIG. 3a is a schematic diagram of electromagnetic signal interference generated by signal soldering points in an interference-sensitive device in a chip packaging structure provided by an embodiment of the present application;
  • Fig. 3b is a schematic diagram of electromagnetic signal interference generated by a ground signal point weakening signal soldering point to an interference-sensitive device in a chip packaging structure provided by an embodiment of the present application;
  • 3c to 3e are top views of distribution states of interference-sensitive devices, signal soldering points, and grounding soldering points in a chip packaging structure provided by an embodiment of the present application;
  • Fig. 4a is a schematic diagram of electromagnetic signal interference generated by a power device on a signal soldering point in a chip packaging structure provided by an embodiment of the present application;
  • FIG. 4b is a schematic diagram of electromagnetic signal interference generated by a ground signal point weakening a power device to a signal soldering point in a chip package structure provided by an embodiment of the present application;
  • 4c to 4e are top views of distribution states of power devices, signal soldering points, and grounding soldering points in a chip packaging structure provided by an embodiment of the present application;
  • FIG. 5 is a schematic cross-sectional structure diagram of a packaging system provided by an embodiment of the present application.
  • the resistance-capacitance sensing device 20 (can also be other passive devices or active devices) is arranged above the multilayer substrate 10, the chip 30 is arranged under the multilayer substrate 10, and the solder ball 40 is also located on the multilayer substrate 10.
  • solder ball 40 here is equivalent to the signal soldering point; in this structure, the chip 30 and the solder ball 40 are located on the same layer, which means that the chip 30 "occupies” the space originally belonging to the solder ball 40, resulting in this packaging structure
  • the number and layout of solder balls 40 are limited.
  • the chip 30 in Figure 1a is a sensitive device 301
  • the solder ball 40 includes a power signal solder ball 401
  • there is a risk that the power signal solder ball 401 interferes with the sensitive device 301 as indicated by the arrow in Figure 1b shown
  • FIG. 1c when the chip 30 in FIG.
  • the solder ball 40 includes a sensitive signal solder ball 402
  • the power device 302 interferes with the sensitive signal solder ball 402 (as shown in FIG. 1c indicated by the arrow).
  • the risk of interference can be reduced by increasing the distance between the sensitive signal and the radiation source.
  • the chip 30 is usually located in the center of the SIP structure. Due to the current SIP structure size limitation, it can be used to separate the power signal solder ball 401 from the sensitive device. The size of the distance between 301 or the distance between the sensitive signal solder ball 402 and the power device 302 is not sufficient to release this risk.
  • the embodiment of the present application provides a chip packaging structure to weaken the electromagnetic signal interference between the chip and the signal pad when there is a risk of electromagnetic signal interference when the chip and the signal pad are arranged on the same layer.
  • references to "one embodiment” or “some embodiments” or the like in this specification means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application.
  • appearances of the phrases “in one embodiment,” “in some embodiments,” “in other embodiments,” “in other embodiments,” etc. in various places in this specification are not necessarily All refer to the same embodiment, but mean “one or more but not all embodiments” unless specifically stated otherwise.
  • the terms “including”, “comprising”, “having” and variations thereof mean “including but not limited to”, unless specifically stated otherwise.
  • FIG. 2 is a schematic cross-sectional structure diagram of a chip package structure 100 provided by an embodiment of the present application, which is a SiP structure using a DSM process.
  • the chip package structure 100 includes a package substrate 1, the package substrate 1 here is a multi-layer plate structure, with a first surface a1 and a second surface a2 opposite to each other; a chip 2 and a signal soldering point 3 are coupled on the first surface a1 As well as the grounding pad 4, the electronic device 5 is coupled on the second surface a2, and the communication channel 11 for connecting the chip 2 and the electronic device 5 is formed in the packaging substrate 1 to provide a reference ground for the chip 2.
  • the electronic device 5 here may be a passive device, may also be an active device, and may also be other devices, such as a combination of one or more of resistors, capacitors, and inductors. It should be understood that a chip here is an unpackaged single unit die.
  • the first encapsulation layer 61 covering the chip 2 is provided on the first surface a1, and correspondingly, the second encapsulation layer 62 covering the electronic device 5 is provided on the second surface a2; and
  • the surface of the second encapsulation layer 62 is sputtered to form a protective coating 7, and the protective coating 7 can realize the function of a shield, and the area and height of the protective coating 7 are smaller than that of the shield, which is beneficial to realize the miniaturization of the entire structure; It is understood that the above-mentioned structural design of the chip package structure 100 can also obtain a more significant area gain.
  • the side of the first surface a1 of the chip package structure 100 is used for coupling with a PCB or other devices to realize electrical signal connection during process preparation.
  • the signal soldering point 3 and the grounding soldering point 4 are shown in the form of solder balls, and the signal soldering point 3 and the grounding soldering point 4 protrude from the first packaging layer 61 to facilitate the signal soldering point 3,
  • the ground pad 4 is coupled with a PCB or other devices.
  • the signal soldering point 3 , the grounding soldering point 4 and the chip 2 are equivalent to being located on the same layer, and this layer may be called a soldering layer. Wherein, there are multiple signal pads 3, and multiple ground pads 4.
  • one or more of the ground pads 4 are It is arranged between the signal soldering point 3 and the chip 2 to isolate the signal soldering point 3 from the chip 2 , thereby weakening the electromagnetic signal interference between the signal soldering point 3 and the chip 2 .
  • the preparation of the signal soldering point 3 and the grounding soldering point 4 here are conventional process steps in the DSM SiP process, so they are fully compatible with the current process flow of the DSM SiP, without additional process operations, and can take into account the electromagnetic protection performance and Product Cost.
  • chip 2 and signal pad 3 are arranged on the same layer, then chip 2 and signal pad 3 also have the risk of electromagnetic signal interference.
  • Arranging the above-mentioned grounding welding point 4 between them can also play an electromagnetic shielding effect, and this embodiment only takes the DSM SiP process as an example for introduction.
  • the chip 2 is specifically an interference-sensitive device 21 (for example, a chip including a low-noise amplifier), and the plurality of signal welding points 3 are specifically welding points for transmitting power signals (for example, uplink signal welding point, set this soldering point as the first soldering point 31), when a chip package structure includes these two structures at the same time, there is a risk that the first soldering point 31 interferes with the interference-sensitive device 21 (the arrow shows the interference signal in Fig.
  • the interference-sensitive device 21 for example, a chip including a low-noise amplifier
  • the plurality of signal welding points 3 are specifically welding points for transmitting power signals (for example, uplink signal welding point, set this soldering point as the first soldering point 31)
  • the grounding soldering point 4 is equivalent to the first soldering point between the interference sensitive device 21 and the first soldering point A shielding structure is formed between 31, and the grounding welding point 4 can block the electromagnetic signal generated by the interference sensitive device 21 on the side of the grounding welding point 4 facing the first welding point 31, preventing the electromagnetic signal from forming electromagnetic signal interference on the interference sensitive device 21 , so the radiation interference of the first welding point 31 to the interference-sensitive device 21 can be weakened.
  • FIG. 3c shows a top view of the distribution state of an interference-sensitive device 21, the first soldering point 31, and the grounding soldering point 4 in the chip package structure 100, and the interference-sensitive device 21 is located in the center of the structure.
  • the first soldering point 31 is located on one side (upper side) of the interference sensitive device 21, then a row of grounding soldering points 4 is set on the side (upper side) of the interference sensitive device 21 facing the first soldering point 31, this row
  • the ground welding point 4 can isolate the first welding point 31 from the interference sensitive device 21 , preventing the electromagnetic radiation generated by the first welding point 31 from entering and causing electromagnetic signal interference to the interference sensitive device 21 .
  • FIG. 3c only shows a possible structural form.
  • the position of the first soldering point 31 may change, and it is only necessary to set the ground soldering between the first soldering point 31 and the interference-sensitive device 21.
  • Point 4 and it can play an isolation and shielding effect, so no more examples will be given here.
  • the ground soldering point 4 is arranged around the interference sensitive device 21 in a surrounding manner, the first soldering point 31 is located outside the ground soldering point 4, and the ground soldering point 4 is grounded, so that the ground soldering point 4 is equivalent to forming a
  • the "Faraday cage" can effectively realize the electromagnetic shielding function, and also can shield and isolate the interference sensitive device 21 from the first welding point 31, preventing the electromagnetic radiation generated by the first welding point 31 from entering and causing interference to the interference sensitive device 21; the first The setting position of the welding point 31 is not limited and can be set as required.
  • the distribution form in FIG. 3d or the distribution form in FIG. 3e other welding points are common welding points 33 , which will not be described in detail here.
  • the chip 2 is specifically a power device 22 (such as a chip including a power amplifier), and the plurality of signal welding points 3 are specifically welding points for transmitting interference-sensitive signals (such as downlink signal welding). point, set this soldering point as the second soldering point 32), when a chip package structure includes these two structures at the same time, there is a risk that the power device 22 interferes with the second soldering point 32 (arrows in FIG.
  • the ground welding point 4 is set between the power device 22 and a plurality of second welding points 32, as shown in Figure 4b, the ground welding point 4 is equivalent to between the power device 22 and the second welding point 32 A shielding structure is formed, and the ground soldering point 4 can block the electromagnetic radiation generated by the power device 22 on the side of the ground soldering point 4 facing the power device 22, preventing the electromagnetic radiation from interfering with the second soldering point 32, thereby weakening the power device 22 Interference with the electromagnetic signal of the second welding point 32 .
  • FIG. 4c shows a top view of the distribution state of a power device 22, the second soldering point 32 and the grounding soldering point 4 in the chip packaging structure 100.
  • the power device 22 is located in the center of the structure, and the second The second welding point 32 is located on one side (left side) of the power device 22, then a row of grounding welding points 4 is set on the side (left side) of the power device 22 facing the second welding point 32, and this row of grounding welding points 4
  • the second soldering point 32 can be isolated from the power device 22 to prevent the electromagnetic signal generated by the power device 22 from escaping and interfering with the second soldering point 32 .
  • FIG. 4c only shows a possible structural form.
  • the position of the second soldering point 32 may change, and only a grounding soldering point needs to be provided between the second soldering point 32 and the power device 22. 4 and can play an isolation and shielding effect, no more examples will be given here.
  • the ground welding point 4 is arranged on the periphery of the power device 22 in a surrounding manner, the second welding point 32 is located outside the ground welding point 4, and the ground welding point 4 is grounded, so that the ground welding point 4 is equivalent to forming a "Faraday" with respect to the power device 22.
  • the second soldering point 32 is set
  • the location is not limited and can be set as needed.
  • the distribution form in FIG. 4d or the distribution form in FIG. 4e other welding points except the second welding point 32 and the grounding welding point 4 are common welding points 33 , which will not be described in detail here.
  • the signal soldering point 3, the grounding soldering point 4, and other common soldering points 33 are all shown in the structure of solder balls.
  • the material of the solder balls is solder, and its shape is a rugby ball whose upper and lower ends are planes. body replacement.
  • the diameter of the solder ball can be selected to be 260 ⁇ m, the height can be selected to be 190 ⁇ m, and the distance between two adjacent solder balls can be selected to be 350 ⁇ m.
  • these parameters are not limited to this, and are specifically related to process capabilities, and are only for reference.
  • the present application also provides a packaging system, as shown in FIG. 5, the packaging system includes a printed circuit board PCB200 and the chip packaging structure 100 in any of the above-mentioned embodiments.
  • the packaging system includes a printed circuit board PCB200 and the chip packaging structure 100 in any of the above-mentioned embodiments.
  • the side of the chip packaging structure 100 with soldering points is soldered to the PCB 200 to achieve electrical connection.
  • the PCB 200 is coupled to the chip packaging structure 100 through the above-mentioned multiple signal soldering points 3 and multiple grounding soldering points 4, where the multiple signal soldering points Point 3 and multiple ground soldering points 4 can realize electrical signal conduction with PCB 200 , and other possible common soldering points 33 can also achieve electrical signal conduction with PCB 200 , thereby helping the system to realize functions.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

本申请提供了一种芯片封装结构及封装系统，该芯片封装结构包括封装基板、芯片、多个信号焊接点以及多个接地焊接点；封装基板具有相对的第一表面和第二表面，芯片耦合于第一表面，多个信号焊接点耦合于第一表面，多个接地焊接点耦合于第一表面，多个接地焊接点中的一个或多个接地焊接点设置于芯片与多个信号焊接点之间以将芯片和多个信号焊接点隔离。当芯片与信号焊接点之间存在辐射信号干扰时，接地焊接点可以充当电磁屏蔽结构，减弱不利的电磁信号干扰。

Description

芯片封装结构及封装系统 技术领域
本申请涉及芯片封装技术领域，尤其涉及到一种芯片封装结构及封装系统。
背景技术
出于对用户体验的不断追求，小型化与多功能是手机、智能手表等电子产品发展必然的选择，但这些也使得手机、智能手表等平台的单板上可用来布置器件的空间越来越受限，在这种趋势下，SiP(system in package，系统级封装)方案受到业界普遍重视。SiP通过将无源器件或有源器件等电子器件、芯片(Die)、多层基板集成起来，使用溅射保护镀膜等小型化自屏蔽技术，并通过BGA(ball grid array，球形网格阵列)焊接层或LGA(land grid array，平面网格阵列)焊接层连接到单板，可以获得显著的面积收益，从而有效缓解电子产品电路板布局布线受限的问题。
在SiP多种封装集成形式中，DSM(duble side molding，双面塑封)方案是将阻容感等无源器件布置在多层基板上方，同时将芯片和焊球布置在多层基板下方，并对基板的上、下两表面均进行塑封，该方案具有低成本、高面积收益、高成本率等优点。但是这种方案焊球和芯片在同一层，存在互相干扰风险；且由于芯片占据了焊球的布局空间，很难通过拉开二者距离降低干扰风险。
发明内容
本申请提供了一种芯片封装结构及封装系统，可以削弱芯片与信号焊接点同层设置时二者之间的产生的电磁信号干扰。
第一方面，本申请提供了一种芯片封装结构，其可以与PCB耦合形成封装系统。该芯片封装结构包括封装基板、芯片、多个信号焊接点以及多个接地焊接点；封装基板为整个结构提供支持，其具有相对的第一表面和第二表面；上述芯片、多个信号焊接点和多个接地焊接点均耦合于第一表面，相当于芯片、多个信号焊接点和多个接地焊接点同层设置；多个接地焊接点中的一个或多个接地焊接点设置于芯片与多个信号焊接点之间以将芯片和多个信号焊接点隔离，当芯片与多个信号焊接点之间存在电磁信号干扰风险时，接地焊接点可以充当电磁屏蔽结构，减弱不利的辐射干扰。
上述芯片封装结构，芯片和信号焊接点同层设置，接地焊接点可以将芯片和信号焊接点隔离，可以保护芯片不受信号焊接点的辐射干扰，或者保护信号焊接点不受芯片的辐射干扰；且其结构是对焊接点的调整，能够全面兼容DSM SiP的工艺流程，兼顾电磁防护性能与产品的成本。
其中，芯片可以为功率器件，多个信号焊接点为传输干扰敏感信号的焊接点；或者，芯片为干扰敏感器件，多个信号焊接点为传输功率信号的焊接点。这两种情况都存在芯片与信号焊接点之间产生电磁信号干扰的风险，而接地焊接点的存在可以削弱电磁信号干扰。具体的，多个信号焊接点和多个接地焊接点都可以是焊球，在工艺制备时，不需要额外工艺步骤，降低生产成本。
一种可能实现的方式中，多个接地焊接点以环绕芯片的方式设置，可以在芯片的外周 形成“法拉第笼”，达到良好的电磁屏蔽效果。
该芯片封装结构还包括设置于第一表面并包覆芯片的第一封装层，多个信号焊接点和多个接地焊接点穿透第一封装层并凸出于第一封装层的表面，方便多个信号焊接点和多个接地焊接点与PCB焊接实现芯片封装结构与PCB的耦合。
此外，芯片封装结构还包括电子器件，电子器件耦合于第二表面，在封装基板内包括有用于连通电子器件与芯片的连通通道，为芯片提供参考地，以实现相关的电气功能。为了保证结构的应力可靠性，在第二表面设置有第二封装层，第二封装层包覆上述电子器件；而且，在第二封装层的表面还溅射形成有保护镀膜。
第二方面，基于上述芯片封装结构的结构，本申请还提供一种封装系统，该封装系统包括PCB以及上述任一种芯片封装结构，PCB通过上述多个信号焊接点与多个接地焊接点耦合至芯片封装结构，可以帮助系统实现功能。
附图说明
图1a至图1c为现有技术中的一种封装系统的剖面结构示意图；
图2为本申请实施例提供的一种芯片封装结构的剖面结构示意图；
图3a为本申请实施例提供的一种芯片封装结构中信号焊接点对干扰敏感器件产生电磁信号干扰的示意图；
图3b为本申请实施例提供的一种芯片封装结构中接地信号点削弱信号焊接点对干扰敏感器件产生电磁信号干扰的示意图；
图3c至图3e为本申请实施例提供的一种芯片封装结构中干扰敏感器件、信号焊接点与接地焊接点的分布状态的俯视图；
图4a为本申请实施例提供的一种芯片封装结构中功率器件对信号焊接点产生电磁信号干扰的示意图；
图4b为本申请实施例提供的一种芯片封装结构中接地信号点削弱功率器件对信号焊接点产生电磁信号干扰的示意图；
图4c至图4e为本申请实施例提供的一种芯片封装结构中功率器件、信号焊接点与接地焊接点的分布状态的俯视图；
图5为本申请实施例提供的一种封装系统的剖面结构示意图。
具体实施方式
智能电子产品的发展越来越趋向于小型化，其芯片的封装结构也需要随之适应改进。SIP工艺备受业界重视，目前的SIP结构常采用DSM方案，可以参照图1a所示的一种封装系统的剖面结构。其中，阻容感器件20(也可以是其他的无源器件或者有源器件)布置在多层基板10的上方，芯片30布置在多层基板10的下方，焊球40也位于多层基板10下方，此处的焊球40相当于信号焊接点；该结构中，芯片30与焊球40位于同一层，相当于芯片30“占据”了原本属于焊球40的空间，导致这种封装结构中焊球40的数量与布局受限。如图1b所示，当图1a中的芯片30为敏感器件301，且焊球40包括功率信号焊球401时，存在功率信号焊球401干扰作为敏感器件301的风险(如图1b中箭头所示)；如图1c所示，当图1a中的芯片30为功率器件302，而焊球40包括敏感信号焊球402时， 存在功率器件302干扰敏感信号焊球402的风险(如图1c中箭头所示)。为了释放该风险，可以通过增加敏感信号与辐射源的距离以降低干扰风险，但是芯片30通常处于SIP结构的中心，由于目前SIP结构尺寸所限，可供拉开功率信号焊球401与敏感器件301之间距离或敏感信号焊球402与功率器件302之间距离的尺寸不足以释放该风险。
因此，本申请实施例提供一种芯片封装结构，以在芯片与信号焊接点同层设置存在电磁信号干扰风险时，削弱芯片与信号焊接点之间的电磁信号干扰。
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
以下实施例中所使用的术语只是为了描述特定实施例的目的，而并非旨在作为对本申请的限制。如在本申请的说明书和所附权利要求书中所使用的那样，单数表达形式“一个”、“一种”、“所述”、“上述”、“该”和“这一”旨在也包括例如“一个或多个”这种表达形式，除非其上下文中明确地有相反指示。
在本说明书中描述的参考“一个实施例”或“一些实施例”等意味着在本申请的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。由此，在本说明书中的不同之处出现的语句“在一个实施例中”、“在一些实施例中”、“在其他一些实施例中”、“在另外一些实施例中”等不是必然都参考相同的实施例，而是意味着“一个或多个但不是所有的实施例”，除非是以其他方式另外特别强调。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
请参照图2所示的本申请实施例提供的一种芯片封装结构100的剖面结构示意图，这是一种采用DSM工艺的SiP结构。该芯片封装结构100包括有封装基板1，封装基板1此处为多层板状结构，具有相对的第一表面a1和第二表面a2；在第一表面a1耦合有芯片2、信号焊接点3以及接地焊接点4，在第二表面a2耦合有电子器件5，在封装基板1内形成有用于连通芯片2与电子器件5的连通通道11，为芯片2提供参考地。此处的电子器件5可以是无源器件，也可以是有源器件，还可以是其他的器件，例如电阻、电容、电感中的一种或多种的组合。应当理解，此处的芯片是未封装的单个单元的裸片。为了保护器件增加结构的应力可靠性，在第一表面a1设置包覆芯片2的第一封装层61，对应地，在第二表面a2设置包覆电子器件5的第二封装层62；且在第二封装层62的表面溅射形成保护镀膜7，保护镀膜7则可以实现屏蔽罩的功能，且保护镀膜7在面积与高度方面的需求小于屏蔽罩，有利于实现整个结构的小型化；应当理解，该芯片封装结构100的上述结构设计还可以获得更为显著的面积收益。
此处，芯片封装结构100的第一表面a1一侧在工艺制备时用于与PCB或其他器件耦合以实现电气信号连接。一种可能实现的方式中，信号焊接点3和接地焊接点4以焊球的形式示出，信号焊接点3和接地焊接点4凸出于第一封装层61，以方便信号焊接点3、接地焊接点4与PCB或其他器件耦合。信号焊接点3、接地焊接点4以及芯片2相当于位于同一层，该层可以称之为焊接层。其中，信号焊接点3的数量为多个，接地焊接点4的数量也为多个，为了防止信号焊接点3与芯片2之间产生电磁信号干涉，接地焊接点4中的一个或者多个被设置于信号焊接点3与芯片2之间以将信号焊接点3和芯片2隔离，进而可以削弱信号焊接点3与芯片2之间的电磁信号干扰。此处的信号焊接点3和接地焊接点4的制备都是DSM SiP工艺中常规的工艺步骤，因此可以全面兼容DSM SiP当前的工艺流程，不会产生额外的工艺操作，能够兼顾电磁防护性能与产品成本。当然，在其他非DSM  SiP工艺的封装结构中，如果芯片2与信号焊接点3同层设置，那么芯片2与信号焊接点3也存在电磁信号干扰的风险，在芯片2与信号焊接点3之间设置上述接地焊接点4同样可以起到电磁屏蔽效果，本实施例仅以DSM SiP工艺为例作介绍。
在一些实施例中，如图3a所示，芯片2具体为干扰敏感器件21(例如包括低噪声放大器的芯片)，而多个信号焊接点3具体为传输功率信号的焊接点(例如上行信号焊接点，设定该焊接点为第一焊接点31)，当一个芯片封装结构同时包括这两种结构，存在第一焊接点31干扰干扰敏感器件21的风险(图3a中箭头示出了干扰信号的辐射方向)；在干扰敏感器件21与多个第一焊接点31之间设置接地焊接点4之后，如图3b所示，接地焊接点4则相当于在干扰敏感器件21与第一焊接点31之间形成一屏蔽结构，接地焊接点4可以将干扰敏感器件21产生的电磁信号阻挡在接地焊接点4朝向第一焊接点31一侧，防止该电磁信号对干扰敏感器件21形成电磁信号干扰，因此可以削弱第一焊接点31对干扰敏感器件21的辐射干扰。
一种可能实现的方式中，如图3c示出了芯片封装结构100中的一种干扰敏感器件21、第一焊接点31与接地焊接点4的分布状态的俯视图，干扰敏感器件21位于结构中央，第一焊接点31位于干扰敏感器件21的其中一侧(上侧)，则在干扰敏感器件21朝向第一焊接点31的一侧(上侧)设置一排接地焊接点4，这一排接地焊接点4可以将第一焊接点31与干扰敏感器件21隔离，防止第一焊接点31产生的电磁辐射进入对干扰敏感器件21形成电磁信号干扰。当然，图3c仅示出了一种可能的结构形式，在具体制备工艺中，第一焊接点31的位置可能发生变化，只需要在第一焊接点31与干扰敏感器件21之间设置接地焊接点4且能起到隔离屏蔽效果即可，此处不再举例说明。
为了起到更好的屏蔽效果，请参照图3d所示的干扰敏感器件21、第一焊接点31与接地焊接点4的另一种分布状态的俯视图。其中，接地焊接点4以环绕的方式设置在干扰敏感器件21周围，第一焊接点31位于接地焊接点4的外侧，接地焊接点4接地，使得接地焊接点4相对干扰敏感器件21相当于形成“法拉第笼”，可以有效实现电磁屏蔽功能，也就可以将干扰敏感器件21与第一焊接点31屏蔽隔离，防止第一焊接点31产生的电磁辐射进入对干扰敏感器件21形成干扰；第一焊接点31设置位置不做限定，按需设置。例如图3d中的分布形式或图3e中的分布形式，其他的焊接点为普通焊接点33，此处不再进行详细介绍。
在另一些实施例中，如图4a所示，芯片2具体为功率器件22(例如包括功率放大器的芯片)，而多个信号焊接点3具体为传输干扰敏感信号的焊接点(例如下行信号焊接点，设定该焊接点为第二焊接点32)，当一个芯片封装结构同时包括这两种结构，存在功率器件22干扰第二焊接点32的风险(图4a中箭头示出了干扰信号的辐射方向)；在功率器件22与多个第二焊接点32之间设置接地焊接点4之后，如图4b所示，接地焊接点4则相当于在功率器件22与第二焊接点32之间形成一屏蔽结构，接地焊接点4可以将功率器件22产生的电磁辐射阻挡在接地焊接点4朝向功率器件22一侧，防止该电磁辐射对第二焊接点32形成干扰，因此可以削弱功率器件22对第二焊接点32的电磁信号干扰。
一种可能实现的方式中，如图4c示出了芯片封装结构100中的一种功率器件22、第二焊接点32与接地焊接点4的分布状态的俯视图，功率器件22位于结构中央，第二焊接点32位于功率器件22的其中一侧(左侧)，则在功率器件22朝向第二焊接点32的一侧(左侧)设置一排接地焊接点4，这一排接地焊接点4可以将第二焊接点32与功率器件 22隔离，防止功率器件22产生的电磁信号逃脱对第二焊接点32形成干扰。当然，图4c仅示出了一种可能的结构形式，在具体制备工艺中，第二焊接点32的位置可能发生变化，只需要在第二焊接点32与功率器件22之间设置接地焊接点4且能起到隔离屏蔽效果即可，此处不再举例说明。
为了起到更好的屏蔽效果，请参照图4d所示的功率器件22、第二焊接点32与接地焊接点4另一种分布状态的俯视图。其中，接地焊接点4以环绕的方式设置于功率器件22外周，第二焊接点32位于接地焊接点4的外侧，接地焊接点4接地，使得接地焊接点4相对功率器件22相当于形成“法拉第笼”，可以有效实现电磁屏蔽，也就可以将第二焊接点32与功率器件22隔离，防止功率器件22产生的电磁辐射逃脱对第二焊接点32形成电磁信号干扰；第二焊接点32设置位置不做限定，按需设置。例如图4d中的分布形式或图4e中的分布形式，除第二焊接点32与接地焊接点4之外的其他的焊接点为普通的焊接点33，此处不再进行详细介绍。
此处，信号焊接点3、接地焊接点4以及其他的普通焊接点33均以焊球的结构示出，焊球的材质为焊锡，其形状为上下端为平面的橄榄球型，也可以用圆柱体替代。焊球的直径可以选择260μm，高度可以选择190μm，两个相邻的焊球之间的间距可以选择为350μm，当然，这些参数都不限定于此，具体与工艺能力相关，仅做参考示例。
基于上述芯片封装结构100，本申请还提供一种封装系统，如图5所示，该封装系统包括印制电路板PCB200以及上述任一种实施例中的芯片封装结构100，在工艺制备中，芯片封装结构100具有焊接点的一侧与PCB200焊接实现电气连接，具体地，PCB200通过上述多个信号焊接点3以及多个接地焊接点4耦合至芯片封装结构100，此处的多个信号焊接点3以及多个接地焊接点4均可以与PCB200实现电气信号导通，而其他可能存在的普通焊接点33也可与PCB200实现电气信号导通，从而帮助系统实现功能。
以上，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (10)

  1. 一种芯片封装结构，其特征在于，包括：封装基板、芯片Die、多个信号焊接点以及多个接地焊接点；
    所述封装基板具有相对的第一表面和第二表面，所述芯片耦合于所述第一表面，所述多个信号焊接点耦合于所述第一表面，所述多个接地焊接点耦合于所述第一表面，所述多个接地焊接点中的一个或多个接地焊接点设置于所述芯片与所述多个信号焊接点之间以将所述芯片和所述多个信号焊接点隔离。
  2. 如权利要求1所述的芯片封装结构，其特征在于，在所述第一表面上，所述多个接地焊接点环绕所述芯片。
  3. 如权利要求1或2所述的芯片封装结构，其特征在于，所述芯片为功率器件，所述多个信号焊接点为传输干扰敏感信号的焊接点。
  4. 如权利要求1或2所述的芯片封装结构，其特征在于，所述芯片为干扰敏感器件，所述多个信号焊接点为传输功率信号的焊接点。
  5. 如权利要求1-4中任一项所述的芯片封装结构，其特征在于，还包括第一封装层，设置于所述第一表面并包覆所述芯片，所述多个信号焊接点和多个接地焊接点穿透所述第一封装层并凸出于所述第一封装层的表面。
  6. 如权利要求1-5中任一项所述的芯片封装结构，其特征在于，还包括电子器件，所述电子器件耦合于所述第二表面，所述封装基板内包括用于连通所述电子器件与所述芯片的连通通道。
  7. 如权利要求6所述的芯片封装结构，其特征在于，还包括第二封装层，所述第二封装层设置于所述第二表面并包覆所述电子器件。
  8. 如权利要求7所述的芯片封装结构，其特征在于，还包括：形成于所述第二封装层的表面的保护镀膜。
  9. 如权利要求1-8中任一项所述的芯片封装结构，其特征在于，所述多个信号焊接点以及多个接地焊接点均为焊球。
  10. 一种封装系统，其特征在于，包括印制电路板PCB以及如权利要求1-9中任一项所述的芯片封装结构，所述PCB通过所述多个信号焊接点与所述多个接地焊接点耦合至所述芯片封装结构。
PCT/CN2021/093696 2021-05-13 2021-05-13 芯片封装结构及封装系统 WO2022236787A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202180005963.9A CN115633543A (zh) 2021-05-13 2021-05-13 芯片封装结构及封装系统
PCT/CN2021/093696 WO2022236787A1 (zh) 2021-05-13 2021-05-13 芯片封装结构及封装系统

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/093696 WO2022236787A1 (zh) 2021-05-13 2021-05-13 芯片封装结构及封装系统

Publications (1)

Publication Number Publication Date
WO2022236787A1 true WO2022236787A1 (zh) 2022-11-17

Family

ID=84027936

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/093696 WO2022236787A1 (zh) 2021-05-13 2021-05-13 芯片封装结构及封装系统

Country Status (2)

Country Link
CN (1) CN115633543A (zh)
WO (1) WO2022236787A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020079568A1 (en) * 2000-12-27 2002-06-27 Yinon Degani Stacked module package
CN101919053A (zh) * 2008-05-19 2010-12-15 德州仪器公司 具有经集成法拉第屏蔽的集成电路封装
US20130078915A1 (en) * 2011-09-28 2013-03-28 Broadcom Corporation Interposer Package Structure for Wireless Communication Element, Thermal Enhancement, and EMI Shielding
CN103296008A (zh) * 2012-02-22 2013-09-11 中国科学院微电子研究所 Tsv或tgv转接板，3d封装及其制备方法
CN105870109A (zh) * 2016-05-19 2016-08-17 苏州捷研芯纳米科技有限公司 一种2.5d集成封装半导体器件及其加工方法
US20190043811A1 (en) * 2017-01-30 2019-02-07 Skyworks Solutions, Inc. Signal isolation for module with ball grid array

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020079568A1 (en) * 2000-12-27 2002-06-27 Yinon Degani Stacked module package
CN101919053A (zh) * 2008-05-19 2010-12-15 德州仪器公司 具有经集成法拉第屏蔽的集成电路封装
US20130078915A1 (en) * 2011-09-28 2013-03-28 Broadcom Corporation Interposer Package Structure for Wireless Communication Element, Thermal Enhancement, and EMI Shielding
CN103296008A (zh) * 2012-02-22 2013-09-11 中国科学院微电子研究所 Tsv或tgv转接板，3d封装及其制备方法
CN105870109A (zh) * 2016-05-19 2016-08-17 苏州捷研芯纳米科技有限公司 一种2.5d集成封装半导体器件及其加工方法
US20190043811A1 (en) * 2017-01-30 2019-02-07 Skyworks Solutions, Inc. Signal isolation for module with ball grid array

Also Published As

Publication number Publication date
CN115633543A (zh) 2023-01-20

Similar Documents

Publication Publication Date Title
US10211190B2 (en) Semiconductor packages having reduced stress
US6686649B1 (en) Multi-chip semiconductor package with integral shield and antenna
KR100690545B1 (ko) 반도체 장치
US7514774B2 (en) Stacked multi-chip package with EMI shielding
US20140124907A1 (en) Semiconductor packages
US20140124906A1 (en) Semiconductor package and method of manufacturing the same
US20070176281A1 (en) Semiconductor package
KR20220163498A (ko) 간섭 차폐를 위한 와이어 본드 와이어
CN111952273B (zh) 半导体器件封装及其制造方法
US7745911B2 (en) Semiconductor chip package
US9337137B1 (en) Method and system for solder shielding of ball grid arrays
TW201318138A (zh) 晶圓等級應用上的射頻遮蔽件
US9780047B1 (en) Semiconductor package
TWI484616B (zh) 具電磁干擾屏蔽之封裝模組
US8546921B2 (en) Hybrid multilayer substrate
US20080237821A1 (en) Package structure and manufacturing method thereof
TWI624113B (zh) 電子模組
KR20140071561A (ko) 회로 기판과 이를 구비하는 반도체 패키지
JP2011187812A (ja) 高周波モジュール
WO2022236787A1 (zh) 芯片封装结构及封装系统
CN108666279B (zh) 电子封装件及其制法
TW201611227A (zh) 封裝結構
KR101741648B1 (ko) 전자파 차폐 수단을 갖는 반도체 패키지 및 그 제조 방법
CN111081696A (zh) 半导体封装和制造半导体封装的方法
CN217544608U (zh) 半导体装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21941358

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21941358

Country of ref document: EP

Kind code of ref document: A1