TW202242964A - 利用低電阻金屬填充半導體裝置中之凹陷特徵部的方法 - Google Patents

利用低電阻金屬填充半導體裝置中之凹陷特徵部的方法 Download PDF

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Publication number
TW202242964A
TW202242964A TW111109151A TW111109151A TW202242964A TW 202242964 A TW202242964 A TW 202242964A TW 111109151 A TW111109151 A TW 111109151A TW 111109151 A TW111109151 A TW 111109151A TW 202242964 A TW202242964 A TW 202242964A
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Taiwan
Prior art keywords
layer
metal
forming
nucleation
semiconductor device
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TW111109151A
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English (en)
Chinese (zh)
Inventor
尤凱鴻
仕昇 張
英 崔克特
志方 劉
蘊 韓
張賀楠
科瑞 瓦伊達
羅伯特 Ｄ 克拉克
赫里特 Ｊ 盧森克
吉亞納蘭江 帕塔奈克
新實寬明
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日商東京威力科創股份有限公司
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Publication of TW202242964A publication Critical patent/TW202242964A/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/035—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/057—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/0595—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by using multiple deposition steps separated by etching steps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/096—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by contacting with gases, liquids or plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)
TW111109151A 2021-03-16 2022-03-14 利用低電阻金屬填充半導體裝置中之凹陷特徵部的方法 TW202242964A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US202163161909P 2021-03-16 2021-03-16
US63/161,909 2021-03-16

Publications (1)

Publication Number Publication Date
TW202242964A true TW202242964A (zh) 2022-11-01

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TW111109151A TW202242964A (zh) 2021-03-16 2022-03-14 利用低電阻金屬填充半導體裝置中之凹陷特徵部的方法

Country Status (5)

Country Link
US (1) US12237216B2 (https=)
JP (1) JP7781360B2 (https=)
KR (1) KR20230156342A (https=)
TW (1) TW202242964A (https=)
WO (1) WO2022197479A1 (https=)

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001053023A (ja) 1999-08-11 2001-02-23 Tokyo Electron Ltd 半導体装置の製造方法及び製造装置
KR101558428B1 (ko) * 2009-03-03 2015-10-20 삼성전자주식회사 반도체 장치의 형성 방법
JP2011216862A (ja) 2010-03-16 2011-10-27 Tokyo Electron Ltd 成膜方法及び成膜装置
JP5654794B2 (ja) 2010-07-15 2015-01-14 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8945305B2 (en) * 2010-08-31 2015-02-03 Micron Technology, Inc. Methods of selectively forming a material using parylene coating
CN105336680B (zh) * 2014-08-13 2020-02-11 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法和电子装置
CN105762109B (zh) * 2014-12-19 2019-01-25 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
US10643893B2 (en) * 2016-06-29 2020-05-05 International Business Machines Corporation Surface area and Schottky barrier height engineering for contact trench epitaxy
US10629478B2 (en) * 2017-08-22 2020-04-21 International Business Machines Corporation Dual-damascene formation with dielectric spacer and thin liner
US10867905B2 (en) * 2017-11-30 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming the same
US11018053B2 (en) * 2018-06-29 2021-05-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with material modification and low resistance plug
US10923393B2 (en) * 2018-09-24 2021-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Contacts and interconnect structures in field-effect transistors
CN112805818B (zh) * 2018-10-10 2024-10-18 东京毅力科创株式会社 用低电阻率金属填充半导体器件中的凹陷特征的方法

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Publication number Publication date
US12237216B2 (en) 2025-02-25
JP2024511023A (ja) 2024-03-12
JP7781360B2 (ja) 2025-12-08
KR20230156342A (ko) 2023-11-14
US20220301930A1 (en) 2022-09-22
WO2022197479A1 (en) 2022-09-22

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