JP7781360B2 - 半導体デバイス内の凹状特徴部を低抵抗率金属で充填する方法 - Google Patents

半導体デバイス内の凹状特徴部を低抵抗率金属で充填する方法

Info

Publication number
JP7781360B2
JP7781360B2 JP2023557010A JP2023557010A JP7781360B2 JP 7781360 B2 JP7781360 B2 JP 7781360B2 JP 2023557010 A JP2023557010 A JP 2023557010A JP 2023557010 A JP2023557010 A JP 2023557010A JP 7781360 B2 JP7781360 B2 JP 7781360B2
Authority
JP
Japan
Prior art keywords
layer
metal
nucleation
recessed feature
silane
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2023557010A
Other languages
English (en)
Japanese (ja)
Other versions
JP2024511023A (ja
JP2024511023A5 (https=
Inventor
ユ，カイ－フン
チャン，シーション
トリケット，イーン
チー－ファン リウ，エリック
ハン，ユン
ジャン，ヘナン
ワイダ，コーリー
ディー クラーク，ロバート
ジェイ ルーシンク，ゲリット
パッタナイク，ギャナランジャン
寛明 新実
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of JP2024511023A publication Critical patent/JP2024511023A/ja
Publication of JP2024511023A5 publication Critical patent/JP2024511023A5/ja
Application granted granted Critical
Publication of JP7781360B2 publication Critical patent/JP7781360B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/035—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/057—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/0595—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by using multiple deposition steps separated by etching steps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/096—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by contacting with gases, liquids or plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2023557010A 2021-03-16 2022-03-07 半導体デバイス内の凹状特徴部を低抵抗率金属で充填する方法 Active JP7781360B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US202163161909P 2021-03-16 2021-03-16
US63/161,909 2021-03-16
PCT/US2022/019152 WO2022197479A1 (en) 2021-03-16 2022-03-07 Method for filling recessed features in semiconductor devices with a low-resistivity metal

Publications (3)

Publication Number Publication Date
JP2024511023A JP2024511023A (ja) 2024-03-12
JP2024511023A5 JP2024511023A5 (https=) 2025-02-26
JP7781360B2 true JP7781360B2 (ja) 2025-12-08

Family

ID=83284091

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023557010A Active JP7781360B2 (ja) 2021-03-16 2022-03-07 半導体デバイス内の凹状特徴部を低抵抗率金属で充填する方法

Country Status (5)

Country Link
US (1) US12237216B2 (https=)
JP (1) JP7781360B2 (https=)
KR (1) KR20230156342A (https=)
TW (1) TW202242964A (https=)
WO (1) WO2022197479A1 (https=)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001053023A (ja) 1999-08-11 2001-02-23 Tokyo Electron Ltd 半導体装置の製造方法及び製造装置
JP2011216862A (ja) 2010-03-16 2011-10-27 Tokyo Electron Ltd 成膜方法及び成膜装置
JP2012023245A (ja) 2010-07-15 2012-02-02 Renesas Electronics Corp 半導体装置及びその製造方法
US20190164887A1 (en) 2017-11-30 2019-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect Structures and Methods of Forming the Same
US20200118871A1 (en) 2018-10-10 2020-04-16 Tokyo Electron Limited Method for filling recessed features in semiconductor devices with a low-resistivity metal

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101558428B1 (ko) * 2009-03-03 2015-10-20 삼성전자주식회사 반도체 장치의 형성 방법
US8945305B2 (en) * 2010-08-31 2015-02-03 Micron Technology, Inc. Methods of selectively forming a material using parylene coating
CN105336680B (zh) * 2014-08-13 2020-02-11 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法和电子装置
CN105762109B (zh) * 2014-12-19 2019-01-25 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
US10643893B2 (en) * 2016-06-29 2020-05-05 International Business Machines Corporation Surface area and Schottky barrier height engineering for contact trench epitaxy
US10629478B2 (en) * 2017-08-22 2020-04-21 International Business Machines Corporation Dual-damascene formation with dielectric spacer and thin liner
US11018053B2 (en) * 2018-06-29 2021-05-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with material modification and low resistance plug
US10923393B2 (en) * 2018-09-24 2021-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Contacts and interconnect structures in field-effect transistors

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001053023A (ja) 1999-08-11 2001-02-23 Tokyo Electron Ltd 半導体装置の製造方法及び製造装置
JP2011216862A (ja) 2010-03-16 2011-10-27 Tokyo Electron Ltd 成膜方法及び成膜装置
JP2012023245A (ja) 2010-07-15 2012-02-02 Renesas Electronics Corp 半導体装置及びその製造方法
US20190164887A1 (en) 2017-11-30 2019-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect Structures and Methods of Forming the Same
US20200118871A1 (en) 2018-10-10 2020-04-16 Tokyo Electron Limited Method for filling recessed features in semiconductor devices with a low-resistivity metal

Also Published As

Publication number Publication date
US12237216B2 (en) 2025-02-25
JP2024511023A (ja) 2024-03-12
KR20230156342A (ko) 2023-11-14
US20220301930A1 (en) 2022-09-22
WO2022197479A1 (en) 2022-09-22
TW202242964A (zh) 2022-11-01

Similar Documents

Publication Publication Date Title
CN112805818B (zh) 用低电阻率金属填充半导体器件中的凹陷特征的方法
KR102780321B1 (ko) 영역 선택적 증착에서 측면 필름 성장의 완화 방법
US7541679B2 (en) Exposed pore sealing post patterning
KR102740084B1 (ko) 상호접속부를 위한 선택적 상향식 금속 피처 충전
CN113314458A (zh) 半导体器件的扩散阻挡部及方法
CN109860102A (zh) 互连结构及其形成方法
US8173538B2 (en) Method of selectively forming a conductive barrier layer by ALD
JP2008532271A (ja) 原子層堆積のための表面のプラズマ前処理
KR20220026452A (ko) 반도체 디바이스를 위한 비아 및 방법
US20220139776A1 (en) Method for filling recessed features in semiconductor devices with a low-resistivity metal
JP2008147644A (ja) ウェットエッチングアンダカットを最小にし且つ超低ｋ（ｋ＜２．５）誘電体をポアシーリングする方法
CN101263591A (zh) 半导体器件结构以及制造具有此结构的半导体器件的方法
JP2025512235A (ja) 選択的金属堆積のための選択的阻害
JP7781360B2 (ja) 半導体デバイス内の凹状特徴部を低抵抗率金属で充填する方法
US12568803B2 (en) Methods of forming interconnect structures
CN118824944A (zh) 形成互连结构的方法
US20240213093A1 (en) Catalyst-enhanced chemical vapor deposition

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20250214

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20250214

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20250916

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20250918

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20251015

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20251015

R150 Certificate of patent or registration of utility model

Ref document number: 7781360

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20260115