JP2024511023A5 - - Google Patents
Info
- Publication number
- JP2024511023A5 JP2024511023A5 JP2023557010A JP2023557010A JP2024511023A5 JP 2024511023 A5 JP2024511023 A5 JP 2024511023A5 JP 2023557010 A JP2023557010 A JP 2023557010A JP 2023557010 A JP2023557010 A JP 2023557010A JP 2024511023 A5 JP2024511023 A5 JP 2024511023A5
- Authority
- JP
- Japan
- Prior art keywords
- layer
- nucleation
- metal
- concave feature
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US202163161909P | 2021-03-16 | 2021-03-16 | |
| US63/161,909 | 2021-03-16 | ||
| PCT/US2022/019152 WO2022197479A1 (en) | 2021-03-16 | 2022-03-07 | Method for filling recessed features in semiconductor devices with a low-resistivity metal |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2024511023A JP2024511023A (ja) | 2024-03-12 |
| JP2024511023A5 true JP2024511023A5 (https=) | 2025-02-26 |
| JP7781360B2 JP7781360B2 (ja) | 2025-12-08 |
Family
ID=83284091
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023557010A Active JP7781360B2 (ja) | 2021-03-16 | 2022-03-07 | 半導体デバイス内の凹状特徴部を低抵抗率金属で充填する方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US12237216B2 (https=) |
| JP (1) | JP7781360B2 (https=) |
| KR (1) | KR20230156342A (https=) |
| TW (1) | TW202242964A (https=) |
| WO (1) | WO2022197479A1 (https=) |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001053023A (ja) | 1999-08-11 | 2001-02-23 | Tokyo Electron Ltd | 半導体装置の製造方法及び製造装置 |
| KR101558428B1 (ko) * | 2009-03-03 | 2015-10-20 | 삼성전자주식회사 | 반도체 장치의 형성 방법 |
| JP2011216862A (ja) | 2010-03-16 | 2011-10-27 | Tokyo Electron Ltd | 成膜方法及び成膜装置 |
| JP5654794B2 (ja) | 2010-07-15 | 2015-01-14 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| US8945305B2 (en) * | 2010-08-31 | 2015-02-03 | Micron Technology, Inc. | Methods of selectively forming a material using parylene coating |
| CN105336680B (zh) * | 2014-08-13 | 2020-02-11 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制作方法和电子装置 |
| CN105762109B (zh) * | 2014-12-19 | 2019-01-25 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
| US10643893B2 (en) * | 2016-06-29 | 2020-05-05 | International Business Machines Corporation | Surface area and Schottky barrier height engineering for contact trench epitaxy |
| US10629478B2 (en) * | 2017-08-22 | 2020-04-21 | International Business Machines Corporation | Dual-damascene formation with dielectric spacer and thin liner |
| US10867905B2 (en) * | 2017-11-30 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures and methods of forming the same |
| US11018053B2 (en) * | 2018-06-29 | 2021-05-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure with material modification and low resistance plug |
| US10923393B2 (en) * | 2018-09-24 | 2021-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Contacts and interconnect structures in field-effect transistors |
| CN112805818B (zh) * | 2018-10-10 | 2024-10-18 | 东京毅力科创株式会社 | 用低电阻率金属填充半导体器件中的凹陷特征的方法 |
-
2022
- 2022-03-07 KR KR1020237030747A patent/KR20230156342A/ko active Pending
- 2022-03-07 WO PCT/US2022/019152 patent/WO2022197479A1/en not_active Ceased
- 2022-03-07 JP JP2023557010A patent/JP7781360B2/ja active Active
- 2022-03-07 US US17/688,343 patent/US12237216B2/en active Active
- 2022-03-14 TW TW111109151A patent/TW202242964A/zh unknown
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