TW202232692A - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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Publication number
TW202232692A
TW202232692A TW110123677A TW110123677A TW202232692A TW 202232692 A TW202232692 A TW 202232692A TW 110123677 A TW110123677 A TW 110123677A TW 110123677 A TW110123677 A TW 110123677A TW 202232692 A TW202232692 A TW 202232692A
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Taiwan
Prior art keywords
capacitor
redistribution
pattern
pad
pads
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TW110123677A
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English (en)
Inventor
鄭校永
金鎭洙
梁現錫
李奇柱
趙浩延
陳翼奎
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南韓商三星電子股份有限公司
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Publication of TW202232692A publication Critical patent/TW202232692A/zh

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Abstract

可提供一種半導體封裝，所述半導體封裝包括：核心基板；半導體晶片，位於核心基板中且具有晶片接墊；重佈線配線層，覆蓋核心基板的下表面且包括電性連接至晶片接墊的重佈線配線及一對電容器接墊，所述晶片接墊及所述一對電容器接墊自重佈線配線層的外表面暴露出；導電膏，分別位於電容器接墊上；以及電容器，藉由導電膏分別位於電容器接墊上且具有位於電容器接墊上的第一外電極及第二外電極。電容器接墊中的每一者包括：接墊圖案，自重佈線配線層的外表面暴露出；以及至少一個通孔圖案，位於接墊圖案的下部分處且電性連接至重佈線配線中的至少一者。通孔圖案相對於接墊圖案的中心線偏心一距離。

Description

半導體封裝以及半導體封裝製造方法
示例性實施例是有關於半導體封裝及/或所述半導體封裝的製造方法。更具體而言，示例性實施例是有關於具有被動裝置的半導體封裝及/或所述半導體封裝的製造方法。 [優先權聲明]
本申請案主張於2020年10月27日在韓國智慧財產局（Korean Intellectual Property Office，KIPO）提出申請的韓國專利申請案第10-2020-0140455號的優先權，所述韓國專利申請案的內容全文併入本案供參考。
具有相對薄的厚度的扇出封裝可包括能夠達成較薄的厚度作為被動裝置的薄膜電容器。薄膜電容器可為用於應用處理器的去耦電容器，且可以背側電容器（Land-Side Capacitor，LSC）的形式製造。LSC型電容器可藉由焊料膏進行安裝。然而，在安裝電容器的迴流製程期間，自焊料膏蒸發的助熔劑氣體可能被收集而在接頭中形成相對大的空隙，藉此降低接面的可靠性。
一些示例性實施例提供能夠改善與電容器的接面可靠性的半導體封裝。
一些示例性實施例提供製造所述半導體封裝的方法。
根據一些示例性實施例，一種半導體封裝可包括：核心基板；至少一個半導體晶片，位於所述核心基板中且具有晶片接墊；重佈線配線層，覆蓋所述核心基板的下表面且包括電性連接至所述晶片接墊的重佈線配線及一對電容器接墊，所述晶片接墊及所述一對電容器接墊自所述重佈線配線層的外表面暴露出且分別電性連接至所述重佈線配線中的對應的重佈線配線；導電膏，分別位於電容器接墊上；以及電容器，藉由所述導電膏位於所述一對電容器接墊上，所述電容器具有第一外電極及第二外電極，所述第一外電極及所述第二外電極分別位於電容器接墊上。電容器接墊中的每一者可包括：接墊圖案，自所述重佈線配線層的所述外表面暴露出；以及至少一個通孔圖案，位於所述接墊圖案的下部分處，所述至少一個通孔圖案電性連接至所述重佈線配線中的至少一者。所述通孔圖案可相對於所述接墊圖案的中心線偏心一距離。
根據一些示例性實施例，一種半導體封裝可包括：重佈線配線層，具有彼此相對的第一表面與第二表面，所述重佈線配線層包括堆疊於至少兩個水平中的重佈線配線，一對電容器接墊自所述第二表面暴露出且分別電性連接至所述重佈線配線中的對應一對重佈線配線；至少一個半導體晶片，位於所述重佈線配線層的所述第一表面上，所述至少一個半導體晶片具有分別電性連接至所述重佈線配線中的對應的重佈線配線的晶片接墊；模製基板，位於所述重佈線配線層上且覆蓋半導體晶片；導電膏，分別位於電容器接墊上；以及電容器，藉由所述導電膏位於所述一對電容器接墊上，所述電容器具有第一外電極及第二外電極，所述第一外電極及所述第二外電極分別位於電容器接墊上。電容器接墊中的每一者可包括：接墊圖案，自所述重佈線配線層的所述第二表面暴露出；以及至少一個通孔圖案，位於所述接墊圖案的下部分處，所述至少一個通孔圖案電性連接至所述重佈線配線中的至少一者。所述通孔圖案可相對於所述接墊圖案的中心線偏心一距離。所述通孔圖案的直徑可為所述接墊圖案的寬度的40%或小於40%。
根據一些示例性實施例，一種半導體封裝可包括：核心基板；至少一個半導體晶片，位於所述核心基板中且具有晶片接墊；重佈線配線層，覆蓋所述核心基板的下表面且包括電性連接至所述晶片接墊的重佈線配線；焊球接墊，自所述重佈線配線層的外表面暴露出；一對電容器接墊，自所述重佈線配線層的外表面暴露出且分別電性連接至所述重佈線配線中的對應的重佈線配線；以及電容器，位於其中導電膏夾置於其間的所述一對電容器接墊上，所述電容器具有第一外電極及第二外電極，所述第一外電極及所述第二外電極分別位於電容器接墊上。電容器接墊中的每一者可包括：接墊圖案，自所述重佈線配線層的所述外表面暴露出；以及至少一個通孔圖案，自接墊圖案向下延伸並電性連接至重佈線配線層。所述接墊圖案可為具有相對長的側及相對短的側的矩形接墊，且所述通孔圖案相對於穿過所述接墊圖案的所述相對短的側的中點的中心線偏心一距離。所述焊球接墊的直徑可大於電容器接墊中的每一者的寬度。
根據一些示例性實施例，作為扇出封裝的半導體封裝可包括：核心基板，在半導體晶片外部的區中被提供作為框架；重佈線配線層，覆蓋所述核心基板的下表面；以及至少一個電容器，位於所述重佈線配線層的外表面上。所述重佈線配線層可包括自其外表面暴露出的一對電容器接墊，且電容器的第一外電極及第二外電極可位於其中導電膏夾置於其間的所述一對電容器接墊上。
電容器接墊中的每一者可包括接墊圖案及至少一個通孔圖案。通孔圖案可相對於接墊圖案的中心線偏心期望的（或作為另外一種選擇，預定的）距離。通孔圖案的直徑可為接墊圖案的寬度的40%或小於40%。
因此，由於通孔圖案被定位成相對於接墊圖案的中心偏心，且通孔圖案具有相對小的直徑，自導電膏（例如，焊料膏）產生的助熔劑氣體（flux gas）可移動至接墊圖案的邊緣區且可容易地自焊料膏逸出，藉此減輕或防止相對大的空隙在通孔圖案上生長。因此，可能改善電容器的接面可靠性。
在下文中，將參照附圖詳細闡釋一些示例性實施例。
當在本說明書中結合數值使用術語「約（about）」或「實質上（substantially）」時，其意指相關聯的數值包括所述數值左右的製造公差（例如，±10%）。此外，當詞語「一般而言」及「實質上」與幾何形狀結合使用時，其意指不要求幾何形狀的精度，但是所述形狀的寬容度處於本揭露的範圍內。此外，不管數值或形狀是被修改為「約」還是「實質上」，應理解，該些數值及形狀應被解釋為包括所述數值或形狀周圍的製造公差或操作公差（例如，±10%）。
圖1是示出根據一些示例性實施例的半導體封裝的剖視圖。圖2是示出圖1中的部分「A」的放大剖視圖。圖3是示出圖2中的第一電容器接墊及第二電容器接墊的平面圖。圖4是示出安裝於圖2中的第一電容器接墊及第二電容器接墊上的電容器的立體圖。
參照圖1至圖4，半導體封裝10可包括核心基板100、佈置於核心基板100中的至少一個半導體晶片200、位於核心基板100的下表面104上的重佈線配線層300以及安裝於重佈線配線層300的外表面上的至少一個電容器420。此外，半導體封裝10可更包括：上部（後側）重佈線配線層350，設置於核心基板100的上表面102上；以及外部連接構件400，設置於重佈線配線層300的外表面上。
在一些示例性實施例中，半導體封裝10可包括被提供作為環繞半導體晶片200的基礎基板的核心基板100。核心基板100可包括核心連接配線120，核心連接配線120設置於其中佈置有半導體晶片200的區域外部的扇出區中，以用作與半導體晶片200的電性連接路徑。因此，半導體封裝10可被提供作為扇出封裝。此外，半導體封裝10可被提供作為上面堆疊有第二封裝的單元封裝。
此外，半導體封裝10可被提供作為系統級封裝（System In Package，SIP）。舉例而言，核心基板100中可佈置有一或多個半導體晶片。半導體晶片可包括包括邏輯電路及/或記憶體晶片的邏輯晶片。邏輯晶片可為用於控制記憶體晶片的控制器。記憶體晶片可包括例如動態隨機存取記憶體（dynamic random access memory，DRAM）、靜態隨機存取記憶體（static random access memory，SRAM）、快閃、相變隨機存取記憶體（phase-change random access memory，PRAM）、電阻式隨機存取記憶體（resistive random access memory，ReRAM）、鐵電隨機存取記憶體（ferroelectric random access memory，FeRAM）、磁阻式隨機存取記憶體（magneto-resistive random access memory，MRAM）或類似物等各種記憶體電路。
在一些示例性實施例中，核心基板100可具有彼此相對的第一表面102（例如，上表面）與第二表面104（例如，下表面）。核心基板100可在其中間區中具有空腔106。空腔106可自核心基板100的第一表面102延伸至第二表面104。
核心基板100可包括多個堆疊的絕緣層110、112及在絕緣層中被提供作為導電連接件的核心連接配線120。在其中設置有半導體晶片（晶粒）的區域外部的扇出區中可設置有多個核心連接配線120，用於與安裝於其中的半導體晶片進行電性連接。
舉例而言，核心基板100可包括第一絕緣層110及堆疊於第一絕緣層110上的第二絕緣層112。核心連接配線120可包括第一金屬配線122、第一接觸件123、第二金屬配線124、第二接觸件125及第三金屬配線126。在核心基板100的第二表面104中（例如，在第一絕緣層110的下表面中）可設置有第一金屬配線122，且第一金屬配線122的至少一部分可自第二表面104暴露出。在核心基板100的第一表面102中（例如，在第二絕緣層112的上表面中）可設置有第三金屬配線126，且第三金屬配線126的至少一部分可自第一表面102暴露出。可理解，絕緣層及核心連接配線的數目及佈置可不限於此。
在一些示例性實施例中，半導體晶片200可設置於核心基板100的空腔106內。半導體晶片200的側壁可與空腔106的內側壁間隔開。因此，半導體晶片200的側壁與空腔106的內側壁之間可形成有間隙（gap）。
半導體晶片200可包括基板及位於有效表面（例如，基板的前表面202）上的晶片接墊210。半導體晶片200可被佈置成使得上面形成有晶片接墊210的前表面面朝下。因此，晶片接墊210可自核心基板100的第二表面104暴露出。半導體晶片200的前表面可與核心基板100的第二表面104共面。半導體晶片200的與前表面202相對的後側表面204可位於較核心基板100的第一表面102高的平面上。
在一些示例性實施例中，核心基板100的第一表面102上可設置有密封層130，以覆蓋半導體晶片200。密封層130可被形成為填充半導體晶片200的側壁與空腔106的內側壁之間的間隙。因此，密封層130可覆蓋半導體晶片200的後側表面、核心基板100的第一表面102及空腔106的內側壁。
舉例而言，密封層130可包含熱固性絕緣材料（例如，環氧樹脂）、感光成像介電（photo imageable dielectric，PID）材料、絕緣膜（例如，味之素構成膜（Ajinomoto Build-up Film，ABF））等。
在一些示例性實施例中，核心基板100的第二表面104及半導體晶片200的前表面202上可佈置有重佈線配線層300。重佈線配線層300可包括第一重佈線配線302，第一重佈線配線302分別電性連接至半導體晶片200的晶片接墊210及核心連接配線120。第一重佈線配線302可設置於核心基板100的第二表面104上，以用作前側重佈線配線。重佈線配線層300可為扇出封裝的前重佈線配線層。
舉例而言，重佈線配線層300可包括第一重佈線配線層，所述第一重佈線配線層具有設置於第一下部絕緣層310上的第一下部重佈線配線312。
第一下部絕緣層310可設置於核心基板100的第二表面104上且可具有分別暴露出半導體晶片200的晶片接墊210及核心連接配線120的第一金屬配線122的第一開口。第一下部重佈線配線312可設置於第一下部絕緣層310上，且第一下部重佈線配線312的部分可經由第一開口而分別與晶片接墊210及第一金屬配線122接觸。
重佈線配線層300可包括第二重佈線配線層，所述第二重佈線配線層具有設置於第二下部絕緣層320上的第二下部重佈線配線322。
第二下部絕緣層320可設置於第一下部絕緣層310上且可具有分別暴露出第一下部重佈線配線312的第二開口。第二下部重佈線配線322可設置於第二下部絕緣層320上，且第二下部重佈線配線322的部分可經由第二開口而分別與第一下部重佈線配線312接觸。
重佈線配線層300可包括第三重佈線配線層，所述第三重佈線配線層具有設置於第三下部絕緣層330上的第三下部重佈線配線332。
第三下部絕緣層330可設置於第二下部絕緣層320上且可具有分別暴露出第二下部重佈線配線322的第三開口。第三下部重佈線配線332可設置於第三下部絕緣層330上且第三下部重佈線配線332的部分可經由第三開口而分別與第二下部重佈線配線322接觸。
重佈線配線層300可包括第四下部絕緣層340，第四下部絕緣層340設置於第三下部絕緣層330上且具有暴露出第三下部重佈線配線332的部分的第四開口341、343。
舉例而言，第一下部絕緣層至第四下部絕緣層可包括聚合物層、介電層等。第一下部絕緣層至第四下部絕緣層可包含PID、絕緣膜（例如，ABF）等。第四下部絕緣層可包含與第一下部絕緣層至第三下部絕緣層相同或不同的材料。第一下部重佈線配線至第三下部重佈線配線可包含鋁（Al）、銅（Cu）、錫（Sn）、鎳（Ni）、金（Au）、鉑（Pt）或其合金。
在一些示例性實施例中，重佈線配線層300可包括自其外表面暴露出的焊球接墊342及一對電容器接墊344。外部連接構件400可分別設置於焊球接墊342上。電容器420可安裝於所述一對電容器接墊344上。
如圖2至圖4中所示，用於與焊球接墊342電性連接的第一通孔孔341及用於與電容器接墊344電性連接的第二通孔孔343可設置於第四下部絕緣層340中。第二通孔孔343可包括一對第二通孔孔343a、343b。
第二通孔孔343a、343b可在第一方向（X方向）上被佈置成彼此間隔開。三個第二通孔孔343a可在與第一方向（X方向）垂直的第二方向（Y方向）上被佈置成彼此間隔開。三個第二通孔孔343b可在第二方向（Y方向）上被佈置成彼此間隔開。
第二通孔孔343a、343b中的每一者的直徑D1可小於第一通孔孔341的直徑D2。舉例而言，第二通孔孔343a、343b中的每一者的直徑D1可處於50微米至200微米的範圍內。第一通孔孔341的直徑D2可處於150微米至250微米的範圍內。第二通孔孔343a之間在第二方向上的間隔距離及第二通孔孔343b之間在第二方向上的間隔距離可處於250微米至450微米的範圍內。
所述一對電容器接墊344可包括第一電容器接墊344a及第二電容器接墊344b。第一電容器接墊344a及第二電容器接墊344b中的每一者可包括接墊圖案346及至少一個通孔圖案348。
接墊圖案346可被形成為自第四下部絕緣層340暴露出。通孔圖案348可形成於第二通孔孔343a、343b中的每一者中。通孔圖案348可自接墊圖案346向下延伸，以與第三下部重佈線配線332接觸。接墊圖案346可藉由通孔圖案348電性連接至第三下部重佈線配線332。
接墊圖案346可在通孔圖案348的上部分中具有凹坑347。凹坑347的直徑可實質上等於或小於通孔圖案348的直徑D1。接墊圖案346的厚度T1可處於5微米至25微米的範圍內。通孔圖案348的厚度可與接墊圖案346的厚度相同或實質上相似。
如圖3中所示，第一電容器接墊344a可包括連接至一個接墊圖案346的三個通孔圖案348。第二電容器接墊344b可包括連接至一個接墊圖案346的三個通孔圖案348。此外，接墊圖案346可具有與安裝於其上的電容器420的第一外電極422a及第二外電極422b的形狀對應的形狀。舉例而言，接墊圖案346可具有具有第一側（例如，相對長的側）及第二側（例如，相對短的側）的矩形接墊形狀。
所述三個通孔圖案348可被定位成相對於接墊圖案346的中心線ML偏心期望的（或者作為另外一種選擇，預定的）距離（例如，距離P1、P2）。中心線ML可穿過接墊圖案346的短側的中點。
舉例而言，接墊圖案346在相對短的側的延伸方向（X方向）上的長度（例如，接墊圖案346的寬度W）可處於150微米至500微米的範圍內。接墊圖案346在相對長的側的延伸方向（Y方向）上的長度（例如，接墊圖案346的長度L）可處於600微米至1200微米的範圍內。通孔圖案348的直徑可為接墊圖案346的寬度W的40%或小於40%。通孔圖案348的直徑可處於50微米至200微米的範圍內。
所述一對電容器接墊344的接墊圖案346可在第一方向（X方向）上彼此間隔開。接墊圖案346之間在第一方向（X方向）上的間隔距離q可處於130微米至300微米的範圍內。
所述三個通孔圖案348可沿著接墊圖案346的相對長的側的延伸方向（例如，第二方向（Y方向））彼此間隔開。通孔圖案348之間在第二方向（Y方向）上的間隔距離可處於250微米至450微米的範圍內。第一電容器接墊344a的接墊圖案346可具有兩個相對長的側S1a、S2a，且第二電容器接墊344b的接墊圖案346可具有兩個相對長的側S1b、S2b。
在一些示例性實施例中，第一電容器接墊344a的接墊圖案346與第二電容器接墊344b的接墊圖案346可具有被定位成彼此相對靠近的側S2a與側S1b。第一電容器接墊344a的接墊圖案346及第二電容器接墊344b的接墊圖案346可具有被定位成彼此相對遠離的側S1a與側S2b。
第一電容器接墊344a的所述三個通孔圖案348可被定位成朝向接墊圖案346的被定位成相對靠近第二電容器接墊344b的接墊圖案346的一側S2a偏心。即，第一電容器接墊344a的所述三個通孔圖案348可與側S2a相鄰地佈置。
第二電容器接墊344b的所述三個通孔圖案348可被定位成朝向接墊圖案346的被定位成相對靠近第一電容器接墊344a的接墊圖案346的一側S1b偏心。即，第二電容器接墊344b的所述三個通孔圖案348可與側S1b相鄰地佈置。
在一些示例性實施例中，第一電容器接墊344a的接墊圖案346可具有彼此相對的相對短的側S3a、S4a，且第二電容器接墊344b的接墊圖案346可具有彼此相對的相對短的側S3b、S4b。
在第一通孔孔341中的每一者中可形成有焊球接墊342。焊球接墊342的直徑可大於接墊圖案346的寬度W。焊球接墊342的直徑可處於160微米至260微米的範圍內。
在一些示例性實施例中，在焊球接墊342上可分別設置有外部連接構件400（例如，焊球），且在所述一對電容器接墊344上可安裝有電容器420。電容器420的第一外電極422a及第二外電極422b可分別藉由導電膏410而貼附在第一電容器接墊344a及第二電容器接墊344b上。
電容器420可為作為去耦電容器的薄膜電容器。電容器420可為設置於重佈線配線層300的與半導體晶片200相對的外表面上的背側電容器（LSC）型電容器。
導電膏410可包括焊料膏。導電膏410中可具有空隙412。空隙412可位於凹坑347上方。導電膏410的厚度T2可處於5微米至15微米的範圍內。電容器420的厚度T3可處於50微米至120微米的範圍內。
在一些示例性實施例中，在核心基板100的第一表面102及半導體晶片200的後側表面204上可設置有上部重佈線配線層350，且上部重佈線配線層350可包括分別電性連接至核心連接配線120的第二重佈線配線352。第二重佈線配線352可設置於核心基板100的第一表面102上，以用作後側重佈線配線。因此，上部重佈線配線層可為後側重佈線配線層。
舉例而言，上部重佈線配線層350可包括：第一上部絕緣層360，覆蓋電性連接至核心連接配線120的第一上部重佈線配線362。第一上部重佈線配線362可設置於密封層130上且可電性連接至核心連接配線120。
上部重佈線配線層350可包括覆蓋第二上部重佈線配線372的第二上部絕緣層370。第二上部重佈線配線372可設置於第一上部絕緣層360上且可電性連接至第一上部重佈線配線362。第二上部絕緣層370可具有暴露出第二上部重佈線配線372的開口371。
舉例而言，第一上部絕緣層及第二上部絕緣層可包含熱固性絕緣材料（例如，環氧樹脂）、感光成像介電（PID）材料、絕緣膜（例如，味之素構成膜（ABF））等。第一下部重佈線配線及第二下部重佈線配線可包含鋁（Al）、銅（Cu）、錫（Sn）、鎳（Ni）、金（Au）、鉑（Pt）或其合金。
在一些示例性實施例中，外部連接構件400可包括焊球。焊球可具有180微米至250微米的直徑。半導體封裝10可藉由焊球而安裝於模組基板（未示出）上以形成記憶體模組。
如上所述，作為扇出面板級封裝的半導體封裝10可包括：重佈線配線層300，覆蓋核心基板100的第二表面104；以及至少一個電容器420，安裝於重佈線配線層300的外表面上。重佈線配線層300可包括暴露於其外表面的所述一對電容器接墊344，且電容器420的第一外電極422a及第二外電極422b可藉由導電膏410安裝於所述一對電容器接墊344上。電容器接墊344中的每一者可包括接墊圖案346及至少一個通孔圖案348。通孔圖案348可被定位成相對於接墊圖案346的中心線ML偏心期望的（或者作為另外一種選擇，預定的）距離（例如，距離P1、P2）。通孔圖案348的直徑D1可為接墊圖案346的寬度W的40%或小於40%。
由於通孔圖案348被定位成相對於接墊圖案346的中心偏心且通孔圖案348具有相對小的直徑，因此由焊料膏產生的助熔劑氣體可移動至接墊圖案346的邊緣區，且可容易地自焊料膏逸出。因此，可能改善電容器420的接面可靠性。
在下文中，將對製造圖1中的半導體封裝的方法進行闡釋。
圖5至圖18是示出根據一些示例性實施例的製造半導體封裝的方法中的階段的圖。圖5是示出其中形成有多個核心基板的面板的平面圖。圖6至圖10及圖17是沿著圖5中的線I-I’截取的剖視圖。圖11及圖13至圖15是示出圖10中的部分「B」的放大剖視圖，且圖18是示出圖17中的部分「B」的放大剖視圖。圖12是圖11的平面圖，且圖16是圖15的平面圖。
參照圖5至圖7，可製備其中形成有多個核心基板100的面板P，在核心基板100的空腔106內可佈置有半導體晶片200，且然後可形成密封層130以覆蓋半導體晶片200。
在一些示例性實施例中，核心基板100可用作用於製造具有扇出面板級封裝配置的半導體封裝的電性連接的支撐框架。
如圖5中所示，面板P可包括其上形成核心基板100的框架區FR及環繞框架區FR的切割道區（例如，切分區CR）。如稍後所述，可沿著劃分框架區FR的切分區CR對面板P進行鋸切，以形成單獨的核心基板100。
核心基板100可具有彼此相對的第一表面102與第二表面104。核心基板100可在框架區FR的中間區中具有空腔106。如稍後所述，空腔106可具有用於接收至少一個半導體晶片的區域。
核心基板100可包括多個堆疊的絕緣層110、112及在絕緣層中被提供作為導電導體的核心連接配線120。多個核心連接配線120可被設置成自核心基板100的第一表面102至第二表面104穿透過核心基板100，以用作電性連接路徑。即，核心連接配線120可設置於其中設置有半導體晶片（晶粒）的區域外部的扇出區中，以用於與安裝於其中的半導體晶片進行電性連接。舉例而言，核心連接配線120可包括第一金屬配線122、第一接觸件123、第二金屬配線124、第二接觸件125及第三金屬配線126。
如圖6中所示，可在阻擋帶（或者作為另外一種選擇，載體帶）20上佈置面板P，且可在核心基板100的空腔106內設置所述至少一個半導體晶片200。
核心基板100的第二表面104可黏附於阻擋帶20上。舉例而言，可在面板P的空腔106中分別佈置約200至約6,000個晶粒（晶片）。如稍後所述，可執行單體化製程或鋸切製程對面板P進行鋸切，以完成扇出面板級封裝。在一些示例性實施例中，可在一個空腔106內佈置多個半導體晶片200。
半導體晶片200可包括基板及位於基板的前表面（例如，第一表面）上的晶片接墊210。半導體晶片200可被佈置成使得其上形成晶片接墊210的第一表面面朝下。半導體晶片200的前表面可與核心基板100的第二表面104共面。
半導體晶片200可設置於核心基板100的空腔106內。半導體晶片200的側壁可與空腔106的內側壁間隔開。因此，可在半導體晶片200的側壁與空腔106的內側壁之間形成間隙。
半導體晶片200的厚度可大於核心基板100的厚度。因此，半導體晶片200的後側表面204可被定位成高於核心基板100的第一表面102。作為另外一種選擇，半導體晶片200的厚度可等於或小於核心基板100的厚度。在此情況下，核心基板100的後側表面204可與核心基板100的第一表面102共面或被定位成低於核心基板100的第一表面102。
如圖7中所示，可在核心基板100的第一表面102上形成密封層130以覆蓋半導體晶片200。密封層130可被形成為填充半導體晶片200的側壁與空腔106的內側壁之間的間隙。因此，密封層130可覆蓋半導體晶片200的後側表面204、核心基板100的第一表面102及空腔106的內側壁。
舉例而言，密封層130可包含熱固性絕緣材料（例如，環氧樹脂）、感光成像介電（PID）材料、絕緣膜（例如，味之素構成膜（ABF））等。在密封層130包含絕緣膜（例如，ABF）的情況下，密封層130可藉由層壓製程形成。
參照圖8，可在核心基板100的第二表面104及半導體晶片200的前表面202上形成重佈線配線層300。重佈線配線層300可包括第一重佈線配線302，第一重佈線配線302分別電性連接至半導體晶片200的晶片接墊210及核心連接配線120。重佈線配線層300可為扇出封裝的前重佈線配線層。
舉例而言，在移除阻擋帶20之後，可將圖7中的結構顛倒，且可將密封層130黏附在第一載體基板（未示出）上。然後，可形成第一下部絕緣層310以覆蓋核心基板100的第二表面104及半導體晶片200的前表面202，且然後可將第一下部絕緣層310圖案化，以形成分別暴露出半導體晶片200的晶片接墊210及核心連接配線120的第一金屬配線122的開口。
舉例而言，第一下部絕緣層310可包括聚合物層、介電層等。第一下部絕緣層310可包含PID、絕緣膜（例如，ABF）等。第一下部絕緣層310可藉由氣相沈積製程、旋塗製程等形成。
然後，可在第一下部絕緣層310上形成第一下部重佈線配線312。第一下部重佈線配線312可分別經由開口與晶片接墊210接觸。
第一下部重佈線配線312可藉由在第一下部絕緣層310的一部分上及在第一開口中形成晶種層、對晶種層進行圖案化以及執行電鍍製程來形成。因此，第一下部重佈線配線312的至少一部分可經由開口與晶片接墊210及第一金屬配線122接觸。
舉例而言，第一下部重佈線配線可包含鋁（Al）、銅（Cu）、錫（Sn）、鎳（Ni）、金（Au）、鉑（Pt）或其合金。
相似地，可在第一下部絕緣層310上形成第二下部絕緣層320，且然後可將第二下部絕緣層320圖案化以形成分別暴露出第一下部重佈線配線312的開口。然後，可在第二下部絕緣層320上形成第二下部重佈線配線322，以分別經由開口與第一下部重佈線配線312接觸。
然後，可在第二下部絕緣層320上形成第三下部絕緣層330，且然後可將第三下部絕緣層330圖案化以形成分別暴露出第二下部重佈線配線322的開口。然後，可在第三下部絕緣層330上形成第三下部重佈線配線332，以分別經由開口與第二下部重佈線配線322接觸。然後，可在第三下部絕緣層330上形成第四下部絕緣層340，以暴露出第三下部重佈線配線332的部分。
第四下部絕緣層340可充當鈍化層。如稍後所述，可藉由下面的通孔形成製程來部分地移除第四下部絕緣層340，以暴露出第三下部重佈線配線332的部分。此外，可在第三下部重佈線配線332的被第四下部絕緣層340暴露出的部分上形成例如凸塊下金屬（Under Bump Metallurgy，UBM）等凸塊接墊（未示出）。
第四下部絕緣層340可包含感光成像介電（PID）材料、絕緣膜（例如，ABF）等。第四下部絕緣層可包含與第一下部絕緣層至第三下部絕緣層相同或不同的材料。
參照圖9，可在核心基板100的第一表面102及半導體晶片200的後側表面204上的密封層130上形成上部重佈線配線層350。上部重佈線配線層350可包括電性連接至核心連接配線120的第二重佈線配線352。上部重佈線配線層350可為扇出封裝的後側重佈線配線層。
舉例而言，在移除第一載體基板之後，可將重佈線配線層300黏附在第二載體基板（未示出）上。然後，在部分地移除核心基板100的第一表面102上的密封層130以形成暴露出核心連接配線120的第三金屬配線126的開口之後，可在密封層130上形成第一上部重佈線配線362。第一上部重佈線配線362可經由開口電性連接至核心連接配線120。
然後，可在密封層130上形成第一上部絕緣層360以覆蓋第一上部重佈線配線362，且然後可將第一上部絕緣層360圖案化以分別形成暴露出第一上部重佈線配線362的開口。然後，可在第一上部絕緣層360上形成第二上部重佈線配線372，以分別經由開口與第一上部重佈線配線362接觸。
然後，可在第一上部絕緣層360上形成第二上部絕緣層370以覆蓋第二上部重佈線配線372，且然後可將第二上部絕緣層370圖案化以分別形成暴露出第二上部重佈線配線372的開口371。
第二上部絕緣層370可充當鈍化層。可在第二上部重佈線配線372的被第二上部絕緣層370暴露出的部分上形成例如凸塊下金屬（UBM）等凸塊接墊（未示出）。
舉例而言，第一上部絕緣層及第二上部絕緣層可包含熱固性絕緣材料（例如，環氧樹脂）、感光成像介電（PID）材料、絕緣膜（例如，ABF）等。
參照圖10至圖18，可在重佈線配線層300的外表面上安裝外部連接構件400及電容器420。
如圖10及圖11中所示，可將第四下部絕緣層340圖案化以分別形成暴露出第三下部重佈線配線332的部分的開口341、343。
開口可包括用於與焊球接墊電性連接的第一通孔孔341及用於與電容器接墊電性連接的第二通孔孔343。第二通孔孔343可包括一對第二通孔孔343a、343b。
如圖12中所示，第二通孔孔343a、343b可被佈置成在第一方向上彼此間隔開。三個第二通孔孔343a可被佈置成在與第一方向垂直的第二方向上彼此間隔開。三個第二通孔孔343b可被佈置成在第二方向上彼此間隔開。
第二通孔孔343a、343b中的每一者的直徑可小於第一通孔孔341的直徑。舉例而言，第二通孔孔343a、343b中的每一者的直徑可處於50微米至200微米的範圍內。第一通孔孔341的直徑可處於150微米至250微米的範圍內。第二通孔孔343a之間在第二方向上的間隔距離及第二通孔孔343b之間在第二方向上的間隔距離可處於250微米至450微米的範圍內。
可在第四下部絕緣層340中形成第二通孔孔343a、343b。在一些示例性實施例中，可在第四下部絕緣層340及第三下部絕緣層330中形成第二通孔孔343a、343b，以暴露出第二下部重佈線配線322的一部分。在一些其他示例性實施例中，可在第四下部絕緣層340、第三下部絕緣層330、第二下部絕緣層320中形成第二通孔孔343a、343b，以暴露出第一下部重佈線配線312的一部分。
如圖13中所示，可在第四下部絕緣層340上形成晶種層20，且可在晶種層20上形成具有開口31的光阻圖案30，所述開口31暴露出晶種層20的位於第三下部重佈線配線332上的部分。
舉例而言，晶種層20可包括合金層，所述合金層包含鈦/銅（Ti/Cu）、鈦/鈀（Ti/Pd）、鈦/鎳（Ti/Ni）、鉻/銅（Cr/Cu）或其組合。晶種層20可藉由濺射製程形成。
可在第四下部絕緣層340上形成光阻層以覆蓋晶種層22。舉例而言，光阻層的厚度可處於5微米至25微米的範圍內。光阻層的厚度可考慮UBM接墊的厚度等來確定。
然後，可對光阻層執行曝光製程，以形成具有暴露出焊球接墊區及電容器接墊區的開口31的光阻圖案30。
如圖14至圖16中所示，可對晶種層20執行鍍覆製程以形成焊球接墊342及一對電容器接墊344。然後，可移除光阻圖案30且可部分地移除光阻圖案30下方的晶種層20，以形成晶種層圖案22。
所述一對電容器接墊344可包括第一電容器接墊344a及第二電容器接墊344b。第一電容器接墊344a及第二電容器接墊344b中的每一者可包括接墊圖案346及至少一個通孔圖案348。
接墊圖案346可自第四下部絕緣層340暴露出。通孔圖案348可形成在第二通孔孔343a、343b中的每一者中。通孔圖案348可自接墊圖案346向下延伸，以與第三下部重佈線配線332接觸。接墊圖案346可藉由通孔圖案348電性連接至第三下部重佈線配線332。
由於在第四下部絕緣層340的部分及第三下部重佈線配線332的暴露出的部分上共形地形成晶種層20，接墊圖案346可在通孔圖案348的上部分中具有凹坑347。凹坑347的直徑可實質上等於或小於通孔圖案348的直徑。凹坑347的深度可等於或小於通孔圖案348的厚度。
如圖16中所示，第一電容器接墊344a可包括連接至一個接墊圖案346的三個通孔圖案348。第二電容器接墊344b可包括連接至一個接墊圖案346的三個通孔圖案348。此外，接墊圖案346可具有與安裝於其上的電容器的第一外電極及第二外電極的形狀對應的形狀。舉例而言，接墊圖案346可具有具有第一側（相對長的側）及第二側（相對短的側）的矩形接墊形狀。
所述三個通孔圖案348可被定位成相對於接墊圖案346的中心線ML偏心期望的（或者作為另外一種選擇，預定的）距離（例如，距離P1、P2）。中心線ML可穿過接墊圖案346的短側的中點。
舉例而言，接墊圖案346在短側的延伸方向上的長度（即接墊圖案346的寬度W）可處於150微米至500微米的範圍內。接墊圖案346在長側的延伸方向上的長度（即接墊圖案346的長度L）可處於600微米至1200微米的範圍內。通孔圖案348的直徑可為接墊圖案346的寬度W的40%或小於40%。通孔圖案348的直徑可處於50微米至200微米的範圍內。
所述一對電容器接墊344的接墊圖案346可在第一方向上彼此間隔開。接墊圖案346之間在第一方向上的間隔距離q可處於130微米至300微米的範圍內。
所述三個通孔圖案348可沿著接墊圖案346的相對長的側的延伸方向（例如，第二方向）彼此間隔開。通孔圖案348之間在第二方向上的間隔距離可處於250微米至450微米的範圍內。
焊球接墊342的直徑可大於接墊圖案346的寬度W。焊球接墊342的直徑可處於160微米至260微米的範圍內。
如圖17及圖18中所示，可在焊球接墊342上分別設置外部連接構件400，且可在所述一對電容器接墊344上安裝電容器420。
舉例而言，可在第一電容器接墊344a及第二電容器接墊344b上塗覆導電膏410（例如，焊料膏），可在焊球接墊342上塗覆助熔劑，且然後可設置外部連接構件（例如焊球）400。然後，電容器420的第一外電極422a及第二外電極422b可藉由導電膏410貼附在第一電容器接墊344a及第二電容器接墊344b上。
在將電容器420的第一外電極422a及第二外電極422b貼附在第一電容器接墊344a及第二電容器接墊344b上之後，可執行迴流製程以將第一外電極422a及第二外電極422b貼附在第一電容器接墊344a及第二電容器接墊344b上。在迴流製程期間，可自焊料膏產生助熔劑氣體，且產生的氣體的一部分可在凹坑347上的導電膏中形成空隙412。
由於通孔圖案348被定位成相對於接墊圖案346的中心偏心，產生的助熔劑氣體可移動至接墊圖案346的邊緣且可容易地逸出。此外，由於通孔圖案348具有相對小的直徑，可減輕或防止空隙在通孔圖案348上方生長成大的大小。因此，可減輕或防止助熔劑氣體聚集在空隙接墊圖案346的中心處的現象，且空隙412可以小的大小形成於接墊圖案346的邊緣部分處而不是中心處。
然後，可對核心基板100執行鋸切製程，以形成單獨的扇出面板級封裝，所述扇出面板級封裝包括核心基板100、形成於核心基板100的下表面上的重佈線配線層300及安裝於重佈線配線層300的外表面上的電容器420。
圖19是示出根據一些示例性實施例的半導體封裝的一部分的剖視圖。圖20是示出圖19中的第一電容器接墊及第二電容器接墊的平面圖。除了通孔圖案的佈置外，半導體封裝可與參照圖1闡述的半導體封裝相同或實質上相似。因此，相同的參考編號將用於指代相同或相似的元件，且將省略關於上述元件的任何進一步的重複闡釋。
在一些示例性實施例中，第一電容器接墊344a的接墊圖案346與第二電容器接墊344b的接墊圖案346可在第一方向（X方向）上彼此間隔開。所述三個通孔圖案348可被定位成相對於接墊圖案346的中心線ML偏心期望的（或者作為另外一種選擇，預定的）距離（例如，距離P1、P2）。中心線ML可穿過接墊圖案346的短側的中點。所述三個通孔圖案348可沿著接墊圖案346的相對長的側的延伸方向（例如，第二方向（Y方向））間隔開。第一電容器接墊344a的接墊圖案346可具有兩個相對長的側S1a、S2a，且第二電容器接墊344b的接墊圖案346可具有兩個相對長的側S1b、S2b。
在一些示例性實施例中，第一電容器接墊344a的接墊圖案346與第二電容器接墊344b的接墊圖案346可具有被定位成彼此相對靠近的側S2a與側S1b。第一電容器接墊344a的接墊圖案344與第二電容器接墊344b的接墊圖案344可具有被定位成彼此相對遠離的側S1a與側S2b。
第一電容器接墊344a的所述三個通孔圖案348可被定位成朝向接墊圖案344的側S1a偏心，接墊圖案344的側S1a被定位成相對遠離第二電容器接墊344b的接墊圖案344。即，第一電容器接墊344a的所述三個通孔圖案348可與側S1a相鄰地佈置。
第二電容器接墊344b的所述三個通孔圖案348可被定位成朝向接墊圖案344的側S2b偏心，接墊圖案344的側S2b被定位成相對遠離第一電容器接墊344a的接墊圖案344。即，第二電容器接墊344b的所述三個通孔圖案348可與側S2b相鄰地佈置。
圖21是示出根據一些示例性實施例的半導體封裝的剖視圖。圖22是示出圖21中的部分「C」的放大剖視圖。除了附加的第二封裝外，半導體封裝可與參照圖1闡述的半導體封裝相同或實質上相似。因此，相同的參考編號將用於指代相同或相似的元件，且將省略關於上述元件的任何進一步的重複闡釋。
參照圖21，半導體封裝11可包括第一封裝及堆疊於第一封裝上的第二封裝600。半導體封裝11可更包括設置於第二封裝600上的散熱器（heat sink）700。第一封裝可包括核心基板100、半導體晶片200、重佈線配線層300及上部重佈線配線層350。第一封裝可與參照圖1闡述的單元封裝相同或實質上相似。
在一些示例性實施例中，第二封裝600可藉由導電連接構件650堆疊於第一封裝上。
第二封裝600可包括第二封裝基板610、安裝於第二封裝基板610上的第二半導體晶片620及第三半導體晶片630以及位於第二封裝基板610上以覆蓋第二半導體晶片620及第三半導體晶片630的模製構件642。
第二封裝600可藉由導電連接構件650堆疊於第一封裝上。舉例而言，導電連接構件650可包括焊球、導電凸塊等。導電連接構件650可佈置於上部重佈線配線層350的第二上部重佈線配線372與第二封裝基板610的第二結合接墊614之間。因此，第一封裝與第二封裝600可藉由導電連接構件650彼此電性連接。
第二半導體晶片620及第三半導體晶片630可藉由黏合構件堆疊於第二封裝基板610上。結合配線640可將第二半導體晶片620及第三半導體晶片630的晶片接墊622、632電性連接至第二封裝基板610的第一結合接墊612。第二半導體晶片620及第三半導體晶片630可藉由結合配線640電性連接至第二封裝基板610。
儘管圖中示出包括以配線結合方式安裝的兩個半導體晶片的第二封裝600，但是可理解，第二封裝的半導體晶片的數目、安裝方式等可不限於此。
在一些示例性實施例中，散熱器700可設置於第二封裝600上，以將熱量自第一封裝及第二封裝散發至外部。散熱器700可藉由熱介面材料（thermal interface material，TIM）710貼附在第二封裝600上。
參照圖22，第一封裝可包括安裝於重佈線配線層300的外表面上的至少一個電容器420。電容器420可安裝於一對電容器接墊344上。電容器420的第一外電極422a及第二外電極422b可分別藉由導電膏410貼附至第一電容器接墊344a及第二電容器接墊344b。所述一對電容器接墊可與參照圖1至圖4闡述的電容器接墊相同或實質上相似。因此，將省略對電容器接墊的闡述。
圖23是示出根據一些示例性實施例的半導體封裝的剖視圖。除了提供模製基板而不是核心基板的配置，半導體封裝可與參照圖1闡述的半導體封裝相同或實質上相似。因此，相同的參考編號將用於指代相同或相似的元件，且將省略關於上述元件的任何進一步的重複闡釋。
參照圖23，半導體封裝12可包括重佈線配線層300、佈置於重佈線配線層300上的至少一個半導體晶片200、位於重佈線配線層300的上表面上以覆蓋半導體晶片200的至少一個表面的模製基板500以及安裝於重佈線配線層300的下表面上的至少一個電容器420。此外，半導體封裝12可更包括佈置於模製基板500的上表面502上的後側重佈線配線層350及佈置於重佈線配線層300的下表面上的外部連接構件400。
在一些示例性實施例中，半導體晶片200可包括位於半導體晶片200的有效表面（例如，第一表面）上的多個晶片接墊210。半導體晶片200可被接收在模製基板500中，使得其上形成晶片接墊210的第一表面面向重佈線配線層300。
在一些示例性實施例中，可提供導電連接柱550以穿透模製基板500在半導體晶片200外部的區中的至少一部分。導電連接柱550可為自模製基板500的上表面502延伸至下表面504的模製穿孔（mold through via，MTV）。
重佈線配線層300可設置於模製基板500的下表面504上且可具有分別電性連接至半導體晶片200的晶片接墊210的第一重佈線配線302。上部重佈線配線層350可設置於模製基板500的上表面502上且可具有分別電性連接至導電連接柱550的第二重佈線配線352。
電容器420可安裝於設置在重佈線配線層300的外表面上的一對電容器接墊上。所述一對電容器接墊可與參照圖1至圖4闡述的電容器接墊相同或實質上相似。因此，將省略對電容器接墊的闡述。
在下文中，將對製造圖23中的半導體封裝的方法進行闡釋。
圖24至圖30是示出根據一些示例性實施例的製造半導體封裝的方法中的階段的剖視圖。
參照圖24，可在第一載體基板C1上形成晶種層50及具有用於形成導電連接件的開口41的光阻圖案40。
在一些示例性實施例中，第一載體基板C1可包括晶圓基板。晶圓基板W可用作其上佈置有多個半導體晶片的基礎基板，且將形成模製構件以覆蓋半導體晶片。晶圓基板可具有與在其上執行半導體製作製程的晶圓對應的形狀。
晶圓基板可包括其上形成有重佈線配線層的重佈線區及切割道區（即，環繞重佈線區的切分區）。如稍後所述，可沿著劃分重佈線區的切分區對形成於晶圓基板上的重佈線配線層及模製構件進行鋸切以使其單體化。
舉例而言，晶種層50可藉由濺射製程形成。晶種層可包括合金層，所述合金層包含鈦/銅（Ti/Cu）、鈦/鈀（Ti/Pd）、鈦/鎳（Ti/Ni）、鉻/銅（Cr/Cu）或其組合。
在晶種層50上形成光阻層之後，可對光阻層執行曝光製程，以形成具有開口41的光阻圖案40。
參照圖25及圖26，可對晶種層50執行鍍覆製程以形成導電連接柱550作為導電連接件，可移除光阻圖案40，且然後可部分地蝕刻光阻圖案40下方的晶種層50。
參照圖27，可在第一載體基板C1上佈置半導體晶片200，且可形成模製基板500以覆蓋半導體晶片200。半導體晶片200可佈置於第一載體基板C1上，使得其上形成晶片接墊210的前表面面向第一載體基板C1。舉例而言，半導體晶片200的高度可小於導電連接柱550的高度。
模製基板500可形成於第一載體基板C1上，以覆蓋半導體晶片200及多個導電連接柱550。舉例而言，模製基板500可包括環氧模塑化合物（epoxy mold compound，EMC）。模製基板500可藉由模製製程、絲網印刷製程（screen printing process）、層壓製程等形成。
參照圖28，可執行與參照圖8闡述的製程相同或相似的製程，以在模製基板500的下表面504及半導體晶片200的前表面202上形成重佈線配線層300。重佈線配線層300可具有電性連接至半導體晶片200的晶片接墊210及導電連接柱550的第一重佈線配線302。
參照圖29，可執行與參照圖9闡述的製程相同或相似的製程，以在模製基板500的上表面502上形成上部重佈線配線層350。
參照圖30，可執行與參照圖10至圖18闡述的製程相同或相似的製程，以將外部連接構件400及電容器420設置於重佈線配線層300的外表面上。
然後，可藉由鋸切製程對重佈線配線層300及模製基板500進行切分，以形成單獨的半導體封裝。
圖31是示出根據一些示例性實施例的半導體封裝的剖視圖。除了提供模製基板而不是核心基板的配置，半導體封裝可與參照圖21闡述的半導體封裝相同或實質上相似。因此，相同的參考編號將用於指代相同或相似的元件，且將省略關於上述元件的任何進一步的重複闡釋。
參照圖31，半導體封裝13可包括第一封裝及堆疊於第一封裝上的第二封裝600。第一封裝可與參照圖23闡述的單元封裝相同或實質上相似。
在一些示例性實施例中，可提供導電連接柱550以穿透模製基板500在半導體晶片200外部的區中的至少一部分。導電連接柱550可為自模製基板500的上表面502延伸至下表面504的模製穿孔（MTV）。
半導體封裝可包括例如邏輯裝置或記憶體裝置等半導體裝置。半導體封裝可包括：邏輯裝置，例如中央處理單元（central processing unit，CPU）、主處理單元（main processing unit，MPU）或應用處理器（application processor，AP）或類似物；以及揮發性記憶體裝置，例如DRAM裝置、高頻寬記憶體（high bandwidth memory，HBM）裝置；或者非揮發性記憶體裝置，例如快閃記憶體裝置、PRAM裝置、MRAM裝置、ReRAM裝置或類似物。
前述內容是對一些示例性實施例的例示，且不應被解釋為對示例性實施例的限制。儘管已闡述幾個示例性實施例，然而熟習此項技術者將容易理解，在不本質上背離本發明概念的新穎教示及優點的條件下，可在所揭露的示例性實施例中作出諸多修改。因此，所有此種修改均旨在包括於如在申請專利範圍中定義的示例性實施例的範圍內。
10、11、12、13:半導體封裝 20:阻擋帶/晶種層 22:晶種層圖案 30、40:光阻圖案 31、41、371:開口 50:晶種層 100:核心基板 102:上表面/第一表面 104:下表面/第二表面 106:空腔 110:絕緣層/第一絕緣層 112:絕緣層/第二絕緣層 120:核心連接配線 122:第一金屬配線 123:第一接觸件 124:第二金屬配線 125:第二接觸件 126:第三金屬配線 130:密封層 200:半導體晶片 202:前表面 204:後側表面 210、622、632:晶片接墊 300:重佈線配線層 302:第一重佈線配線 310:第一下部絕緣層 312:第一下部重佈線配線 320:第二下部絕緣層 322:第二下部重佈線配線 330:第三下部絕緣層 332:第三下部重佈線配線 340:第四下部絕緣層 341:第四開口/第一通孔孔 342:焊球接墊 343:第四開口/第二通孔孔 343a、343b:第二通孔孔 344:電容器接墊/接墊圖案 344a:第一電容器接墊 344b:第二電容器接墊 346:接墊圖案 347:凹坑 348:通孔圖案 350:上部重佈線配線層/後側重佈線配線層 352:第二重佈線配線 360:第一上部絕緣層 362:第一上部重佈線配線 370:第二上部絕緣層 372:第二上部重佈線配線 400:外部連接構件 410:導電膏 412:空隙 420:電容器 422a:第一外電極 422b:第二外電極 500:模製基板 502:上表面 504:下表面 510:晶種層圖案 550:導電連接柱 600:第二封裝 610:第二封裝基板 612:第一結合接墊 614:第二結合接墊 620:第二半導體晶片 630:第三半導體晶片 640:結合配線 642:模製構件 650:導電連接構件 700:散熱器 710:熱介面材料（TIM） A、B、C:部分 C1:第一載體基板 CR:切分區 D1、D2:直徑 FR:框架區 H:高度 I-I’:線 L:長度 ML:中心線 P:面板/距離 P1、P2:距離 q:間隔距離 S1a、S1b、S2a、S2b:側/相對長的側 S3a、S3b、S4a、S4b:側/相對短的側 T1、T2、T3:厚度 W:寬度/晶圓基板 X、Y、Z:方向
結合附圖閱讀以下詳細說明，將更清楚地理解示例性實施例。圖1至圖31表示如本文中所述的非限制性示例性實施例。 圖1是示出根據一些示例性實施例的半導體封裝的剖視圖。 圖2是示出圖1中的部分「A」的放大剖視圖。 圖3是示出圖2中的第一電容器接墊及第二電容器接墊的平面圖。 圖4是示出安裝在圖2中的第一電容器接墊及第二電容器接墊上的電容器的立體圖。 圖5至圖18是示出根據一些示例性實施例的製造半導體封裝的方法中的階段的圖。 圖19是示出根據一些示例性實施例的半導體封裝的一部分的剖視圖。 圖20是示出圖19中的第一電容器接墊及第二電容器接墊的平面圖。 圖21是示出根據一些示例性實施例的半導體封裝的剖視圖。 圖22是示出圖21中的部分「C」的放大剖視圖。 圖23是示出根據一些示例性實施例的半導體封裝的剖視圖。 圖24至圖30是示出根據一些示例性實施例的製造半導體封裝的方法中的階段的剖視圖。 圖31是示出根據一些示例性實施例的半導體封裝的剖視圖。
10:半導體封裝
100:核心基板
102:上表面/第一表面
104:下表面/第二表面
106:空腔
110:絕緣層/第一絕緣層
112:絕緣層/第二絕緣層
120:核心連接配線
122:第一金屬配線
123:第一接觸件
124:第二金屬配線
125:第二接觸件
126:第三金屬配線
130:密封層
200:半導體晶片
202:前表面
204:後側表面
210:晶片接墊
300:重佈線配線層
302:第一重佈線配線
310:第一下部絕緣層
312:第一下部重佈線配線
320:第二下部絕緣層
322:第二下部重佈線配線
330:第三下部絕緣層
332:第三下部重佈線配線
340:第四下部絕緣層
350:上部重佈線配線層/後側重佈線配線層
352:第二重佈線配線
360:第一上部絕緣層
362:第一上部重佈線配線
370:第二上部絕緣層/晶種層
371:開口
372:第二上部重佈線配線
400:外部連接構件
420:電容器
A:部分

Claims (20)

  1. 一種半導體封裝，包括： 核心基板； 至少一個半導體晶片，在所述核心基板中，所述至少一個半導體晶片具有晶片接墊； 重佈線配線層，覆蓋所述核心基板的下表面，所述重佈線配線層包括電性連接至所述晶片接墊的重佈線配線及一對電容器接墊，所述晶片接墊及所述一對電容器接墊自所述重佈線配線層的外表面暴露出且分別電性連接至所述重佈線配線中的對應的重佈線配線； 導電膏，分別位於所述電容器接墊上；以及 電容器，通過所述導電膏位於一對所述電容器接墊上，所述電容器具有第一外電極及第二外電極，所述第一外電極及所述第二外電極分別位於所述電容器接墊上， 其中所述電容器接墊中的每一者包括： 接墊圖案，自所述重佈線配線層的所述外表面暴露出；以及 至少一個通孔圖案，在所述接墊圖案的下部分處，所述至少一個通孔圖案電性連接至所述重佈線配線中的至少一者，且 其中所述通孔圖案自所述接墊圖案的中心線偏心一距離。
  2. 如請求項1所述的半導體封裝，其中所述通孔圖案的直徑是所述接墊圖案的寬度的40%或小於40%。
  3. 如請求項1所述的半導體封裝，其中所述接墊圖案的寬度在150微米至500微米的範圍內，且所述通孔圖案的直徑在50微米至200微米的範圍內。
  4. 如請求項1所述的半導體封裝，其中所述接墊圖案是具有第一側及第二側的矩形接墊，且所述中心線穿過所述接墊圖案的所述第二側的中點。
  5. 如請求項4所述的半導體封裝，其中至少三個所述通孔圖案是沿著所述第一側的延伸方向且彼此間隔開。
  6. 如請求項5所述的半導體封裝，其中所述通孔圖案之間在所述第一側的所述延伸方向上的間隔距離在250微米至450微米的範圍內。
  7. 如請求項1所述的半導體封裝，其中所述接墊圖案具有在所述通孔圖案的上部分中的凹坑。
  8. 如請求項7所述的半導體封裝，其中所述導電膏中的至少一者具有在所述凹坑上方的空隙。
  9. 如請求項1所述的半導體封裝，其中所述重佈線配線層更包括焊球接墊，所述焊球接墊自所述重佈線配線層的所述外表面暴露出。
  10. 如請求項9所述的半導體封裝，其中所述焊球接墊的直徑大於所述接墊圖案的寬度。
  11. 一種半導體封裝，包括： 重佈線配線層，具有彼此相對的第一表面與第二表面，所述重佈線配線層包括堆疊於至少兩個水平中的重佈線配線以及自所述第二表面暴露出且分別電性連接至所述重佈線配線中對應的一對重佈線配線的一對電容器接墊； 至少一個半導體晶片，在所述重佈線配線層的所述第一表面上，所述至少一個半導體晶片具有分別電性連接至所述重佈線配線中的對應的重佈線配線的晶片接墊； 模製基板，在所述重佈線配線層上且覆蓋所述半導體晶片； 導電膏，分別在所述電容器接墊上；以及 電容器，通過所述導電膏位於一對所述電容器接墊上，所述電容器具有第一外電極及第二外電極，所述第一外電極及所述第二外電極分別在所述電容器接墊上， 其中所述電容器接墊中的每一者包括： 接墊圖案，自所述重佈線配線層的所述第二表面暴露出；以及 至少一個通孔圖案，在所述接墊圖案的下部分處，所述至少一個通孔圖案電性連接至所述重佈線配線中的至少一者， 其中所述通孔圖案自所述接墊圖案的中心線偏心一距離，且 其中所述通孔圖案的直徑是所述接墊圖案的寬度的40%或小於40%。
  12. 如請求項11所述的半導體封裝，其中所述接墊圖案的所述寬度在150微米至500微米的範圍內，且所述通孔圖案的所述直徑在50微米至200微米的範圍內。
  13. 如請求項11所述的半導體封裝，其中所述接墊圖案是具有第一側及第二側的矩形接墊，且所述中心線穿過所述接墊圖案的所述第二側的中點。
  14. 如請求項13所述的半導體封裝，其中至少三個所述通孔圖案是沿著所述第一側的延伸方向且彼此間隔開。
  15. 如請求項14所述的半導體封裝，其中所述通孔圖案之間在所述第一側的所述延伸方向上的間隔距離在250微米至450微米的範圍內。
  16. 如請求項11所述的半導體封裝，其中所述電容器接墊中的一者的所述通孔圖案與所述電容器接墊中的另一者的所述通孔圖案之間的間隔距離在130微米至300微米的範圍內。
  17. 如請求項11所述的半導體封裝，其中所述接墊圖案具有在所述通孔圖案的上部分中的凹坑。
  18. 如請求項17所述的半導體封裝，其中所述導電膏中的至少一者具有在所述凹坑上方的空隙。
  19. 如請求項11所述的半導體封裝，其中 所述重佈線配線層更包括焊球接墊，所述焊球接墊自所述重佈線配線層的所述第二表面暴露出，且 所述焊球接墊的直徑大於所述接墊圖案的所述寬度。
  20. 如請求項11所述的半導體封裝，更包括： 導電連接柱，穿過所述模製基板的至少一部分且電性連接至所述重佈線配線中的對應一者；以及 第二封裝，堆疊於所述模製基板上且電性連接至所述導電連接柱。
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