TW202218080A - 使用晶片對晶圓接合之封裝堆疊技術(二) - Google Patents
使用晶片對晶圓接合之封裝堆疊技術(二) Download PDFInfo
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Abstract
實施例總體上針對使用晶片對晶圓接合之封裝堆疊技術。裝置之實施例包括第一堆疊層,該第一堆疊層包括一或多個半導體晶粒、組件或兩者,該第一堆疊層進一步包括第一介電層,該第一堆疊層經薄化至第一厚度;以及一或多個半導體晶粒、組件或兩者之第二堆疊層,該第二堆疊層進一步包括第二介電層,該第二堆疊層在該第一堆疊層上製造。
Description
發明領域
本文中所描述之實施例總體上係關於電子裝置之領域,且更特定而言係關於使用晶片對晶圓接合之封裝堆疊技術。
發明背景
在新行動式應用之發展中,雖然成本仍然是發展之主要驅動因素,但堆疊式封裝之高度已成為日益重要的元素。為了將元件裝配於較薄行動電話或其他行動裝置內,或將此類元件裝配於行動裝置內之新位置處(諸如蓄電池下方、板之雙面總成中等),薄層疊封裝(PoP)或分階段晶片方案時重要的未來系統整合應用。
在裝置之習知製造中,為了堆積薄化的堆疊式晶粒、封裝或組件,每一部分可在堆疊之前薄化,或替代地可薄化堆疊式封裝。
由於此等元件之翹曲及硬化行為,在製造中處理極薄晶粒或封裝是很困難的,並且因此製造通常需要額外過程及工具,諸如用以解決毛細管底部填充過程及模製底部填充過程之非導電性膠熱壓縮(TCNCP)。
然而,此等類型之過程給製造增添複雜性,且潛在的產率損失由於處理薄晶粒之問題可顯著地增加裝置製造之成本。
依據本發明之一實施例,係特地提出一種裝置,其包含:一第一堆疊層,包括一或多個半導體晶粒、組件或兩者,該第一堆疊層進一步包括一第一介電層,該第一堆疊層經薄化至一第一厚度;以及一或多個半導體晶粒、組件或兩者之一第二堆疊層,該第二堆疊層進一步包括一第二介電層,該第二堆疊層係在該第一堆疊層上製造。
較佳實施例之詳細說明
本文中所描述之實施例總體上針對使用晶片對晶圓接合之封裝堆疊技術。
在一些實施例中,設備、系統或過程提供使用晶片對晶圓接合之封裝堆疊技術。在一些實施例中,過程提供使用晶片對晶圓接合之具有單晶粒及多晶粒佈置的兩個或更多封裝級之堆疊技術。在一些實施例中,過程在堆疊內之層的數目方面不受限制,且可按需要利用堆疊中之額外層繼續。
在一些實施例中,可包括半導體晶粒(晶片)、組件或兩者(本文中通常稱為晶粒及組件)之一或多個組件在過程(本文中通常稱為模製過程)中與介電材料(其可包括模製化合物、層板或其他介電材料)一起施加至載體,以便產生藉由模製過程人工產生之重構元件。重構元件在本文中通常被稱為「重構晶圓」。然而,實施例不限於特定晶圓或其他形狀。在一些實施例中,重構晶圓接合至載體且薄化至最終厚度,以暴露嵌入的晶粒及組件。
在一些實施例中,可在嵌入載體之前任擇地應用毛細管底部填充,其中毛細管底部填充過程用來包封矽晶粒之底部側面。在一些實施例中,過程可針對不同層替代地使用不同介電材料。例如,由於在實施例中避免處理薄晶粒,所以聚醯亞胺可用於下層(而非模製化合物或層板),其中僅最後層使用模製化合物或層板模製,以為整個封裝提供穩定性。
在一些實施例中,利用晶片對晶圓接合過程,在薄化重構晶圓上形成後側接觸,且下一層晶粒及組件面向下附接至此等後側接觸。在一些實施例中,第二層晶粒及組件然後在模製過程中嵌入(利用模製化合物、層板或其他介電材料),且藉由薄化來暴露。
在一些實施例中,自形成後側接觸至薄化晶圓之過程順序可按需要重複許多次,以便將所需要的許多層堆疊至所得裝置中,其中此類過程順序在不卸下載體的情況下出現,從而貫穿製造過程提供穩定性。
在一些實施例中,過程因此提供薄化堆疊式封裝的已安裝至載體上之部分,且將後續層(若需要,則包括後側RDL)建立至所建立及薄化的重構晶圓上。
在一些實施例中,藉由將不同晶粒及組件維持於重構晶圓內且不卸下載體,單一矽晶粒及組件未經處理成薄晶粒,並且因此單一晶粒之可能翹曲由於薄化而在過程中不是問題。在一些實施例中,使用晶片對晶圓接合之封裝堆疊技術可用來堆積極薄的封裝堆疊,同時減小翹曲且處理由用於處理薄晶圓或晶片之習知過程所產生的問題。在此過程的情況下,可針對特定裝置達成極薄的堆疊高度。
在一些實施例中,由於堆疊及薄化之生產過程使得每一層組件具有與周圍電介質(諸如模製化合物或層板)相同的高度,所以可產生堆疊式設備,在該堆疊式設備中,封裝之不同層之間不存在顯著傾斜,其中所有層係平行的。由於重構晶圓內之許多封裝的平行處理,封裝之最終單一化過程因此可利用簡單筆直割鋸操作,因為沿著封裝之外邊緣,模製化合物或層板之不同層之間不存在階梯式接面。
在一些實施例中,晶片對晶圓製造設備或過程提供以下各項:
(1)因為重構晶圓在最終晶粒附接及最終薄化過程(若需要最終薄化)之前未自載體卸下,所以不面臨處理流程期間晶粒處理及薄化中的翹曲問題。避免處理薄晶粒及晶粒至晶粒附接,且質量回流可用於將晶粒附接至載體上之重構晶圓。由於載體接合,晶粒及組件可經薄化至最小可能厚度,且同時經處理成厚晶圓,其中藉由增添單一層來建立最終穩定性。
(2)在一些實施例中,在每一層處,可組合具有多個不同寬度及高度之多個晶粒及組件,其中層內之不同高度藉由薄化過程平衡。
(3)不同晶粒尺寸可堆疊於彼此之頂部上,其中重構晶圓之每一層的產生針對整個堆疊式封裝產生均勻寬度。
(4)對於多個封裝層堆疊式SiP (封裝中之系統)而言,並排佈置經由任擇地利用堆疊之層之間的後側金屬化再分佈層(RDL),在每一層處不同。
(5)此外,側向RDL可在堆疊式封裝處之每一晶粒層處實現。
(6)在特定實行方案中,除實際限制以外,堆疊中之層的數目(兩級、三級及以上)不存在限制。
(7)設備或過程之實施例可利用標準製造過程及工具。在一些實施例中,晶粒至重構晶圓的連接可藉由焊料凸塊或Cu柱凸塊建立。此外,穿過堆疊式封裝之層的連接可利用穿模通孔(TMV)或穿矽通孔(TSV)建立。
(8)裝置之中間及最終厚度僅受研磨工具公差及類似因素限制,而不受薄晶粒之處理限制。
(9)設備或過程之實施例可利用模製化合物或層板作為電介質。然而,實施例不限於此類材料。
在一些實施例中,裝置包括第一堆疊層,該第一堆疊層包括一或多個半導體晶粒、組件或兩者,該第一堆疊層進一步包括第一介電層,該第一堆疊層經薄化至第一厚度;任擇的金屬化層,該金屬化層在薄化第一堆疊層之後形成於該第一堆疊層之後側上;後側接觸,該後側接觸處於第一堆疊層之後側上;以及一或多個半導體晶粒、組件或兩者之第二堆疊層,該第二堆疊層進一步包括第二介電層,該第二堆疊層經薄化至第二厚度,該第二堆疊層在形成於第一堆疊層上之後側接觸上製造,其中第一堆疊層及第二堆疊層各自在將載體安裝至第一堆疊層之前側時製造。
在一些實施例中,方法包括將一或多個晶粒及組件附接於第一堆疊層中,將載體安裝至第一堆疊層之前側;在第一堆疊層之一或多個晶粒及組件上方模製第一介電層;將第一堆疊層薄化至第一厚度;在第一堆疊層之後側上形成金屬化層;將一或多個晶粒及組件附接於第二堆疊層中,該等一或多個晶粒及組件附接至金屬化層;在第二堆疊層之一或多個晶粒及組件上方模製第二介電層;將第二堆疊層薄化至第二厚度,其中第一堆疊層及第二堆疊層各自在將載體安裝至第一堆疊層之前側時製造。
圖1A為用以例示用於使用晶片對晶圓接合來製造堆疊式封裝之過程的流程圖。在一些實施例中,用於封裝堆疊之過程100包括以下各項:
105:放置及接合載體,以用於製造堆疊式封裝。
110-過程P1(過程P5用於第二層):將半導體晶粒(諸如矽晶粒)及組件附接至載體上以用於第一層,或附接至用於先前層之金屬化以用於第二及後續層。在一些實施例中,晶粒及組件之附接可包括將互連件附接於層之間,以提供Z方向(垂直於堆疊式封裝之層)上之電氣接觸,其中該等互連件可包括穿過半導體晶粒之互連件(穿矽通孔(TSV))或穿過模製介電材料處於半導體晶粒旁邊或半導體晶粒之間的互連件(其可被稱為貫穿模製通孔或通孔條)。
在一些實施例中,在過程P1之前,過程可進一步包括將共用晶圓附接至載體上,其中重構晶圓建立至此類附接晶圓上。
115-過程P2(過程P6用於第二層):模製過程包括將介電材料(包括但不限於,模製化合物或層板)施加至當前層之半導體晶粒及組件上方,以便產生重構晶圓,或將堆疊層添加至重構晶圓。
在一些實施例中,重構晶圓將使用任何已知技術在製造過程期間保持附接至載體,該技術諸如利用靜電卡盤(e-卡盤)、抽吸器、黏合劑或黏合箔(包括經設計以便易於剝離之黏合劑,該黏合劑可例如在施加高溫或UV輻射後損失其黏合強度),或將晶圓安裝至載體或其他底部層上之任何其他方式。
120-過程P3(過程P7用於第二層):研磨當前層之介電材料、半導體晶粒及組件,以便將重構晶圓之當前堆疊層薄化至最終厚度。
125-過程P4(過程P8用於第二層):在一些實施例中,對當前薄化層施加後側金屬化。
130:若將添加額外的堆疊層130,則過程將進行至過程P5,以便附接用於額外的堆疊層之半導體晶粒及組件。
若不添加額外的堆疊層130,則過程進行至:
135-過程P9:自重構晶圓卸下載體。
140-過程P10:對重構晶圓進行前側金屬化。
145-過程P11:用以對重構晶圓進行前側金屬化之球柵陣列或類似應用。
150-過程P12:在一些實施例中,過程可進一步包括將堆疊式封裝單一化成多個裝置。
圖1B為根據實施例之堆疊式封裝的圖解。在一些實施例中,依據圖1A中所例示之過程,重構晶圓170包括薄化層之堆疊,其例示為層1(172)、層2(174)、以及繼續至層n(176),其中每一層利用附接半導體晶粒及組件、模製有電介質、藉由研磨過程薄化來依次建立,且接收後側金屬化(圖1A,110-115),而仍然接合至載體160。在一些實施例中,重構晶圓之堆疊層然後藉由卸下載體、施加前側金屬化、球柵陣列或其他應用以及單一化來進行進一步處理,以產生一或多個最終封裝180。(圖1A,元素135-155)
圖1A及圖1B中所例示之過程及設備在圖2至圖9中進一步例示。
圖2為根據實施例之重建晶圓的圖解。在設備或過程之一些實施例中,提供載體225以用於製造重構晶圓。在一些實施例中,利用實施的矽晶粒及組件210來製造重構晶圓200,其可包括一或多個通孔條215及一或多個穿矽通孔或金屬填充的深溝槽220之實行方案,其中如圖2所示,矽晶粒及組件210具有一第一橫向側壁201及一第二橫向側壁202。
在一些實施例中,重構晶圓200在矽晶粒及組件210上方模製有電介質(其可包括但不限於,模製化合物或層板)以形成一第一模製層,該電介質包括任何通孔條215。例如,見圖1,元素110及115中之過程P1及P2。
圖3為根據實施例之研磨後的重建晶圓之圖解。在設備或過程之一些實施例中,重構晶圓(如圖2中所例示)經受研磨(薄化)過程,從而到達特定厚度以便打開任何通孔條215及任何TSV或金屬填充的溝槽220,從而導致薄化的重構層200。在一些實施例中,在用於薄化重構晶圓230之研磨過程後,矽晶粒及組件210及任何通孔條255及TSV或金屬填充的溝槽220具有相同高度。例如,見圖1,元素120中之過程P3。
圖4A 及圖4B為根據實施例之將組件層疊於薄化重構晶圓上之圖解。在一些實施例中,設備或過程包括施加後側金屬化,其中後側金屬化可為再分佈層(RDL)、墊或層間金屬化。例如,見圖1,元素125中之過程P4。在一些實施例中,施加RDL堆疊可進一步包括施加介電層,以便將RDL之導體與藉由研磨/薄化再分佈層所暴露之矽表面隔離。
圖4A例示具有所施加RDL金屬化之重構層。在一些實施例中,薄化重構晶圓包括施加電介質235及RDL 240。
在一些實施例中,組件之額外層將堆疊於第一堆積層之頂部。圖4A進一步例示其中將展示為具有一第一橫向側壁203及一第二橫向側壁204之矽晶粒及組件245之額外的組件安裝於RDL 240上之實施例,該RDL為設備提供信號再分佈。在設備或過程之一些實施例中,可使用已知技術將組件安裝於RDL層上,該技術包括但不限於,將組件焊接至RDL上(使用SOP(墊上焊料)、Cu柱(銅柱)或焊料凸點技術250)或藉由熱壓接合將組件附接至RDL層。
圖4B例示其中晶粒及組件245直接安裝於通孔條215上、TSV或金屬填充的溝槽(圖4B中未展示)上,或此類元件之組合上之替代實施例,此類安裝在凸點接觸或其他接觸上進行。例如,見圖1,元素115中之過程P5。
雖然圖4A及圖4B中未例示,但晶粒及組件245可包括TSV或金屬填充的溝槽,且安裝可進一步包括將一或多個通孔條與矽晶粒及組件245安裝在一起。
圖5A 及圖5B為根據實施例之模製組件的圖解。在一些實施例中,在安裝額外的晶粒及組件245(如圖4A及圖4B中所例示)後,重構晶圓經受第二模製過程,以便在額外的晶粒及組件245上方提供電介質(諸如模製化合物、層板或其他介電材料)255以形成一第二模製層,從而產生重構晶圓之額外的堆疊層。例如,見圖1,元素115中之過程P6。
圖5A例示其中將模製件255中之組件安裝於RDL 240上之實施例,且圖5B例示其中電介質250中之晶粒及組件245安裝於通孔條215上、TSV或金屬填充的溝槽(圖5B中未展示)上,或此類元件之組合上的替代實施例。
圖6A 及圖6B為根據實施例之任擇研磨後的重建晶圓之圖解。在一些實施例中,重構晶圓可在第二模製過程(如圖5A及圖5B中所例示)後經受第二研磨(薄化)過程。在一些實施例中,若將附加al堆疊層添加至重構晶圓,則重構晶圓經受研磨過程。
在一些實施例中,在用於薄化重構晶圓200之第二研磨過程之後,額外的矽晶粒及組件245及任何TSV、金屬填充的溝槽或通孔條(圖6A及圖6B中未展示)具有相同高度。例如,見圖1,元素120中之過程P7。
圖6A例示其中電介質255中之薄化組件安裝於RDL 240上之實施例,且圖6B例示其中模製件255中之薄化組件245安裝於通孔條215上、TSV或金屬填充的溝槽(圖6B中未展示)上,或此類元件之組合上的替代實施例。
圖7A 及圖7B為根據實施例之重建晶圓在前側金屬化及載體卸下的情況下之圖解。在一些實施例中,若存在將要製造之額外層,則不卸下載體,其中過程繼續任擇後側金屬化,若需要,接著添加新組件,諸如圖4A及圖4B中所例示。
在一些實施例中,若沒有額外的堆疊層添加至重構晶圓,則重構晶圓自載體卸下,見圖1,過程P9,元素130,且重構晶圓200經倒轉以用於施加前側金屬化260、墊開口及焊球應用或類似技術265。在一些實施例中,過程可包括施加電介質270以便將前側金屬化之導體與藉由研磨/薄化再分佈晶圓之堆疊層所暴露的矽表面隔離。見,例如,圖1,過程P10元素140及P11元素150。
在一些實施例中,後側金屬化可進一步施加至重構晶圓之最終堆疊層的後側,接著應用焊球接觸或類似技術。
圖8A 及圖8B為根據實施例之將重建晶圓進行單一化的圖解。在一些實施例中,在完成對前側金屬化之附接及對球柵陣列或類似連接之附接後,可使用單一化工具275將重構晶圓分離(單一化)成分開的裝置,該單一化工具可包括但不限於,鋸條或雷射切割設備。作為單一化之結果,晶粒經單一化成第一裝置280及第二裝置285。
圖9為根據實施例所製造之堆疊式封裝的圖解。在一些實施例中,利用使用晶片對晶圓接合添加層之過程來製造所得最終裝置290,如圖1A及圖1B中所例示,且如圖2至圖8中進一步詳細例示。
在以上描述中,出於解釋之目的,闡明許多特定細節以便提供對所描述實施例之徹底理解。然而,熟習此項技術者將明白,可在無此等特定細節中之一些的情況下實踐實施例。在其他情況下,以方塊圖形式展示熟知的結構及裝置。所例示之組件之間可存在中間結構。本文中所描述或例示之組件可具有未例示或描述的額外輸入或輸出。
各種實施例可包括各種過程。此等過程可由硬體組件進行或可體現於電腦程式或機器可執行指令中,該電腦程式或該等機器可執行指令可用來使以該等指令程式設計的通用處理器或邏輯電路或特殊用途處理器或邏輯電路進行該等過程。或者,過程可由硬體及軟體之組合進行。
各種實施例中之部分可提供為電腦程式產品,該電腦程式產品可包括電腦可讀媒體,該電腦可讀媒體上儲存有電腦程式指令,該等電腦程式指令可用來程式設計電腦(或其他電子裝置)以用於由一或多個處理器執行來進行根據某些實施例之過程。電腦可讀媒體可包括但不限於磁碟片、光碟片、光碟片唯讀記憶體(CD-ROM)及磁光碟片、唯讀記憶體(ROM)、隨機存取記憶體(RAM)、可抹除可規劃唯讀記憶體(EPROM)、電氣可抹除可規劃唯讀記憶體(EEPROM)、磁卡或光卡、快閃記憶體或適合於儲存電子指令的其他類型之電腦可讀媒體。此外,實施例可亦下載為電腦程式產品,其中程式可自遠端電腦傳遞至請求電腦。
方法中之許多係以其最基本的形式被描述,但在不脫離本實施例之基本範疇的情況下,可將過程增添至方法中之任一者或自方法中之任一者刪除,且可將資訊增添至所述訊息中之任一者或自所描述訊息中之任一者減去。熟習此項技術者將明白,可進行許多進一步修改及調適。特定實施例並非提供來限制概念而是提供來例示概念。實施例之範疇將並非由以上提供的特定實例來判定,而僅由以下申請專利範圍來判定。
若說元件「A」耦接至元件「B」或與元件「B」耦接,則元件A可直接耦接至元件B或穿過例如元件C間接耦接。當說明書或申請專利範圍說明組件、特徵、結構、過程或特性A「引起」組件、特徵、結構、過程或特性B時,意味「A」至少是「B」之部分原因,但亦可存在有助於引起「B」之至少一個其他組件、特徵、結構、過程或特性。若說明書指示「可」、「可能」或「可以」包括組件、特徵、結構、過程或特性,則不需要包括特定組件、特徵、結構、過程或特性。若說明書或申請專利範圍引用「一(a或an)」元件,則此不意味僅存在所描述元件中之一者。
實施例為實行方案或實例。說明書中對「一實施例」、「一個實施例」、「一些實施例」或「其他實施例」之引用意味結合實施例描述之特定特徵、結構或特性包括在至少一些實施例中,而不必在所有實施例中。「一實施例」、「一個實施例」或「一些實施例」之各種態樣不一定都參考相同實施例。應瞭解,在示範性實施例之先前描述中,有時出於使揭示內容合理化且幫助理解各種新穎態樣中之一或多個的目的將各種特徵在單個實施例、圖或其描述中分組在一起。然而,此揭示方法將不被解釋為反映所主張之實施例需要比每一請求項中明確表述的更多特徵的意圖。相反,如以下申請專利範圍所反映,新穎態樣在於少於單個先前所揭示實施例之所有特徵。因此,申請專利範圍在此明確併入此描述中,其中每一請求項堅持其自己作為分開的實施例。
在一些實施例中,裝置包括第一堆疊層,該第一堆疊層包括一或多個半導體晶粒、組件或兩者,該第一堆疊層進一步包括第一介電層,該第一堆疊層經薄化至第一厚度;以及一或多個半導體晶粒、組件或兩者之第二堆疊層,該第二堆疊層進一步包括第二介電層,該第二堆疊層在該第一堆疊層上製造。
在一些實施例中,該裝置進一步包括金屬化層,該金屬化層形成於第一堆疊層之前側上。
在一些實施例中,該裝置進一步包括球柵陣列,該球柵陣列附接至形成於第一堆疊層之前側上的金屬化層。
在一些實施例中,該裝置進一步包括金屬化層,該金屬化層形成於第一堆疊層之後側上,第二堆疊層附接至形成於第一堆疊層上之金屬化層。
在一些實施例中,第一金屬化層為再分佈層(RDL)。
在一些實施例中,第一堆疊層包括穿過該第一堆疊層之多個連接,其中該等多個連接包括穿矽通孔(TSV)、金屬填充的溝槽及通孔條之多個任何組合。
在一些實施例中,第二堆疊層附接至多個連接。
在一些實施例中,該裝置為自堆疊式封裝單一化之多個裝置中的一者。
在一些實施例中,第二堆疊層經薄化至第二厚度。
在一些實施例中,該裝置進一步包括一或多個額外的堆疊層,該等一或多個額外的堆疊層中之每一者包括一或多個半導體晶粒、組件或兩者,每一額外的堆疊層進一步包括介電層且耦接至經薄化至特定厚度的先前的層。
在一些實施例中,該裝置之第一介電層及第二介電層中之一或多者包括模製化合物或層板。
在一些實施例中,方法包括將一或多個晶粒及組件附接於第一堆疊層中,將載體安裝至第一堆疊層之前側;在第一堆疊層之一或多個晶粒及組件上方模製第一介電層;將第一堆疊層薄化至第一厚度;將一或多個晶粒及組件附接於第二堆疊層中;以及在第二堆疊層之一或多個晶粒及組件上方模製第二介電層。在一些實施例中,第一堆疊層及第二堆疊層各自在將載體安裝至第一堆疊層之前側時製造。
在一些實施例中,該方法進一步包括自第一堆疊層之前側卸下載體;以及在第一堆疊層之前側上形成金屬化層。
在一些實施例中,該方法進一步包括將球柵陣列附接至第一堆疊層之前側上的金屬化層。
在一些實施例中,該方法進一步包括在第一堆疊層之後側上形成金屬化層,第二堆疊層之一或多個晶粒及組件附接至該金屬化層。
在一些實施例中,將一或多個晶粒及組件附接於第一堆疊層中包括穿過該第一堆疊層之多個連接,該等多個連接包括穿矽通孔(TSV)、金屬填充的溝槽及通孔條之多個任何組合,第二堆疊層附接至該等多個連接。
在一些實施例中,第一堆疊層及第二堆疊層包括在堆疊式封裝中,且進一步包含單一化該堆疊式封裝以產生第一裝置及第二裝置。
在一些實施例中,該方法進一步包括將第二堆疊層薄化至第二厚度。
在一些實施例中,該方法進一步包括製造一或多個額外的堆疊層,該等一或多個額外的堆疊層中之每一者包括一或多個半導體晶粒、組件或兩者,每一額外的堆疊層進一步包括介電層且耦接至經薄化至特定厚度的層。
在一些實施例中,在第一堆疊層之一或多個晶粒及組件上方模製第一介電層產生重構晶圓,並且其中第二堆疊層為該重構晶圓之延伸部。
在一些實施例中,沒有堆疊層在未將載體安裝至第一堆疊層的情況下處理。
在一些實施例中,堆疊式封裝包括第一堆疊層,其中該第一堆疊層包括一或多個半導體晶粒、組件或兩者,且包括第一介電層,且該第一堆疊層經薄化至第一厚度;一或多個額外的堆疊層,其中每一額外的堆疊層包括一或多個半導體晶粒、組件或兩者及介電層,且每一額外的堆疊層藉由晶片對晶圓接合附接至先前的堆疊層,該先前的堆疊層經薄化至特定厚度;金屬化層,該金屬化層形成於第一堆疊層之前側上;以及球柵陣列,該球柵陣列附接至金屬化層。
在一些實施例中,每一額外的堆疊層藉由形成於先前的堆疊層上之金屬化層;或穿過先前的堆疊層之多個連接附接至先前的堆疊層。
在一些實施例中,多個連接包括穿矽通孔(TSV)、金屬填充的溝槽及通孔條之多個任何組合。
在一些實施例中,堆疊式封裝之堆疊層的最終堆疊層之介電層為模製化合物或層板。
在一些實施例中,堆疊式封裝之每一堆疊層為在將載體安裝至第一堆疊層時所製造之層。
100:過程
105-155:元素
160、225:載體
170:重構晶圓
172:層1
174:層2
176:層n
180:最終封裝
200:重構晶圓/重構層
210:矽晶粒及組件
215:通孔條
220:穿矽通孔或金屬填充的深溝槽/TSV或金屬填充的溝槽
235、270:電介質
240:RDL
245:矽晶粒及組件/晶粒及組件
250:SOP(墊上焊料)、Cu柱(銅柱)或焊料凸點技術
255:電介質/模製件
260:前側金屬化
265:焊球應用或類似技術
275:單一化工具
280:第一裝置
285:第二裝置
290:最終裝置
在隨附圖式之諸圖中以實例之方式而非以限制之方式例示在此所描述之實施例,在隨附圖式中相同參考數字代表類似元件。
圖1A為用以例示用於使用晶片對晶圓接合來製造堆疊式封裝之過程的流程圖;
圖1B為根據實施例之堆疊式封裝的圖解;
圖2為根據實施例之重構晶圓的圖解;
圖3為根據實施例之研磨後的重構晶圓之圖解;
圖4A 及圖4B為根據實施例之將組件層疊於薄化重構晶圓上之圖解;
圖5A 及圖5B為根據實施例之模製組件的圖解;
圖6A 及圖6B為根據實施例之研磨後的重構晶圓之圖解;
圖7A 及圖7B為根據實施例之重構晶圓在前側金屬化及載體卸下的情況下之圖解;
圖8A 及圖8B為根據實施例之將重構晶圓進行單一化的圖解;以及
圖9為根據實施例所製造之堆疊式封裝的圖解。
275:單一化工具
280:第一裝置
285:第二裝置
Claims (20)
- 一種裝置,其包含: 一第一堆疊層,其包括一或多個半導體晶粒、組件或兩者,該第一堆疊層進一步包括一第一介電層,該第一堆疊層經薄化至一第一厚度; 一第二堆疊層,其包括一或多個半導體晶粒、組件或兩者,該第二堆疊層進一步包括一第二介電層,該第二堆疊層係在該第一堆疊層上製造,其中該第二介電層並未垂直地在該第一堆疊層之該等一或多個半導體晶粒、組件或兩者與該第二堆疊層之該等一或多個半導體晶粒、組件或兩者之間; 一第一穿模通孔,其在該第一介電層中,該第一穿模通孔從該第一堆疊層之該等一或多個半導體晶粒、組件或兩者之一第一橫向側壁橫向間隔分開,其中該第一穿模通孔延伸在該等第一堆疊層之該等一或多個半導體晶粒、組件或兩者之上,並且其中該第一穿模通孔並未在該第一介電層之一底部之下延伸;以及 一第二穿模通孔,其在該第一介電層中,該第二穿模通孔從該第一堆疊層之該等一或多個半導體晶粒、組件或兩者之一第二橫向側壁橫向間隔分開,其中該第二穿模通孔延伸在該等第一堆疊層之該等一或多個半導體晶粒、組件或兩者之上,並且其中該第二穿模通孔並未在該第一介電層之該底部之下延伸。
- 如請求項1之裝置,其進一步包含形成於該第一堆疊層之一前側上一金屬化層。
- 如請求項2之裝置,其進一步包含一球柵陣列,其附接至形成於該第一堆疊層之一前側上的該金屬化層。
- 如請求項1之裝置,進一步包含形成於該第一堆疊層之一背側上之一金屬化層,該第二堆疊層被附接至形成於該第一堆疊層上之該金屬化層。
- 如請求項4之裝置,其中該第一金屬化層係一再分佈層(RDL)。
- 如請求項1之裝置,其中該第一堆疊層包括通過該第一堆疊層之複數個連接,其中該等複數個連接包括穿矽通孔(TSVs)、金屬填充的溝槽、及穿模通孔之複數個任意組合。
- 如請求項6之裝置,其中該第二堆疊層係附接至該等複數個連接。
- 如請求項1之裝置,其中該裝置係從一堆疊式封裝而單一化之複數個裝置中的一者。
- 如請求項1之裝置,其中該第二堆疊層經薄化至第二厚度。
- 如請求項9之裝置,其進一步包含一或多個額外的堆疊層,該等一或多個額外的堆疊層之每一者包括一或多個半導體晶粒、組件或兩者,每一額外的堆疊層進一步包括一介電層及耦接至經薄化至一特定厚度之一先前的層。
- 如請求項1之裝置,其中該第一及該第二介電層之一或多者包括模製化合物或層板。
- 一種堆疊式封裝,其包含: 一第一堆疊層,其中: 該第一堆疊層包括一或多個半導體晶粒、組件或兩者,並包括一第一介電層, 該第一堆疊層經薄化至一第一厚度;並且該第一堆疊層包含: 在該第一介電層中之一第一穿模通孔,該第一穿模通孔從該第一堆疊層之該等一或多個半導體晶粒、組件或兩者之一第一橫向側壁橫向間隔分開,其中該第一穿模通孔延伸在該第一堆疊層之該等一或多個半導體晶粒、組件或兩者之一頂部上,並且其中該第一穿模通孔並未在該第一介電層之一底部之下方延伸;以及 在該第一介電層中之一第二穿模通孔,該第二穿模通孔從該第一堆疊層之該等一或多個半導體晶粒、組件或兩者之一第二橫向側壁橫向間隔分開,其中該第二穿模通孔延伸在該第一堆疊層之該等一或多個半導體晶粒、組件或兩者之該頂部上,並且其中該第二穿模通孔未在該第一介電層之該底部之下方延伸;以及 一或多個額外的堆疊層,其中: 每一額外的堆疊層包括一或多個半導體晶粒、組件或兩者,並且包括一介電層,其中該額外的堆疊層之一第一者之該介電層並不垂直地在該第一堆疊層之該等一或多個半導體晶粒、組件或兩者與該額外的堆疊層之該第一者之該等一或多個半導體晶粒、組件或兩者之間,以及 每個額外的堆疊層係藉由晶片對晶圓接合來附接至一先前的堆疊層,該先前的堆疊層經薄化至一特定厚度; 形成於該第一堆疊層之一前側上之一金屬化層;以及 附接至該金屬化層之一球柵陣列。
- 如請求項12之堆疊式封裝,其中每個額外的堆疊層係藉由下列之任一者附接至該先前的堆疊層: 形成於該先前的堆疊層上之一金屬化層;或 通過該先前的堆疊層之複數個連接。
- 如請求項13之堆疊封裝體,其中該等複數個連接包括矽通孔(TSVs)、金屬填充的溝槽及穿模通孔之複數個任意組合。
- 如請求項12之堆疊式封裝,其中該堆疊式封裝之該等堆疊層之一最後堆疊層之介電層係模製化合物或層板。
- 一種裝置,其包含: 一重分佈層,其具有相對於一第二側之一第一側,該重分佈層具有一橫向寬度; 在該重分佈層之該第一側上之一第一晶粒,該第一晶粒具有一最上表面、一最下表面、在該最上表面及該最下表面之間之一第一側表面及一第二側表面,該第二側表面係相對於該第一側表面; 在該重分佈層之該第一側之一模製,該模製橫向地鄰接至該第一晶粒之該第一側表面及該第二側表面且與該第一晶粒之該第一側表面及該第二側表面接觸,該模製具有與該第一晶粒之該最上表面共平面之一最上表面,並且該模製具有與該重分佈層之該橫向寬度相同之橫向寬度; 一第一穿模通孔,其在該模製中並且從該第一晶粒之該第一側表面橫向間隔分開; 一第二穿模通孔,其在該模製中並且從該第一晶粒之該第二側表面橫向間隔分開; 一介電層,其在該模製及該第一晶粒上,該介電層具有相同於該模製之橫向寬度之一橫向寬度,並且該介電層具有一最上表面; 一第二晶粒,其在該介電層中,該第二晶粒直接地電氣連接至該第一穿模通孔及直接地電氣連接至該第二穿模通孔,該第二晶粒具有與該介電層之該最上表面共平面之一最上表面;及 複數個焊球,其在該重分佈層之該第二側上。
- 如請求項16之裝置,其中該第二晶粒包含隱蔽進入該第一穿模通孔之一第一傳導凸塊,並且該第二晶粒包含隱蔽進入至該第二穿模通孔之一第二傳導凸塊。
- 如請求項16之裝置,其中該等複數個焊球之一或多者係垂直地在該第一晶粒下方。
- 如請求項16之裝置,其中該第一晶粒之一中心係從該第二晶粒之一中心橫向地偏移。
- 如請求項16之裝置,其進一步包含: 一第三穿模通孔,其在該模製中且從該第二穿模通孔橫向間隔分開,其中該第二晶粒係直接地電氣連接至該第三穿模通孔。
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